Some clients have a requirement to sandbox memory mappings for security and
advanced features like SVM. This series adds support to enable per-instance
pagetables as auxiliary domains in the arm-smmu driver and adds per-instance
support for the Adreno GPU.
This patchset builds on the split pagetab
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/d
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/d
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
---
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
---
dri
Attempt to enable split pagetables if the arm-smmu driver supports it.
This will move the default address space from the default region to
the address range assigned to TTBR1. The behavior should be transparent
to the driver for now but it gets the default buffers out of the way
when we want to sta
Everywhere an IOMMU object is created by msm_gpu_create_address_space
the IOMMU device is attached immediately after. Instead of carrying around
the infrastructure to do the attach from the device specific code do it
directly in the msm_iommu_init() function. This gets it out of the way for
more ag
This is another iteration for the split pagetable support based on the
suggestions from Robin and Will [1].
Background: In order to support per-context pagetables the GPU needs to enable
split tables so that we can store global buffers in the TTBR1 space leaving the
GPU free to program the TTBR0 r
Refactor how address space initialization works. Instead of having the
address space function create the MMU object (and thus require separate but
equal functions for gpummu and iommu) use a single function and pass the
MMU struct in. Make the generic code cleaner by using target specific
functions
Hi,
On Tue, Jan 28, 2020 at 06:54:44PM +0530, Harigovindan P wrote:
> Add display, DSI hardware DT nodes for sc7180.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v1:
> -Added display DT nodes for sc7180
> Changes in v2:
> -Renamed node names
> -Corrected code alignme
Hi,
On Tue, Jan 28, 2020 at 07:06:57PM +0530, Harigovindan P wrote:
> Adding dsi controller and phy entries for idp dt.
>
> Signed-off-by: Harigovindan P
> ---
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 56
> +
> 1 file changed, 56 insertions(+)
>
> diff --git
On Mon, Jan 27, 2020 at 02:29:53PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 27, 2020 at 1:30 AM Sharat Masetty
> wrote:
> >
> > This patch adds the required dt nodes and properties
> > to enabled A618 GPU.
> >
> > Signed-off-by: Sharat Masetty
> > ---
> > arch/arm64/boot/dts/qcom/sc71
Adding dsi controller and phy entries for idp dt.
Signed-off-by: Harigovindan P
---
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 56 +
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
in
Add display, DSI hardware DT nodes for sc7180.
Signed-off-by: Harigovindan P
---
Changes in v1:
-Added display DT nodes for sc7180
Changes in v2:
-Renamed node names
-Corrected code alignments
-Removed extra new line
-Added DISP AHB clock for register acce
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