Hi,
I'm also curious about why the CSUM_IP was removed in all the intel NICs.
Although this thread is very old, I still need the answer because IP checksum
offload is actually supported in intel's datasheet.
Thanks!
2012-04-14
beezarliu
发件人： YongHyeon PYUN
发送时间： 2011-09-18
Hi,
On Mon, Sep 19, 2011 at 12:59 PM, YongHyeon PYUN wrote:
> On Mon, Sep 19, 2011 at 10:17:22AM -0400, Arnaud Lacombe wrote:
>> Hi,
>>
>> On Mon, Sep 19, 2011 at 5:28 AM, Adrian Chadd wrote:
>> > Arnaud (and others),
>> >
>> > Liaising with vendors is not an easy task. The reason why Intel (and
On Mon, Sep 19, 2011 at 10:17:22AM -0400, Arnaud Lacombe wrote:
> Hi,
>
> On Mon, Sep 19, 2011 at 5:28 AM, Adrian Chadd wrote:
> > Arnaud (and others),
> >
> > Liaising with vendors is not an easy task. The reason why Intel (and
> > other vendors) don't supply detailed history and reasoning for t
>>> The data sheet for intel 82576 advertises IP TX/RX checksum offload
>>> but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean
>>> that driver (and chip) do not support IP TX checksum offload or the
>>> support for TX is not yet included
Hi,
On Mon, Sep 19, 2011 at 5:28 AM, Adrian Chadd wrote:
> Arnaud (and others),
>
> Liaising with vendors is not an easy task. The reason why Intel (and
> other vendors) don't supply detailed history and reasoning for their
> development efforts is that their engineers are likely tasked with
> "m
On Sunday, September 18, 2011 10:48:32 pm Arnaud Lacombe wrote:
> As the PCI spec is not public, I've not been able to find out from the
> few public datasheet how the PCI MSI-X capability field is first
> programmed. I'd assume that the BIOS is using the data in the NVM to
> program it at power up
Hooman Fazaeli wrote:
> >> >> >> Hi list,
> >> >> >>
> >> >> >> The data sheet for intel 82576 advertises IP TX/RX checksum
> offload
> >> >> >> but the driver does not set CSUM_IP in ifp->if_hwassist. Do
Arnaud (and others),
Liaising with vendors is not an easy task. The reason why Intel (and
other vendors) don't supply detailed history and reasoning for their
development efforts is that their engineers are likely tasked with
"making it work" versus "writing lots of stuff down for public
release."
It is interesting that how a thread goes off topic!
Anyway, I will appreciate if folks, especially Jack, provide
a firm comment on the original question: Does intel chips (specifically 82576)
support IP TX checksum offload? If so, why the driver does not support it?
On 9/19/2011 8:59 AM, Jack
Hi,
On Mon, Sep 19, 2011 at 12:29 AM, Jack Vogel wrote:
> [...]
> If you notice, the Linux driver did not enable multiqueue on the hardware
> either, so do you think a whole department of software engineers backed
> by the hardware engineers who designed the damn thing might have had
> a reason?
t; >> Hi,
>> >>
>> >> On Sat, Sep 17, 2011 at 4:32 PM, YongHyeon PYUN wrote:
>> >> > On Sat, Sep 17, 2011 at 11:57:10AM +0430, Hooman Fazaeli wrote:
>> >> >> Hi list,
>> >> >>
>> >> >> The data
.. and believe me, lots of people will appreciate it if you can
verify/diagnose issues. :)
Adrian
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n PYUN wrote:
> >> > On Sat, Sep 17, 2011 at 11:57:10AM +0430, Hooman Fazaeli wrote:
> >> >> Hi list,
> >> >>
> >> >> The data sheet for intel 82576 advertises IP TX/RX checksum offload
> >> >> but the driver does not set
On Sun, Sep 18, 2011 at 5:23 PM, Dieter BSD wrote:
>> The data sheet for intel 82576 advertises IP TX/RX checksum offload
>> but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean that
>> driver (and chip) do not support IP TX checksum offload or the support
> The data sheet for intel 82576 advertises IP TX/RX checksum offload
> but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean that
> driver (and chip) do not support IP TX checksum offload or the support for
> TX is not yet included in the driver?
The first
gt; >> Hi list,
>> >>
>> >> The data sheet for intel 82576 advertises IP TX/RX checksum offload
>> >> but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean
>> >> that
>> >> driver (and chip) do not support IP TX
On Sun, Sep 18, 2011 at 03:19:46PM -0400, Arnaud Lacombe wrote:
> Hi,
>
> On Sat, Sep 17, 2011 at 4:32 PM, YongHyeon PYUN wrote:
> > On Sat, Sep 17, 2011 at 11:57:10AM +0430, Hooman Fazaeli wrote:
> >> Hi list,
> >>
> >> The data sheet for intel
Hi,
On Sat, Sep 17, 2011 at 4:32 PM, YongHyeon PYUN wrote:
> On Sat, Sep 17, 2011 at 11:57:10AM +0430, Hooman Fazaeli wrote:
>> Hi list,
>>
>> The data sheet for intel 82576 advertises IP TX/RX checksum offload
>> but the driver does not set CSUM_IP in ifp->if
On Sat, Sep 17, 2011 at 11:57:10AM +0430, Hooman Fazaeli wrote:
> Hi list,
>
> The data sheet for intel 82576 advertises IP TX/RX checksum offload
> but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean that
> driver (and chip) do not support IP TX check
Hi list,
The data sheet for intel 82576 advertises IP TX/RX checksum offload
but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean that
driver (and chip) do not support IP TX checksum offload or the support for
TX is not yet included in the dri
At Fri, 21 May 2004 17:58:00 +0400,
Yar Tikhiy wrote:
>
> Hi folks,
>
> While sweeping network interface drivers for incorrect usage of the
> capabilities framework, I noticed some bugs in bge(4). Unfortunately,
> I have no such card and I don't know its internals. Therefore I
> made a patch fi
While on the subject of bge any idea why it performs so poorly in 100Mb mode
when compared to the humble fxp in the following results.
FreeBSD 5.1.2 (i386)
local: 22834.872368421 records per second
fxp 100Mb: 3854.06863517 records per second
bge 100Mb: 2501.66999862 records per second
bge 1Gb: 32
On Fri, May 21, 2004 at 11:11:41PM +0900, George V.Neville-Neil wrote:
> >
> > While sweeping network interface drivers for incorrect usage of the
> > capabilities framework, I noticed some bugs in bge(4). Unfortunately,
> > I have no such card and I don't know its internals. Therefore I
> > mad
Hi folks,
While sweeping network interface drivers for incorrect usage of the
capabilities framework, I noticed some bugs in bge(4). Unfortunately,
I have no such card and I don't know its internals. Therefore I
made a patch fixing hw-independent bugs and marking some questionable
spots. It wou
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