"E.B. Dreger" wrote:
>
> > Date: Fri, 29 Jun 2001 21:44:43 -0500
> > From: Michael C . Wu <[EMAIL PROTECTED]>
> >
> > The issue is a lot more complicated than what you think.
>
> How so? I know that idleproc and the new ipending / threaded INTs
> enter the picture... and, after seeing the "HLT
> Date: Fri, 29 Jun 2001 21:44:43 -0500
> From: Michael C . Wu <[EMAIL PROTECTED]>
>
> The issue is a lot more complicated than what you think.
How so? I know that idleproc and the new ipending / threaded INTs
enter the picture... and, after seeing the "HLT benchmark" page, it
would appear that
On Fri, Jun 29, 2001 at 09:14:06PM +, E.B. Dreger scribbled:
| > Date: Fri, 29 Jun 2001 13:14:58 -0700
| > From: Matthew Rogers <[EMAIL PROTECTED]>
The issue is a lot more complicated than what you think.
This actually is a big issue in our future SMP implementation.
There are two types of p
> Date: Fri, 29 Jun 2001 13:14:58 -0700
> From: Matthew Rogers <[EMAIL PROTECTED]>
>
> Why not just use First in line, Next processor available ? Then you
> wouldn't care what processor did which task.
That was my question: Would the added complexity of "CPU affinity
hinting" be worth the reduc
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