New patch description for v3 patch
update upstream MAINTAINERS mail list
New patch description for v2 patch
Missing declaration for i variable in function
it6505_irq_video_error_handler
, add it by this patch
Origianl description for v1 patch
drm/brid
From: kuro chung
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus
From: Kuro Chung
New patch description for v4 patch
update by reviewer Pin-yen Lin comment, remove function
it6505_irq_video_fifo_error/it6505_irq_io_latch_fifo_overflow
update by reviewer Pin-yen Lin comment, update Signed-off-by column
New patch description for v3 patch
From: Kuro
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus, it6505
From: kuro chung
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus
From: kuro chung
New patch description for v2 patch
Missing declaration for i variable in function
it6505_irq_video_error_handler
, add it by this patch
Origianl description for v1 patch
drm/bridge: it6505: fix hibernate to resume no display issue
ITE added
From: kuro chung
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus
From: Kuro
New patch description for v8 patch
resolve merge conflict
New patch description for v7 patch
modify code from
it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x02); to
it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET
From: Kuro
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus, it6505
From: Kuro Chung
This patch added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output
module
From: Kuro Chung
This patch added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output
module rising
From: Kuro Chung
When the system power resumes, the TTL input of IT6505 may experience
some noise before the video signal stabilizes, necessitating a video
reset. This patch has been implemented to prevent a loop of video error
interrupts, which can occur when a video reset in the video FIFO
From: Kuro Chung
When the system power resumes, the TTL input of IT6505 may experience
some noise before the video signal stabilizes, necessitating a video
reset. This patch is implemented to prevent a loop of video error
interrupts, which can occur when a video reset in the video FIFO error
From: Kuro Chung
When the system power resumes, the TTL input of IT6505 may experience
some noise before the video signal stabilizes, necessitating a video
reset. This patch is implemented to prevent a loop of video error
interrupts, which can occur when a video reset in the video FIFO error
From: Kuro
New patch description for v5 patch
after customer feedback and test finished, update again, kernel build
pass.
New patch description for v4 patch
update by reviewer Pin-yen Lin comment, remove function
it6505_irq_video_fifo_error
From: Kuro
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus, it6505
From: Kuro
New patch description for v6 patch
remove the unrelated patch change (split into anoter patch)
remove extra line
New patch description for v5 patch
after customer feedback and test finished, update again, kernel build
pass.
New patch description
From: Kuro
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus, it6505
From: Kuro
New patch description for v7 patch
modify code from
it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x02); to
it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET,
TX_FIFO_RESET); for macro define
New patch description for v6 patch
From: Kuro
ITE added a FIFO reset bit for input video. When system power resume,
the TTL input of it6505 may get some noise before video signal stable
and the hardware function reset is required.
But the input FIFO reset will also trigger error interrupts of output module
rising.
Thus, it6505
From: Kuro Chung
The spec of timing between IVDD/OVDD and SYSRTEN is 10ms, but SYSRSTN RC
circuit need at least 25ms for rising time, update for match spec
Signed-off-by: Kuro Chung
Signed-off-by: Hermes Wu
---
drivers/gpu/drm/bridge/ite-it6505.c | 2 +-
1 file changed, 1 insertion(+), 1
From: allen chen
Change-Id: Iaa3cd9da92a625496f579d87d0ab74ca9c4937c4
---
drivers/gpu/drm/bridge/ite-it6505.c | 42 ++---
1 file changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c
b/drivers/gpu/drm/bridge/ite-it6505.c
index b53da9
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