From: Kuro Chung <kuro.ch...@ite.com.tw>
The spec of timing between IVDD/OVDD and SYSRTEN is 10ms, but SYSRSTN RC
circuit need at least 25ms for rising time, update for match spec
Signed-off-by: Kuro Chung <kuro.ch...@ite.com.tw>
Signed-off-by: Hermes Wu <hermes...@ite.com.tw>
---
drivers/gpu/drm/bridge/ite-it6505.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c
b/drivers/gpu/drm/bridge/ite-it6505.c
index cd1b5057ddfb4..1e1c06fdf2064 100644
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@ -2615,7 +2615,7 @@ static int it6505_poweron(struct it6505 *it6505)
gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
usleep_range(1000, 2000);
gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
- usleep_range(10000, 20000);
+ usleep_range(25000, 35000);
}
it6505->powered = true;
--
2.25.1
