On 2021-07-21 19:42, Bjorn Andersson wrote:
reg was defined as one region covering the entire DP block, but the
memory map is actually split in 4 regions and obviously the size of
these regions differs between platforms.
Switch the reg to require that all four regions are specified instead.
It i
On 2021-07-21 19:42, Bjorn Andersson wrote:
The non-devres version of ioremap is used, which requires manual
cleanup. But the code paths leading here is mixed with other devres
users, so rely on this for ioremap as well to simplify the code.
Signed-off-by: Bjorn Andersson
Reviewed-by: Abhinav
On 2021-07-21 19:42, Bjorn Andersson wrote:
In order to deal with multiple memory ranges in the following commit
change the ioremap wrapper to not poke directly into the dss_io_data
struct.
Signed-off-by: Bjorn Andersson
I think we can squash this one and the next patch into one.
Because the A
On 2021-07-21 19:42, Bjorn Andersson wrote:
Not all platforms has DP_P0 at offset 0x1000 from the beginning of the
DP block. So dss_io_data into representing each of the sub-regions, to
make it possible in the next patch to specify each of the sub-regions
individually.
Signed-off-by: Bjorn Ander
On 2021-07-21 19:42, Bjorn Andersson wrote:
Not all platforms has P0 at an offset of 0x1000 from the base address,
so add support for specifying each sub-region in DT. The code falls
back
to the predefined offsets in the case that only a single reg is
specified, in order to support existing DT.
On 2021-07-24 21:24, Bjorn Andersson wrote:
As the Qualcomm DisplayPort driver only supports a single instance of
the driver the commonly used struct dp_display is kept in a global
variable. As we introduce additional instances this obviously doesn't
work.
Replace this with a combination of exis
Hi Bjorn
On 2021-07-24 21:24, Bjorn Andersson wrote:
The current implementation supports a single DP instance and the DPU
code will
only match it against INTF_DP instance 0. These patches extends this to
allow
multiple DP instances and support for matching against DP instances
beyond 0.
This
On 2021-07-14 23:51, Vinod Koul wrote:
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul
---
Changes since RFC:
- Drop the
On 2021-07-14 23:51, Vinod Koul wrote:
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
---
Changes since RFC:
- Drop unused enums
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/
On 2021-07-14 23:51, Vinod Koul wrote:
In SDM845, DSC can be enabled by writing to pingpong block registers,
so
add support for DSC in hw_pp
Signed-off-by: Vinod Koul
Reviewed-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
.../gpu/drm/msm/disp
On 2021-07-14 23:51, Vinod Koul wrote:
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 32 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 files
On 2021-07-14 23:51, Vinod Koul wrote:
This add SDM845 DSC blocks into hw_catalog
/add --> adds
Signed-off-by: Vinod Koul
---
Changes since RFC:
- use BIT values from MASK
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 22 +++
1 file changed, 22 insertions(+)
diff --git a
On 2021-07-14 23:51, Vinod Koul wrote:
Later gens of hardware have DSC bits moved to hw_ctl, so configure
these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul
Please correct me if wrong but here you seem to be flushing all the DSC
bits
even the unused ones. This will end-
On 2021-07-14 23:51, Vinod Koul wrote:
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc_mode() to detect dsc
enabled and pass this to .setup_intf_cfg()
This
On 2021-07-14 23:52, Vinod Koul wrote:
When DSC is enabled in DT, we need to configure the encoder for DSC
configuration, calculate DSC parameters for the given timing.
This patch adds that support by adding dpu_encoder_prep_dsc() which is
invoked when DSC is enabled in DT
correct me if wrong bu
On 2021-07-14 23:52, Vinod Koul wrote:
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions upto 4k. For more resolutions like 8k this
won't
work.
The topology information is provided by DTS so we try to deduce the
topology required for DSC.
Furthermore,
On 2021-07-14 23:52, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-of
On 2021-07-14 23:52, Vinod Koul wrote:
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Signed-off-by: Vinod Koul
based on the comments on prev patches in the series, this will need to
be reworked
On 2021-08-03 02:06, Thomas Zimmermann wrote:
Drop the DRM IRQ midlayer in favor of Linux IRQ interfaces. DRM's
IRQ helpers are mostly useful for UMS drivers. Modern KMS drivers
don't benefit from using it.
DRM IRQ callbacks are now being called directly or inlined.
Signed-off-by: Thomas Zimmer
On 2021-04-07 01:23, Zhen Lei wrote:
Fixes the following W=1 kernel build warning:
drivers/gpu/drm/msm/dp/dp_display.c: In function
‘dp_display_usbpd_attention_cb’:
drivers/gpu/drm/msm/dp/dp_display.c:496:19: warning: variable ‘hpd’
set but not used [-Wunused-but-set-variable]
Fixes: c58eb1b54f
On 2021-04-07 01:33, Zhen Lei wrote:
Fixes the following W=1 kernel build warning:
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c: In function
‘dpu_encoder_phys_cmd_wait_for_commit_done’:
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c:688:31: warning:
variable ‘cmd_enc’ set but not u
On 2021-04-07 06:06, Bernard Zhao wrote:
This patch fix coccicheck warning:
drivers/gpu/drm/msm/dp/dp_link.c:848:5-8: Unneeded variable: "ret".
Return "0" on line 880
Also remove unneeded function return value check.
Signed-off-by: Bernard Zhao
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm
On 2021-04-07 01:33, Zhen Lei wrote:
Fixes the following W=1 kernel build warning:
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c: In function
‘dpu_encoder_phys_cmd_wait_for_commit_done’:
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c:688:31: warning:
variable ‘cmd_enc’ set but not u
Hi Marijn
On 2021-04-06 14:47, Marijn Suijten wrote:
Leaving this at a close-to-maximum register value 0xFFF0 means it takes
very long for the MDSS to generate a software vsync interrupt when the
hardware TE interrupt doesn't arrive. Configuring this to double the
vtotal (like some downstream k
Hi Rob
Thank you for the review.
On 2021-04-09 13:38, Rob Clark wrote:
On Thu, Apr 8, 2021 at 7:28 PM Abhinav Kumar
wrote:
Add the dpu_dbg module which adds supports to dump dpu registers
which can be used in case of error conditions.
changes in v3:
- Get rid of registration mechanism for
Hi Dmitry
Thanks for the review.
On 2021-04-14 17:16, Dmitry Baryshkov wrote:
On 15/04/2021 02:11, Abhinav Kumar wrote:
Add the msm_disp_snapshot module which adds supports to dump dpu
registers and capture the drm atomic state which can be used in
case of error conditions.
changes in v4:
-
On 2021-04-09 18:19, Dmitry Baryshkov wrote:
The parent_name initialization was lost in refactoring, restore it now.
Fixes: 5d13459650b3 ("drm/msm/dsi: push provided clocks handling into
a generic code")
Reported-by: kernel test robot
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
On 2021-04-11 17:01, Dmitry Baryshkov wrote:
msm_dsi_phy_get_clk_provider() always returns two provided clocks, so
return 0 instead of returning incorrect -EINVAL error code.
Fixes: 5d13459650b3 ("drm/msm/dsi: push provided clocks handling into
a generic code")
Signed-off-by: Dmitry Baryshkov
On 2021-04-25 09:07, Dmitry Baryshkov wrote:
Instead of always getting the disp_state from drm device, pass it as an
argument.
Signed-off-by: Dmitry Baryshkov
This certainly reduces some amount of code, I am onboard with this,
hence:
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/d
On 2021-04-25 09:08, Dmitry Baryshkov wrote:
Instead of allocating snapshotting structure at the driver probe time
and later handling concurrent access, actual state, etc, make
msm_disp_state transient struct. Allocate one when snapshotting happens
and free it after coredump data is read by users
On 2021-04-26 14:23, Dmitry Baryshkov wrote:
On 26/04/2021 23:50, abhin...@codeaurora.org wrote:
On 2021-04-25 09:08, Dmitry Baryshkov wrote:
Instead of allocating snapshotting structure at the driver probe time
and later handling concurrent access, actual state, etc, make
msm_disp_state transi
On 2021-04-26 15:14, Dmitry Baryshkov wrote:
On Tue, 27 Apr 2021 at 01:03, wrote:
On 2021-04-26 14:23, Dmitry Baryshkov wrote:
> On 26/04/2021 23:50, abhin...@codeaurora.org wrote:
>> On 2021-04-25 09:08, Dmitry Baryshkov wrote:
>>> Instead of allocating snapshotting structure at the driver pr
On 2021-04-26 17:18, Dmitry Baryshkov wrote:
Rework MSM coredump support: add DSI PHY registers, simplify
snapshotting code.
Changes since v1:
- Readd mutex serializing register snapshot calls
- Add DSI PHY register dumping support
Need to mention the dependency here , got missed from the p
Hi Dmitry
On 2021-04-26 17:18, Dmitry Baryshkov wrote:
Instead of allocating snapshotting structure at the driver probe time
and later handling concurrent access, actual state, etc, make
msm_disp_state transient struct. Allocate one when snapshotting happens
and free it after coredump data is re
Hi Dmitry
On 2021-04-26 17:18, Dmitry Baryshkov wrote:
Instead of looping throught the resources each time to get the DSI CTRL
area size, get it at the ioremap time.
Signed-off-by: Dmitry Baryshkov
We will have to call into the individual modules anyway everytime we
take a snapshot as only th
On 2021-04-27 13:29, Dmitry Baryshkov wrote:
On Tue, 27 Apr 2021 at 22:19, wrote:
Hi Dmitry
On 2021-04-26 17:18, Dmitry Baryshkov wrote:
> Instead of allocating snapshotting structure at the driver probe time
> and later handling concurrent access, actual state, etc, make
> msm_disp_state tra
On 2021-04-27 13:32, Dmitry Baryshkov wrote:
On Tue, 27 Apr 2021 at 22:30, wrote:
Hi Dmitry
On 2021-04-26 17:18, Dmitry Baryshkov wrote:
> Instead of looping throught the resources each time to get the DSI CTRL
> area size, get it at the ioremap time.
>
> Signed-off-by: Dmitry Baryshkov
We w
On 2021-04-26 17:18, Dmitry Baryshkov wrote:
Add DSI PHY registers to the msm state snapshots to be able to check
their contents.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.c | 1 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drive
On 2021-04-30 12:30, Stephen Boyd wrote:
This patch series attempts to trim down the drm logging in the msm
driver to make it useable with DRM_UT_DRIVER, DRM_UT_KMS, and DRM_UT_DP
levels enabled. Right now the log is really spammy and prints multiple
lines for what feels like every frame. I moved
Hi Marijn
Thanks for reviewing and testing the latest patchset.
On 2021-08-10 15:59, Marijn Suijten wrote:
Hi Abhinav,
On 7/16/21 2:01 AM, abhin...@codeaurora.org wrote:
Hi Marijn
Sorry for the late response.
Apologies from my side as well.
[...]
+static void msm_dsi_host_cmd_test_patt
On 2021-08-05 10:08, Dmitry Baryshkov wrote:
Unlike previous generations, 7nm PHYs are required to collaborate with
the host for conitnuos clock mode. Add changes neccessary to enable
/continuous
/necessary
continuous clock mode in the 7nm DSI PHYs.
Signed-off-by: Dmitry Baryshkov
---
Changes
On 2021-06-28 12:19, Dmitry Baryshkov wrote:
Add support for alpha blending properties. Setup the plane blend state
according to those properties.
Signed-off-by: Dmitry Baryshkov
I think this has already been picked up by Rob but just had a couple of
comments
below.
Also, how has this been
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
With dpu_core_irq being the wrapper around dpu_hw_interrupts, there is
little sense in having them separate. Squash them together to remove
another layer of abstraction (hw_intr ops).
Signed-off-by: Dmitry Baryshkov
Overall, I think this is a reason
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
We already clear the IRQ status register before processing IRQs, so do
not clear the register again. Especially do not clear the IRQ status
_after_ processing the IRQ as this way we can loose the event.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: A
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
As dpu_core_irq was merged into dpu_hw_intr, merge data structures too,
removing the need for a separate data structure.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 51 +--
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
DPU interrupts code allows multiple callbacks per interrut. In reality
/interrupt
none of the interrupts is shared between blocks (and will probably
never
be). Drop support for registering multiple callbacks per interrupt to
simplify interrupt handl
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
Remove extra dpu_irq_* wrappers from dpu_kms.c, merge them directly
into
dpu_core_irq_* functions.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 12 -
.../gpu/drm/msm/disp/
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
Get rid of dpu_encoder_helper_register_irq/unregister_irq helpers, call
dpu_core_register/unregister_callback directly, without surrounding
them
with helpers.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/di
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
Drop the wrapping structures and the enum used to index those
structures
in dpu_kms. Instead of them use IRQ indices and callback functions
directly.
Signed-off-by: Dmitry Baryshkov
Is this change really needed because I think the enum based appro
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
From: Daniel Palmer
Add a devm helper for clk_hw_register_fixed_factor() so that drivers
that internally
register fixed factor clocks for things like dividers don't need to
manually unregister
them on remove or if probe fails.
Signed-off-
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
The only PLL using multiple enable sequences is the 28nm PLL, which
just
does the single step in the loop. Push that support back into the PLL
code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_p
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Add devm_clk_hw_register_mux() - devres-managed version of
clk_hw_register_mux().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/clk/clk-mux.c| 35 +++
include/linux/clk-provider.h |
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Add devm_clk_hw_register_divider() - devres version of
clk_hw_register_divider().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
include/linux/clk-provider.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/i
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits
the amount of data in the struct msm_dsi_pll.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.h | 6 --
drivers/gp
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
DSI PHY init callback would either map dsi_phy_regulator or
dsi_phy_lane
depending on the PHY type. Replace those callbacks with configuration
options governing mapping those regions.
Signed-off-by: Dmitry Baryshkov
This is a nice cleanup which wil
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
With the current upstream driver the msm_dsi_phy_type enum does not
make
much sense: all DSI PHYs are probed using the dt bindings, the phy type
is not passed between drivers. Use quirks in phy individual PHY drivers
to differentiate minor harware dif
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 6 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 6 --
driv
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
msm_dsi_pll_set_usecase() function is not used outside of individual
DSI
PHY drivers, so drop it in favour of calling the the respective
set_usecase functions directly.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/d
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping this
manual
setup allows us to drop repeating code and to move registration of hw
clock providers to generic
Hi Dmitry
On 2021-03-26 13:36, Dmitry Baryshkov wrote:
On 26/03/2021 21:05, abhin...@codeaurora.org wrote:
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping t
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
From: Daniel Palmer
Add a devm helper for clk_hw_register_fixed_factor() so that drivers
that internally
register fixed factor clocks for things like dividers don't need to
manually unregister
them on remove or if probe fails.
Signed-off-by: Daniel
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
All MSM DSI PHYs provide two clocks: byte and pixel ones.
Register/unregister provided clocks from the generic place, removing
boilerplate code from all MSM DSI PHY drivers.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/g
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
Use devres-enabled version of clock registration functions. This lets
us
remove dsi_pll destroy callbacks completely.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.h | 4 -
drivers/gp
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
Use devm_of_clk_add_hw_provider() to register provided clocks. This
allows dropping the remove function alltogether.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 22 +-
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
Morph msm_dsi_pll_save/restore_state() into
msm_dsi_phy_save/restore_state(),
thus removing last bits of knowledge about msm_dsi_pll from
dsi_manager.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 18 ++-
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
These drivers do not use vco_delay variable, so drop it from all of
them.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 ---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4
driv
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
Instead of setting the variable and then using it just in the one
place,
determine vco_delay directly at the PLL configuration time.
Signed-off-by: Dmitry Baryshkov
The subject line should still be "drm/msm/dsi" and not "drm/msm/dpu".
Once thats fi
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
10nm and 7nm already do not use these helpers, as they handle setting
slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to
remove unnecessary indirection and drop enable_seq/disable_seq PLL
callbacks.
Signed-off-by: Dmitry Baryshkov
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
Make save_state/restore callbacks accept struct msm_dsi_phy rather than
struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing
us to drop struct msm_dsi_pll_ops.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_ph
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw
directly into struct msm_dsi_phy.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/Kconfig | 8 --
drivers/gpu/drm/msm/Makefil
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY
accessors, reducing duplication.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 24 +--
drivers/gpu/drm/msm/dsi
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
All PHY drivers would map dsi_pll area. Some PHY drivers would also
map dsi_phy area again (a leftover from old PHY/PLL separation). Move
all ioremaps to the common dsi_phy driver code and drop individual
ioremapped areas from PHY drivers.
Signed-off-
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse
those fields from the provided msm_dsi_phy.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 72 +--
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
The 7nm, 10nm and 14nm drivers would store interim data used during
VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this
data
structures to the onstack storage. While we are at it, drop
unused/static 'config' data, unused config fields
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.
Signed-off-by: Dmitry Baryshkov
---
driver
On 2021-03-29 20:13, abhin...@codeaurora.org wrote:
On 2021-03-27 04:02, Dmitry Baryshkov wrote:
Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw
directly into struct msm_dsi_phy.
Signed-off-by: Dmitry Baryshkov
Forgot to mention, please fix the typo "abstraction" in the subj
On 2021-03-30 06:42, Dmitry Baryshkov wrote:
On 30/03/2021 06:34, abhin...@codeaurora.org wrote:
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
The src_truthtable config is not used for some of phys, which use
other
means of configuring the master/slave usecases. Inline this function
with the go
On 2021-03-27 04:03, Dmitry Baryshkov wrote:
Phy driver already knows the source PLL id basing on the set usecase
and
the current PLL id. Stop passing it to the phy_enable call. As a
reminder, dsi manager will always use DSI 0 as a clock master in a
slave
mode, so PLL 0 is always a clocksource
On 2021-03-31 03:57, Dmitry Baryshkov wrote:
Make save_state/restore callbacks accept struct msm_dsi_phy rather than
struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing
us to drop struct msm_dsi_pll_ops.
Signed-off-by: Dmitry Baryshkov
Tested-by: Stephen Boyd # on sc7180 la
On 2021-03-31 03:57, Dmitry Baryshkov wrote:
Phy driver already knows the source PLL id basing on the set usecase
and
the current PLL id. Stop passing it to the phy_enable call. As a
reminder, dsi manager will always use DSI 0 as a clock master in a
slave
mode, so PLL 0 is always a clocksource
On 2021-03-31 03:57, Dmitry Baryshkov wrote:
The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.
Signed-off-by: Dmitry Baryshkov
Tested-by:
On 2021-02-03 15:15, Konrad Dybcio wrote:
The maximum mdp clock rate on msm8974v2 is 320MHz. Fix it.
Signed-off-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/d
On 2021-02-02 19:08, Yang Li wrote:
Eliminate the following coccicheck warning:
./drivers/gpu/drm/msm/dp/dp_ctrl.c:1161:2-3: Unneeded semicolon
Reported-by: Abaci Robot
Signed-off-by: Yang Li
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +-
1 file changed, 1 insertio
Hi Nicolas
On 2021-02-10 19:33, Nicolas Boichat wrote:
Many of the DSI flags have names opposite to their actual effects,
e.g. MIPI_DSI_MODE_EOT_PACKET means that EoT packets will actually
be disabled. Fix this by including _NO_ in the flag names, e.g.
MIPI_DSI_MODE_NO_EOT_PACKET.
Signed-off-by
Hi Dmitry
Thanks for the patch.
On 2021-02-24 15:05, Dmitry Baryshkov wrote:
The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value
directly, but the same value was also being specified in the
dsi_pll_regs struct pll_lockdet_rate variable: let's use it!
Based on 362cadf34b9f ("drm/
Hi Dmitry
Thanks for the patch.
On 2021-02-24 15:01, Dmitry Baryshkov wrote:
The number of fractional registers bits is known and already set in
the frac_bits variable of the dsi_pll_config struct here in 7nm:
remove the TODO by simply using that variable. This is a copy of
196145eb1af1 ("drm/m
On 2021-03-01 13:41, Dmitry Baryshkov wrote:
if GPU components have failed to bind, shutdown callback would fail
with
the following backtrace. Add safeguard check to stop that oops from
happening and allow the board to reboot.
[ 66.617046] Unable to handle kernel NULL pointer dereference at
v
Hi Stephen
Thanks for the review.
I will break this up into patches according to the class of warning to
show the warning in the commit text
and resend the patches.
Abhinav
On 2021-03-04 23:23, Dan Carpenter wrote:
On Thu, Mar 04, 2021 at 10:55:58PM -0800, Stephen Boyd wrote:
> @@ -368,44 +3
Hi Bjorn
I had a quick glance on the series and before getting to other things
wanted to know how you are initializing two different connectors for
DP & EDP resp.
The connector type for DP should be DRM_MODE_CONNECTOR_DisplayPort and
eDP should be DRM_MODE_CONNECTOR_eDP.
We need both to be cr
On 2020-11-23 03:18, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c:28: warning: Function
parameter or member 'hw_blk' not described in 'dpu_hw_blk_init'
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c:120: warning: Excess
function param
On 2020-11-23 03:18, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:124:19: warning:
initialized field overwritten [-Woverride-init]
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:124:19: note: (near
initialization for ‘sm8250_d
On 2020-11-23 03:18, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c:50: warning: Function
parameter or member 'fmt' not described in 'INTERLEAVED_RGB_FMT'
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c:50: warning: Function
parameter
On 2020-11-23 03:18, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:207: warning: Function
parameter or member 'cur_slave' not described in 'dpu_encoder_virt'
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:207: warning: Function
param
On 2020-11-23 03:18, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c:31: warning: Enum value
'DPU_PERF_MODE_MAX' not described in enum 'dpu_perf_mode'
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c:34: warning: Cannot
understand *
On 2020-11-23 03:18, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c:240: warning: Function
parameter or member 'ctx' not described in 'dpu_hw_sspp_setup_format'
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c:240: warning: Function
par
On 2020-11-23 03:18, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c:55: warning: Function
parameter or member 'ctx' not described in '_stage_offset'
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c:55: warning: Excess
function parameter 'c'
On 2020-11-23 03:19, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:152: warning: Function
parameter or member 'plane' not described in '_dpu_plane_calc_bw'
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:152: warning: Function
parameter o
On 2020-11-23 03:19, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:247: warning: Excess function
parameter 'Return' description in '_dpu_rm_check_lm_peer'
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:283: warning: Function
parameter or membe
On 2020-11-23 03:19, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/msm/msm_drv.c:124:15: warning: no previous prototype
for ‘_msm_ioremap’ [-Wmissing-prototypes]
Cc: Rob Clark
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Cc: linux-arm-...@vger.kernel
On 2020-11-23 03:18, Lee Jones wrote:
These tables are not large or overbearing, so moving them into the
source file seems like the right thing to do. The alternative is to
use __maybe_unused, which is undesirable.
Fixes the following W=1 kernel build warning(s):
In file included from
driver
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