On Fri, 2019-07-26 at 19:23 +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Philipp Zabel
Thanks!
regards
Philipp
> ---
> drivers/gpu/drm/imx/imx-ldb.c | 7 ---
>
On Fri, 2019-07-26 at 19:23 +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Philipp Zabel
regards
Philipp
> ---
> drivers/gpu/drm/imx/imx-tve.c | 6 --
> 1 file changed,
_size(struct etnaviv_iommu *iommu)
> +void etnaviv_iommu_dump(struct etnaviv_iommu_context *context, void *buf)
> {
> - return iommu->domain->ops->dump_size(iommu->domain);
> + context->global->ops->dump(context, buf);
> }
>
> -void etnaviv_iommu_dump(struct etnaviv_iommu *iommu, void *buf)
> +extern const struct etnaviv_iommu_ops etnaviv_iommuv1_ops;
> +extern const struct etnaviv_iommu_ops etnaviv_iommuv2_ops;
These should be moved into a header that is also included where the ops
are defined.
Apart from this,
Reviewed-by: Philipp Zabel
regards
Philipp
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prefetch = etnaviv_buffer_init(gpu);
> -
> gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
> - etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer,
> - &gpu->cmdbuf_mapping), prefetch);
> +
> + etnaviv_gpu_start_fe_idleloop(gpu);
> }
>
iv/etnaviv_gem_submit.c
> index 3f4f6ab388de..267ff5863e5d 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
> @@ -224,7 +224,7 @@ static int submit_pin_objects(struct etnaviv_gem_submit
> *submit)
> struct etnaviv_vra
work and has been terminated. Only when the GPU is runtime
> suspended or switches to another clients MMU context is the old context
> freed up.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
I just have two nitpicks below:
> ---
> drivers/gpu/drm/etna
On Wed, 2019-07-31 at 18:58 +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
> Acked-by: Sam Ravnborg
> Reviewed-by: Emil Velikov
Reviewed-by: Philipp Zabel
regards
Philipp
> ---
Hi Christian,
On Wed, 2019-07-31 at 23:29 +0200, Christian Gmeiner wrote:
> Signed-off-by: Christian Gmeiner
> ---
> drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
> b/drivers/gpu/
r contents of imx-ipuv3-crtc.o are built via imxdrm-objs. So
there's no need to keep an extra entry with a non existing config value
(CONFIG_DRM_IMX_IPUV3).
Fixes: 3d1df96ad468 ("drm/imx: merge imx-drm-core and ipuv3-crtc in one
module")
Signed-off-by: Guido G
Hi Guido,
On Fri, 2019-08-02 at 15:39 +0200, Guido Günther wrote:
> Hi Lucas,
> On Fri, Jul 05, 2019 at 07:17:21PM +0200, Lucas Stach wrote:
> > This allows to decouple the cmdbuf suballocator create and mapping
> > the region into the GPU address space. Allowing multiple AS to share
> > a single
gt; + abs(error - 1000) / 10, abs(error - 1000) % 10);
>
> /* Allow a 1% error */
> if (error < 1010 && error >= 990) {
Rounding (always down) is still a bit unintuitive, but this certainly
improves things.
Reviewed-by: Philipp Zabel
regards
Philipp
1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Ethdr Device Tree Bindings
> +
> +maintainers:
> + - Chun-Kuang Hu
> + - Philipp Zabel
> +
> +descript
On Sa, 2022-04-16 at 10:07 +0800, Nancy.Lin wrote:
> Add merge async reset control in mtk_merge_stop. Async hw doesn't do self
> reset on each sof signal(start of frame), so need to reset the async to
> clear the hw status for the next merge start.
>
> Signed-off-by: Nancy.Lin
> Reviewed-by: CK H
On Sa, 2022-04-16 at 10:07 +0800, Nancy.Lin wrote:
> ETHDR is a part of ovl_adaptor.
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combine
> dif
Hi Dave, Daniel,
The following changes since commit 3123109284176b1532874591f7c81f3837bbdc17:
Linux 5.18-rc1 (2022-04-03 14:08:21 -0700)
are available in the Git repository at:
git://git.pengutronix.de/pza/linux.git tags/imx-drm-next-2022-05-04
for you to fetch changes up to 927d8fd465adba
dev,
> if (IS_ERR(gpu->gpu_cx))
> gpu->gpu_cx = NULL;
>
> + gpu->cx_collapse = devm_reset_control_get_optional(&pdev->dev,
> + "cx_collapse");
Please use devm_reset_control_get_optional_exclusive() instead.
With that,
Reviewed-by: Philipp Zabel
regards
Philipp
On Mi, 2022-06-29 at 14:34 +0200, Maxime Ripard wrote:
> The DRM-managed function to register an encoder is
> drmm_encoder_alloc() and its variants, which will allocate the underlying
> structure and initialisation the encoder.
>
> However, we might want to separate the structure creation and the
f Kozlowski
> Tested-by: AngeloGioacchino Del Regno
>
Acked-by: Philipp Zabel
regards
Philipp
On Mo, 2022-06-27 at 14:47 +0200, Lucas Stach wrote:
There are two events that signal a real change of the link state: HPD going
high means the sink is newly connected or wants the source to re-read the
EDID, RX sense going low is a indication that the link has been disconnected.
Ignore the other
Hi Dave, Daniel,
The following changes since commit 3123109284176b1532874591f7c81f3837bbdc17:
Linux 5.18-rc1 (2022-04-03 14:08:21 -0700)
are available in the Git repository at:
git://git.pengutronix.de/pza/linux.git tags/imx-drm-fixes-2022-04-06
for you to fetch changes up to 070a88fd4a03f
Hi Lucas,
On Mi, 2022-04-06 at 18:01 +0200, Lucas Stach wrote:
> This adds the driver for the Samsung HDMI PHY found on the
> i.MX8MP SoC.
>
> Heavily based on the PHY implementation in the downstream kernel
> written by Sandor Yu , but also cleaned up
> quite a bit and extended to support runtim
On Mi, 2022-04-06 at 18:01 +0200, Lucas Stach wrote:
> Add a simple wrapper driver for the DWC HDMI bridge driver that
> implements the few bits that are necessary to abstract the i.MX8MP
> SoC integration.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
On Mi, 2022-04-06 at 18:01 +0200, Lucas Stach wrote:
> This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a
> full timing generator and can switch between different video sources. On
> the i.MX8MP however the only supported source is the LCDIF. The block
> just needs to be powe
Hi Akhil,
On Wed, Aug 31, 2022 at 10:48:23AM +0530, Akhil P Oommen wrote:
> Allow soc specific clk drivers to specify a custom reset operation. We
> will use this in an upcoming patch to allow gpucc driver to specify a
> differet reset operation for cx_gdsc.
>
> Signed-off-by: Akhil P Oommen
> R
On Wed, Aug 31, 2022 at 10:48:24AM +0530, Akhil P Oommen wrote:
> Add a reset op compatible function to poll for gdsc collapse.
>
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Minor update to function prototype
>
> driv
On Wed, Aug 31, 2022 at 10:48:25AM +0530, Akhil P Oommen wrote:
> Allow a consumer driver to poll for cx gdsc collapse through Reset
> framework.
>
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Convert 'struct qcom_reset_
Hi Lucas,
On Do, 2022-09-15 at 16:19 +0200, Lucas Stach wrote:
> While the interface for the MMU mapping takes phys_addr_t to hold a
> full 64bit address when necessary and MMUv2 is able to map physical
> addresses with up to 40bit, etnaviv_iommu_map() truncates the address
> to 32bits. Fix this b
his by using the correct type.
>
> Fixes: 931e97f3afd8 ("drm/etnaviv: mmuv2: support 40 bit phys address")
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
Hi Laurent,
On Fri, 2019-11-01 at 10:43 +0200, Laurent Pinchart wrote:
> Hello,
>
> I'm looking at the available options to support overlays in the display
> pipeline of the i.MX7. The LCDIF itself unfortunaltey doesn't support
> overlays, the feature being implemented in the PXP. A driver for th
On Fri, 2019-10-18 at 10:43 -0400, Drew DeVault wrote:
> Regarding hotplugging, the Wayland compositor is probably keeping track
> of hotplugs itself and withdrawing/offering connectors as appropriate.
>
> Also, when the lease is issued, the compositor withdraws that connector.
> For the client, up
Hi Laurentiu,
On Fri, 2019-12-06 at 11:52 +0200, Laurentiu Palcu wrote:
> Add bindings for iMX8MQ Display Controller Subsystem.
>
> Signed-off-by: Laurentiu Palcu
> Reviewed-by: Rob Herring
> ---
> .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 86
> ++
> 1 file chan
way would be great if you at least check out what the new drm
> managed resource stuff would mean for imx here, since you're blowing
> on devm_kzalloc exactly in the way that I'm trying to get sorted now
> (without tons of explicit kfree() everywhere).
I concur.
le driver data.
>
> Cc: Philipp Zabel
> Signed-off-by: Maxime Ripard
This shoulod be done in such a way that simple reset drivers which do
not set the reset delay continue to return -ENOTSUPP from
reset_control_reset().
> ---
> drivers/reset/reset-simple.c | 21 +
Hi Laurentiu,
On Fri, 2020-03-06 at 11:58 +0200, Laurentiu Palcu wrote:
> On Wed, Feb 26, 2020 at 02:19:11PM +0100, Lucas Stach wrote:
[...]
> > > +/* This function will be called from interrupt context. */
> > > +void dcss_scaler_write_sclctrl(struct dcss_scaler *scl)
> > > +{
> > > + int chnum;
if the DI provides no formats. Similarly for bus_flags, which
> are set from imxpd->bus_flags only if the DI provides no formats.
>
> Signed-off-by: Marek Vasut
> Cc: Daniel Vetter
> Cc: David Airlie
> Cc: Fabio Estevam
> Cc: NXP Linux Team
> Cc: Philipp Zabel
> Cc: S
> Cc: Daniel Vetter
> Cc: David Airlie
> Cc: Fabio Estevam
> Cc: NXP Linux Team
> Cc: Philipp Zabel
> Cc: Sascha Hauer
> Cc: Shawn Guo
> Cc: linux-arm-ker...@lists.infradead.org
> To: dri-devel@lists.freedesktop.org
> ---
> V2: Rebase on next, upda
imxpd->bus_flags;
> +
> + bus_fmt = bridge_state->input_bus_cfg.format;
> + if (!imx_pd_format_supported(bus_fmt))
> + return -EINVAL;
> +
> + if (bus_flags &
> + ~(DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_DE_HIGH |
> +
Hi Boris,
On Wed, 2019-10-23 at 17:45 +0200, Boris Brezillon wrote:
> Now that bridges can expose the bus format/flags they expect, we can
> use those instead of the relying on the display_info provided by the
> connector (which is only valid if the encoder is directly connected
> to bridge elemen
On Wed, 2019-08-21 at 19:42 +0200, Guido Günther wrote:
> Hi,
> On Tue, Aug 13, 2019 at 01:07:52PM +0200, Arnd Bergmann wrote:
> > On Tue, Aug 13, 2019 at 12:10 PM Guido Günther wrote:
> > > On Tue, Aug 13, 2019 at 10:08:44AM +0200, Arnd Bergmann wrote:
> > > > On Fri, Aug 9, 2019 at 6:24 PM Guido
.
Guido Günther (1):
drm/imx: Drop unused imx-ipuv3-crtc.o build
Philipp Zabel (9):
gpu: ipu-v3: enable remaining 32-bit RGB V4L2 pixel formats
gpu: ipu-v3: image-convert: enable V4L2_PIX_FMT_BGRX32 and _RGBX32
gpu: ipu-v3: image
Hi Boris,
On Mon, 2019-08-26 at 17:26 +0200, Boris Brezillon wrote:
> Now that bridges can expose the bus format/flags they expect, we can
> use those instead of the relying on the display_info provided by the
> connector (which is only valid if the encoder is directly connected
> to bridge elemen
On Tue, 2019-08-27 at 10:43 +0200, Boris Brezillon wrote:
[...]
> > > +static void
> > > +imx_pd_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
> > > + struct drm_bridge_state *bridge_state,
> > > + struct drm_crtc_stat
On Tue, 2019-08-27 at 11:57 +0200, Boris Brezillon wrote:
> On Tue, 27 Aug 2019 11:23:02 +0200
> Philipp Zabel wrote:
> > On Tue, 2019-08-27 at 10:43 +0200, Boris Brezillon wrote:
[...]
> > Absolutely. This was just a cosmetic remark. I'm suggesting to put this
> > b
On Tue, 2019-08-27 at 15:20 +0200, Boris Brezillon wrote:
> On Tue, 27 Aug 2019 14:51:20 +0200
> Philipp Zabel wrote:
>
> > [...]
> > > > > I can do that if you like. Note that we are forwarding
> > > > > the ->output_bus_cfg.fmt value to the I
te_one(gpu, stream, args->stream_size / 4,
> + if ((priv->mmu_global->version != ETNAVIV_IOMMU_V2) &&
> + !etnaviv_cmd_validate_one(gpu, stream, args->stream_size / 4,
> relocs, args->nr_relocs)) {
>
h
Reviewed-by: Philipp Zabel
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gem.c | 2 +-
> drivers/gpu/drm/etnaviv/etnaviv_gem.h | 2 +-
> drivers/gpu/drm/etnaviv/etnaviv_mmu.c | 16 ++--
> drivers/gpu/drm/etnaviv/etnaviv_mmu.h | 2 +-
> 4 files changed, 17 insertions(+
0x02
The presumed field of drm_etnaviv_gem_submit_bo has an elaborate comment
on its supposed pre-softpin use in etnaviv_drm.h, maybe that should be
updated.
Otherwise,
Reviewed-by: Philipp Zabel
regards
Philipp
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re is no direct replacement.
> We may be able to just check that drm_panel_get_modes() return > 0,
> but as this is not the same functionality it is left for later.
>
> Signed-off-by: Sam Ravnborg
> Cc: Philipp Zabel
> Cc: Sascha Hauer
> Cc: Pengutronix Kernel Team
> Cc: Fa
}
> + count = drm_panel_get_modes(tc->panel);
> + if (count > 0)
> + return count;
>
> edid = drm_get_edid(connector, &tc->aux.ddc);
Reviewed-by: Philipp Zabel
regards
Philipp
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On Mon, 2019-08-05 at 14:23 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Make use of the newly added drm_dp_aux_rd_interval() helper in existing
> DP link training helpers and add comments about minimum required delays
> mandated by the DP specification.
This patch does not add any co
On Mon, 2019-08-05 at 14:23 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Remove a gratuituous blank line in one place and add a blank line in
> another to improve readability.
Seems like the comment description is outdated here as well.
> Signed-off-by: Thierry Reding
> ---
> drive
On Mon, 2019-08-05 at 14:23 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Use existing parsing helpers to probe a DisplayPort link.
>
> Signed-off-by: Thierry Reding
Reviewed-by: Philipp Zabel
regards
Philipp
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>
> Signed-off-by: Thierry Reding
Reviewed-by: Philipp Zabel
regards
Philipp
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On Mon, 2019-08-05 at 14:23 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Use microsecond sleeps for the clock recovery and channel equalization
> delays during link training. The duration of these delays can be from
> 100 us up to 16 ms. It is rude to busy-loop for that amount of time.
> Add a helper to extract these adjustments on a per-lane basis from the
> DPCD link status.
>
> Signed-off-by: Thierry Reding
Reviewed-by: Philipp Zabel
regards
Philipp
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- iter.start);
>
> etnaviv_core_dump_registers(&iter, gpu);
> - etnaviv_core_dump_mmu(&iter, gpu, mmu_size);
> + etnaviv_core_dump_mmu(&iter, gpu->mmu, mmu_size);
> +
I'd split this into a separate commit, or at least mention it in the
comm
On Fri, 2019-08-09 at 14:03 +0200, Lucas Stach wrote:
> This function does only need the mmu part part of the gpu struct.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
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> check if the TLB is in sync with the current page table state for each GPU.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
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work and has been terminated. Only when the GPU is runtime
> suspended or switches to another clients MMU context is the old context
> freed up.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
_
termediate tile size limit is not exceeded, calculate the number of
tiles from the maximum of intermediate size and output size and avoid
unnecessary downsizing.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 49 --
1 file changed, 31 inserti
Burst aligned input and output width can be calculated once per column,
instead of repeatedly for each tile in the column. The same goes for
input and output height per row. Also don't round up the same values
repeatedly.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-conv
Limit the input seam position to an interval that guarantees the tile
size does not exceed 1024 pixels after the IC downsizing section and
that space is left for the next tile.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 30 --
1 file
terval all but the left column / top row, to
avoid returning position 0 as best fit.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-image-convert.c
b/drivers/gpu/ipu-v3/ipu
If we managed to create tiles sized 0x0 because of a bug in the seam
calculation, return with an error message instead of letting the driver
run into a division by zero later. Also check for tile sizes that are
larger than supported by the hardware.
Signed-off-by: Philipp Zabel
---
drivers/gpu
This reduces code duplication and allows to easily calculate the valid
interval for the input seam position in the same place.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 30 +++---
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a
The first pixel of the next tile is only sampled by the hardware if the
fractional input position corresponding to the last written output pixel
is not an integer position.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 4 ++--
1 file changed, 2 insertions(+), 2
On Wed, 2019-08-14 at 13:54 +0200, Philipp Zabel wrote:
> This reduces code duplication and allows to easily calculate the valid
> interval for the input seam position in the same place.
>
> Signed-off-by: Philipp Zabel
> ---
> drivers/gpu/ipu-v3/ipu-im
Support is already implemented for the corresponding DRM formats,
just hook up the remaining V4L2 pixel formats.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-common.c | 16 ++--
drivers/gpu/ipu-v3/ipu-cpmem.c | 26 +-
2 files changed, 35
Enable image converter support for V4L2_PIX_FMT_BGRX32 and
V4L2_PIX_FMT_RGBX32 pixel formats.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/ipu-v3/ipu-image-convert.c
b/drivers/gpu/ipu-v3/ipu-image
Hi Marco,
On Thu, 2019-08-15 at 08:36 +0200, Marco Felsch wrote:
> Hi Philipp,
>
> On 19-08-14 17:10, Philipp Zabel wrote:
> > Support is already implemented for the corresponding DRM formats,
> > just hook up the remaining V4L2 pixel formats.
> >
>
gt; --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> @@ -59,7 +59,6 @@ properties:
>- description: SRC interrupt
>- description: CPU WDOG interrupts out of SRC
> minItems: 1
> -maxItems: 2
>
>'#reset-cells':
> const: 1
Acked-by: Philipp Zabel
regards
Philipp
pu_plane_helper_funcs = {
> - .prepare_fb = drm_gem_plane_helper_prepare_fb,
> .atomic_check = ipu_plane_atomic_check,
> .atomic_disable = ipu_plane_atomic_disable,
> .atomic_update = ipu_plane_atomic_update,
Acked-by: Philipp Zabel
regards
Philipp
andler and
> - * drivers can well take care of their interrupts
> - */
> - drm->irq_enabled = true;
> -
> /*
>* set max width and height as default value(4096x4096).
>* this value would be used to check framebuffer size limitation
Acked-by: Philipp Zabel
regards
Philipp
On Thu, Jan 26, 2023 at 07:47:44PM +0100, Lucas Stach wrote:
> imx-drm doesn't mandate a modeset when the framebuffer modifier changes,
> but currently the tile prefetch and resolve (TPR) configuration of the
> PRE is only set up on the initial modeset.
>
> As the TPR configuration is double buffe
On Thu, Jan 26, 2023 at 07:47:43PM +0100, Lucas Stach wrote:
> Move the variables tracking the current dynamic state into a struct
> to separate it a bit better from the static device properties.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
on rollover
Reviewed-by: Philipp Zabel
regards
Philipp
On Wed, Feb 01, 2023 at 04:26:09PM +0100, Lucas Stach wrote:
> This exposes a accumulated GPU active time per client via the
> fdinfo infrastructure.
>
> Signed-off-by: Lucas Stach
> ---
> v3: handle NPU cores
Reviewed-by: Philipp Zabel
regards
Philipp
= devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
> + if (IS_ERR(lcdc->bridge))
> + return dev_err_probe(dev, PTR_ERR(lcdc->bridge), "Failed to
> find bridge\n");
[...]
> + ret = drm_bridge_attach(&lcdc->pipe.encoder, lcdc->bridge, NULL,
> DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> + if (ret)
> + return dev_err_probe(drm->dev, ret, "Cannot attach bridge\n");
The bridge could be a local variable.
With those addressed,
Reviewed-by: Philipp Zabel
regards
Philipp
set of headers.
>
> Signed-off-by: Sam Ravnborg
Reviewed-by: Philipp Zabel
regards
Philipp
(0);
> struct etnaviv_file_private *ctx;
> int ret, i;
>
> @@ -56,6 +57,8 @@ static int etnaviv_open(struct drm_device *dev, struct
> drm_file *file)
> if (!ctx)
> return -ENOMEM;
>
> + ctx->id = atomic_inc_return(&ident);
I suppose we can ignore that this could theoretically wrap around.
Reviewed-by: Philipp Zabel
regards
Philipp
continue;
> +
> + if (gpu->identity.features & chipFeatures_PIPE_2D)
> + cur = snprintf(engine, sizeof(engine), "2D");
> + if (gpu->identity.features & chipFeatures_PIPE_3D)
> + cur = snprintf(eng
gpu_top does not do.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Rob Clark
> Cc: Christian König
> Acked-by: Christian König
Tested-by: Philipp Zabel
on etnaviv with [1].
[1]
https://lore.kernel.org/dri-devel/20220916151205.165687-3-l.st...@pengutronix.de/
regards
Philipp
On Thu, Nov 10, 2022 at 10:49:45AM +0100, Uwe Kleine-König wrote:
[...]
> new file mode 100644
> index ..c3cf6f92a766
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-lcdc.yaml
> @@ -0,0 +1,110 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
pu/drm/imx/Kconfig
> +++ b/drivers/gpu/drm/imx/Kconfig
> @@ -4,7 +4,6 @@ config DRM_IMX
> select DRM_KMS_HELPER
> select VIDEOMODE_HELPERS
> select DRM_GEM_DMA_HELPER
> - select DRM_KMS_HELPER
> depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM
struct drm_display_mode *mode)
> {
> struct imx_tve *tve = con_to_tve(connector);
> unsigned long rate;
Reviewed-by: Philipp Zabel
and pushed to drm-misc-fixes.
regards
Philipp
plane width by limiting the rounding up to the
primary plane.
drm_rect_width(&new_state->src) >> 16 is the same value as
drm_rect_width(dst) because there is no plane scaling support.
Fixes: 94dfec48fca7 ("drm/imx: Add 8 pixel alignment fix")
Signed-off-by: Philipp Zabel
-
On Mi, 2022-11-30 at 19:53 +0100, Lucas Stach wrote:
From: Christian Gmeiner
The MMU tells us the fault status. While the raw register value is
already printed, it's a bit more user friendly to translate the
fault reasons into human readable format.
Signed-off-by: Christian Gmeiner
Signed-off-b
.
>
> Signed-off-by: Christian Gmeiner
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
nce seqno
> monotonicity. Split the lock into those two functions.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
On Thu, Dec 01, 2022 at 06:48:46PM +0100, Lucas Stach wrote:
> This simplifies the driver code a bit, as XArray already provides
> internal locking. IDRs are implemented using XArrays anyways, so
> this drops one level of unneeded abstraction.
>
> Signed-off-by: Lucas Stach
Revie
On Wed, Dec 14, 2022 at 12:59:21PM +0100, Uwe Kleine-König wrote:
> From: Marian Cichy
>
> Add support for the LCD Controller found on i.MX21 and i.MX25.
>
> It targets to be a drop in replacement for the imx-fb driver.
>
> Signed-off-by: Marian Cichy
> [ukl: Rebase to v6.1, various smaller fi
On Fr, 2022-12-16 at 15:51 +0530, Akhil P Oommen wrote:
> Remove the unused 'reset' interface which was supposed to help to ensure
> that cx gdsc has collapsed during gpu recovery. This is was not enabled
> so far due to missing gpucc driver support. Similar functionality using
> genpd framework wi
> Signed-off-by: Liang He
Reviewed-by: Philipp Zabel
regards
Philipp
into its own subdirectory to make the separation more clear.
>
> Signed-off-by: Lucas Stach
Reviewed-by: Philipp Zabel
regards
Philipp
On Fr, 2022-12-16 at 13:03 +0100, Uwe Kleine-König wrote:
> On Fri, Nov 25, 2022 at 12:25:19PM +0100, Lucas Stach wrote:
> > diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
> > index b644deffe948..909622864716 100644
> > --- a/drivers/gpu/drm/imx/Makefile
> > +++ b/drivers/
Hi Uwe,
On Fr, 2022-12-16 at 18:50 +0100, Uwe Kleine-König wrote:
> From: Marian Cichy
>
> Add support for the LCD Controller found on i.MX21 and i.MX25.
>
> It targets to be a drop in replacement for the imx-fb driver.
>
> Signed-off-by: Marian Cichy
> [ukl: Rebase to v6.1, various smaller f
On Fr, 2022-12-16 at 18:50 +0100, Uwe Kleine-König wrote:
> Hello,
>
> Changes since v2:
>
> - added allOf as Krzysztof requested
> - reworked driver based on Philipp's comments
> (improved error handling, different selects, moved driver to a
> subdirectory,
> header sorting, drm_err ins
On Fr, 2022-11-25 at 12:25 +0100, Lucas Stach wrote:
> The IPUv3 and DCSS driver are two totally separate DRM drivers. Having
> one of them live in the drivers/gpu/drm/imx toplevel directory and the
> other one in the dcss/ subdirectory is confusing. Move the IPUv3 driver
> into its own subdirector
On Fr, 2022-12-02 at 16:43 +0100, Lucas Stach wrote:
> Am Dienstag, dem 08.11.2022 um 15:14 +0100 schrieb Philipp Zabel:
> > ipu_src_rect_width() was introduced to support odd screen resolutions
> > such as 1366x768 by internally rounding up primary plane width to a
> &
On Mi, 2022-07-20 at 23:22 +0800, Liang He wrote:
> In ipu_add_client_devices(), we need to call of_node_put() for
> reference returned by of_graph_get_port_by_id() in fail path.
>
> Fixes: 17e052175039 ("gpu: ipu-v3: Do not bail out on missing optional port
> nodes")
> Signed-off-by: Liang He
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