k,mt8195-disp-pseudo-ovl";
>
> Do not create pseudo or virtual device, so just leave the
> "mediatek,mt8195-vdo1-rdma".
>
> Regards,
> Chun-Kuang.
>
OK, I will remove it.
> > +reg = <0 0x1c104000 0 0x1000>;
> > +interrupts = ;
> > +clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> > +power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > +iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> > +mediatek,gce-client-reg = <&gce1 SUBSYS_1c10
> > 0x4000 0x1000>;
> > +};
> > +
> > +disp_vpp_merge@1c10c000 {
> > +compatible = "mediatek,mt8195-vdo1-merge";
> > +reg = <0 0x1c10c000 0 0x1000>;
> > +interrupts = ;
> > +clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> > + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> > +clock-names = "merge","merge_async";
> > +power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > +mediatek,gce-client-reg = <&gce1 SUBSYS_1c10
> > 0xc000 0x1000>;
> > +};
> > +
> > +...
> > --
> > 2.18.0
> >
Regards,
Nancy Lin
Hi Chun-Kuang,
On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年7月17日 週六 下午5:04寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and p
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 83 --
drivers/soc/mediatek/mtk-mmsys.c | 10
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files ch
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin
---
include/dt-bindings/reset/mt8195-resets.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h
b/include/dt-bindings/reset/mt8195-resets.h
index 7ec27a64afc7..e
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,disp.yaml | 8 +
.../display/mediatek/mediatek,ethdr.yaml | 144 ++
2 files changed, 152 inserti
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm devic
Add vdosys1 RDMA and MERGE definition.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,disp.yaml | 30 +++
1 file changed, 30 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
b/Documentation/devicetree/bindings/d
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subseque
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file
Add display node for vdosys1.
Signed-off-by: Nancy.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c| 77 +
drivers/soc/mediatek/mtk
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mutex
Add mmsys config API.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 38
drivers/soc/mediatek/mtk-mmsys.c | 50 ++
drivers/soc/mediatek/mtk-mmsys.h | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 18 ++
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets.
Signed-off-by: Nancy.Lin
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1
The DT binding includes for reset controllers are located in
include/dt-bindings/reset/. Move the Mediatek reset constants in there.
Signed-off-by: Nancy.Lin
---
include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename include/d
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek/Makefi
The hardware path of vdosys1 with DPTx output need to go through by several
modules, such as, PSEUDO_OVL and MERGE.
Add DRM and these modules support by the patches below:
Change in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Ad
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:10 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch
>
> Missatge de Nancy.Lin del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > The DT binding includes for reset controllers are located in
> > include/dt
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin del dia dj., 22 de
> jul.
> 2021 a les 11:45:
> >
> > Add mt8195 vdosys1 clock driver name and routing table to
> > the driver d
Hi Enric,
Thanks for your review.
On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Thank you for your patch.
>
> Missatge de Nancy.Lin del dia dj., 22 de
> jul.
> 2021 a les 11:46:
> >
> > Among other features the mmsys driver should implement a reset
> > control
Hi Chun-Kuang,
Thanks for your review.
On Wed, 2021-07-28 at 07:39 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multi
Hi Chun-Kuang,
Thanks for your review.
On Sun, 2021-07-25 at 09:57 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年7月22日 週四 下午5:46寫道：
> >
> > Add pseudo ovl module files:
>
> My English is not good. The word 'pseudo' seems like 'looks like but
> indeed not the same'.
> I think
Hi Enric,
On Wed, 2021-07-28 at 12:31 +0200, Enric Balletbo Serra wrote:
> Hi Nancy,
>
> Missatge de Nancy.Lin del dia dc., 28 de
> jul.
> 2021 a les 8:01:
> >
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 14:20 +0200, Matthias Brugger wrote:
>
> On 28/07/2021 07:34, Nancy.Lin wrote:
> > Hi Enric,
> >
> > Thanks for your review.
> >
> > On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote:
> > > Hi Nancy,
> > >
> > > Thank you f
Hi Matthias,
Thanks for the review.
On Fri, 2021-08-06 at 17:30 +0200, Matthias Brugger wrote:
>
> On 22/07/2021 11:45, Nancy.Lin wrote:
> > Add mmsys config API.
>
> This patch is doing a lot of things, it adds a "config" and it adds
> cmdq
> support. Please explain better in the commit messag
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
For MT8195 vdosys1, many async modules need to reset after
the display pipe stops and restart.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,ethdr.yaml | 144 ++
1 file changed, 144 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git
a/Documentation/devicetree
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git
a/Documentation/devicetre
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 136 +
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files ch
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
s
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++-
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin
---
include/dt-bindings/reset/mt8195-resets.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h
b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..e
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 ++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 275
driver
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 62 ++
drivers/soc/mediatek/mtk-mmsy
The hardware path of vdosys1 with DPTx output need to go through by several
modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v3:
- modify for reviewer's comment in v2.
- add vdosys1 2 pixels align limit.
- add mixer odd offset support.
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm devic
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets
Signed-off-by: Nancy.Lin
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1
Add display node for vdosys1.
Signed-off-by: Nancy.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 217 +++
1 file changed, 217 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..b2e377515a52
Add vdosys1 MERGE definition.
Signed-off-by: Nancy.Lin
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml| 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
b/Documentation/devicetree/bindings/display/me
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 09:14 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys1
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-08-21 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm
> > for
> > multi-mmsys support. The two mmsys (vdosys0 and vdosys
Hi Chun-Kuang,
Thanks for the review.
On Sun, 2021-08-22 at 07:47 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年8月18日 週三 下午5:19寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module
Hi Chun-Kuang,
Thanks for the review.
On Fri, 2021-08-20 at 07:25 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年8月18日 週三 下午5:18寫道：
> >
> > Add vdosys1 MERGE definition.
> >
> > Signed-off-by: Nancy.Lin
> > ---
> > .../devicetree/bindings/display/mediatek/mediatek,merge.yaml
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is
Add display node for vdosys1.
Signed-off-by: Nancy.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 221 +++
1 file changed, 221 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 4064a92e28a5..6ea6d0c6d840
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin
---
include/dt-bindings/reset/mt8195-resets.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h
b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..e
Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.
For MT8195 vdosys1, many async modules need to reset after
the display pipe stops and restart.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,ethdr.yaml | 144 ++
1 file changed, 144 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git
a/Documentation/devicetree
The mmsys system controller exposes a set of memory client resets and
needs to specify the #reset-cells property in order to advertise the
number of cells needed to describe each of the resets
Signed-off-by: Nancy.Lin
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 +++
1
MT8195 vdosys1 merge1 to merge4 have HW mute function.
Add MERGE additional mute property description.
Signed-off-by: Nancy.Lin
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/med
The hardware path of vdosys1 with DPTx output need to go through by several
modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v4:
- use merge common driver for merge1~4.
- refine ovl_adaptor rdma driver.
- use ovl_adaptor ddp_comp functio
Add merge new API.
1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
2. Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension.
3. Add merge e
MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support.
The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers,
only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 136 +
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files ch
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 62 ++
drivers/soc/mediatek/mtk-mmsy
Add driver data of mt8195 vdosys1 to mediatek-drm and the sub driver.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git
a/Documentation/devicetre
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++-
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 306
drivers
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
s
Add merge vblank support.
The vdosys1 go through the following component:
pseudo_ovl -> ethdr -> merge5 -> dp_intf1
The first comp is pseudo_ovl. This comp doesn't
have the whole CRTC timing vblank but only has vblank for each layer.
Merge5 comp gets all the mixed layers after the ETHDR module.
Use
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subseque
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
Two RDMAs merge into one layer, so this module support 4
layers. The four layers are blending at the EHTDR module next to it.
Signed-off-
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++
2 files changed, 142 inserti
1. Add pseudo-ovl definition file for mt8195 display.
2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++
2 files chang
The hardware path of vdosys1 with DPTx output need to go through
by several modules, such as, PSEUDO_OVL, ETHDR, and MERGE.
Add DRM and these modules support by the patches below:
Signed-off-by: Nancy.Lin
---
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 a
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mutex
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 83 --
drivers/soc/mediatek/mtk-mmsys.c | 10
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files ch
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm devic
Add display node for vdosys1.
Signed-off-by: Nancy.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 +++
1 file changed, 206 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..5dc9bf6edda0
Hi Philipp,
Thanks for the review.
I will base on Enric's patchset in my next revision.
Regards,
Nancy
On Wed, 2021-08-25 at 12:46 +0200, Philipp Zabel wrote:
> Hi,
>
> On Wed, 2021-08-25 at 18:05 +0800, Nancy.Lin wrote:
> > Among other features the mmsys driver should implement a reset
> > con
MT8195 vdosys1 merge1 to merge4 have HW mute function.
Add MERGE additional mute property description.
Signed-off-by: Nancy.Lin
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/med
Add merge new API.
1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
2. Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension.
3. Add merge e
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 77 +++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git
a/Documentation/devicetre
MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Modify mmsys for support 64 bit and different reset
base.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c| 15 ---
drivers/soc/mediate
Add driver data of mt8195 vdosys1 to mediatek-drm and the sub driver.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 62 ++
drivers/soc/mediatek/mtk-mmsy
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 301
drivers
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin
---
include/dt-bindings/reset/mt8195-resets.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h
b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..e
MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support.
The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers,
only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h| 136 +
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files ch
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is
The hardware path of vdosys1 with DPTx output need to go through by several
modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v5:
- add mmsys reset controller reference.
Changes in v4:
- use merge common driver for merge1~4.
- refine ovl
Add display node for vdosys1.
Signed-off-by: Nancy.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 221 +++
1 file changed, 221 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 4064a92e28a5..6ea6d0c6d840
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++-
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
s
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin
---
.../display/mediatek/mediatek,ethdr.yaml | 144 ++
1 file changed, 144 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git
a/Documentation/devicetree
Dear Philipp,
Thanks for the review.
On Mon, 2021-09-06 at 09:29 +0200, Philipp Zabel wrote:
> Hi Nancy,
>
> On Mon, 2021-09-06 at 15:15 +0800, Nancy.Lin wrote:
> > MT8195 vdosys1 has more than 32 reset bits and a different reset
> > base
> > than other chips. Modify mmsys for support 64 bit and
w!1MjfK1sAMDvP9fU1GX6QvfLEfapYEcLmsYP2AhkAOZ6LVaLTLi6vAnJMMqH3vrJ3$
>
> [2]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210906071539.12953-12-nancy@mediatek.com/__;!!CTRNKA9wMg0ARbw!1MjfK1sAMDvP9fU1GX6QvfLEfapYEcLmsYP2AhkAOZ6LVaLTLi6vAnJ
RST_B_HDR_VDO_FE0_DL_ASYNC 51
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
> > +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_AS
mask);
> > + } else {
> > +#endif
> > + u32 tmp = readl(mmsys->regs + offset);
> > +
> > + tmp = (tmp & ~mask) | reg_val;
> > + writel(tmp, mmsys->regs + offset);
> > +#if IS_REACHABLE(CONFIG_MTK_CM
turn -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + priv->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(priv->regs)) {
> > + dev_err(dev, "failed to ioremap rdma\n"
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 16:56 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/21 08:21, Nancy.Lin ha scritto:
> > MT8195 vdosys1 has more than 32 reset bits and a different reset
> > base
> > than other chips. Modify mmsys for support 64 bit and different
> > r
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-10-16 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add vdosys1 ETHDR definition.
> >
> > Signed-off-by: Nancy.Lin
> > ---
> > .../display/mediatek/mediatek,ethdr.yaml | 145
> > +
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 17:01 +0200, AngeloGioacchino Del Regno wrote:
> > Add mtk-mutex support for mt8195 vdosys1.
> > The vdosys1 path component contains ovl_adaptor, merge5,
> > and dp_intf1. Ovl_adaptor is composed of several sub-elements,
> > so change it to
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