On Thu, Dec 08, 2016 at 11:23:39PM +0200, Jani Nikula wrote:
> On Tue, 06 Dec 2016, Manasi Navare wrote:
> > Sink's capabilities are advertised through DPCD registers and get
> > updated only on hotplug. So they should be computed only once in the
> > long pulse handler
gets merged so that i dont have to
rebase it tremendously after 3 weeks when I am back and plus
its good for the driver to start using this clean up. This kind
of clean up was long due.
Regards
Manasi
On Thu, Dec 08, 2016 at 11:23:39PM +0200, Jani Nikula wrote:
> On Tue, 06 Dec 2016, Manasi Nav
On Thu, Dec 08, 2016 at 11:46:02PM +0200, Jani Nikula wrote:
> On Tue, 06 Dec 2016, Manasi Navare wrote:
> > If link training fails, then we need to fallback to lower
> > link rate first and if link training fails at RBR, then
> > fallback to lower lane count.
> > T
On Thu, Dec 08, 2016 at 11:51:30PM +0200, Jani Nikula wrote:
> On Tue, 06 Dec 2016, Manasi Navare wrote:
> > If link training at a link rate optimal for a particular
> > mode fails during modeset's atomic commit phase, then we
> > let the modeset complete and then re
variables through a memset instead of
individual resetting.
Signed-off-by: Manasi Navare
Cc: Jani Nikula
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 -
drivers/gpu/drm/i915/intel_dp.c | 24 ++--
drivers/gpu/drm/i915/intel_drv.h| 14
This patch addresses a few issues from the original patch for
DP Compliance EDID test support submitted by
Todd Previte
Video Mode requested in the EDID test handler for the EDID Read
test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
Signed-off-by: Manasi Navare
Cc: Jani Nikula
sent in order
to trigger another modeset during which the pipe is configured
and link is retrained and enabled for link parameters requested
by the test.
v2:
* Validate the test lane count before using it in
intel_dp_compute_config (Jani Nikula)
Signed-off-by: Manasi Navare
Cc: Jani Nikula
Cc
wakes up the IGT tool, userspace
reads the video pattern values from corresponding debugfs files and fills the
framebuffers and triggers a modeset.
Manasi Navare (5):
drm/i915: Move all the DP compliance data to a separate struct
drm/i915: Add support for DP link training compliance
drm/i915:
sk of interruption from the userspace
app that is polling on that flag.
v2:
* Updated the DPCD Register reads based on proper defines in header (Jani
Nikula)
* Squahsed the patch that forced the pipe bpp to compliance test bpp (Jani
Nikula)
Signed-off-by: Manasi Navare
Cc: Jani Nikula
Cc: Daniel V
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-devel at lists.freedesktop.org
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
---
include/drm/drm_dp_helper.h | 58 +
1 file changed, 58
-by: Harry Wentland
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Daniel Vetter
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 38 ++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-devel at lists.freedesktop.org
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
---
include/drm/drm_dp_helper.h | 58 +
1 file changed, 58
Jani,
I have added the defs for all compliance video pattern test registers as
you had commented on previous version of this patch.
It also fixes the indentation. Could you please review this patch?
Regards
Manasi
On Fri, Dec 09, 2016 at 04:32:59PM -0800, Manasi Navare wrote:
> v2:
>
; > > Subject: Re: [Intel-gfx] [PATCH v4 19/25] drm/i915/dsc: Add a power domain
> > > for VDSC on eDP/MIPI DSI
> > >
> > > On Fri, Sep 21, 2018 at 04:46:47PM +0300, Ville Syrjälä wrote:
> > > > On Fri, Sep 21, 2018 at 01:34:00AM -0700, Manasi Nava
This patch explains the DRM_MODE_PROP_IMMUTABLE flag a bit better
by telling which function to call if kernel wants to update
drm object's immutable properties.
Suggested-by: Daniel Vetter
Cc: Daniel Vetter
Signed-off-by: Manasi Navare
---
include/drm/drm_property.h | 3 ++-
1 file chang
On Wed, Oct 03, 2018 at 10:41:20AM +0200, Daniel Vetter wrote:
> On Tue, Oct 02, 2018 at 10:49:17AM -0400, Harry Wentland wrote:
> >
> >
> > On 2018-10-01 03:15 AM, Daniel Vetter wrote:
> > > On Mon, Sep 24, 2018 at 02:15:34PM -0400, Nicholas Kazlauskas wrote:
> > >> These patches are part of a p
variable refresh rate capability for a connector.
> + *
> + * The value from &drm_connector_state.vrr_capable will reads
> + *
The sentence above looks incomplete.
Other than that this patch looks good to me. So with the kernel doc fixes:
Reviewed-by: Manasi Navare
Manasi
)
* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320
v2:
* Add SHIFT define and DECOMPRESSION_EN define missed in prev patch
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
i
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha
.
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 15
trol parameters for DSC
drm/i915/dp: Enable/Disable DSC in DP Sink
Manasi Navare (21):
drm/dp: Add DP DSC DPCD receiver capability size define and missing
SHIFT
drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP
Init
drm/dp: DRM DP helper/macros to get DP sink DSC parame
rjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/drm_dp_helper.c | 90 +
include/drm/drm_dp_helper.h | 30 +++
2 files changed, 120 insertions(+)
diff --git a/driver
: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index 1f2b5dc82f16..f2b3b30b6f5e 100644
--- a/drivers/gpu/drm/i915
(Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_display.c | 20 +++-
drivers/gpu/drm/i
kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm
27;s patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_vdsc.c | 127
ams
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
d
Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Dhinakaran Pandiyan
Signed-off-by: Manasi Navare
nction (Jani N)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Daniel Vetter
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 32
drivers/gpu/dr
(Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915
-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52dca5901aa1..987d3b2eb8d3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
ivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 6 +
drivers/gpu/drm/i915/intel_vdsc.c| 418 +++
3 files changed, 426 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/g
we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 0e5e3368d645..8562d8ee8161 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index
Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index f2b3b30b6f5e
compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 13
ro (Manasi)
v2:
- Add define to conditionally check the buffer target depth (James Ausmus)
Suggested-by: Madhav Chauhan
Cc: Madhav Chauhan
Cc: Manasi Navare
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index e9
VDSC enabling/disabling.
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_vdsc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
Cc: Rodrigo Vivi
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Lyude Paul
Signed-off-by: Manasi Navare
VESA eDP 1.4 specification has separate fields defined in
EDP_DPCD_REV for eDP 1.4a and 1.4b eDP revisions.
This patch defines those. Found this when one of my eDP panels
advertises eDP 1.4a (04h) in the EDP_DPCD_REV DPCD field.
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
Thanks for the review.
Pushed to drm-misc.
Manasi
On Wed, Oct 03, 2018 at 09:32:49PM +0200, Daniel Vetter wrote:
> On Tue, Oct 02, 2018 at 02:50:55PM -0700, Manasi Navare wrote:
> > This patch explains the DRM_MODE_PROP_IMMUTABLE flag a bit better
> > by telling which function to
On Tue, Oct 09, 2018 at 04:43:51PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 08, 2018 at 05:23:51PM -0700, Manasi Navare wrote:
> > VESA eDP 1.4 specification has separate fields defined in
> > EDP_DPCD_REV for eDP 1.4a and 1.4b eDP revisions.
> > This patch defines those. F
On Tue, Oct 09, 2018 at 05:32:49PM +0300, Jani Nikula wrote:
> On Tue, 09 Oct 2018, Ville Syrjälä wrote:
> > On Mon, Oct 08, 2018 at 05:23:51PM -0700, Manasi Navare wrote:
> >> VESA eDP 1.4 specification has separate fields defined in
> >> EDP_DPCD_REV for eDP
On Fri, Oct 05, 2018 at 07:34:35PM -0400, Lyude Paul wrote:
> On Fri, 2018-10-05 at 16:23 -0700, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same
Hi Imre/Ville,
This patch adds the power domain as per our discussion and feedback
on previous patch set.
Could you please take a look at this?
Manasi
On Fri, Oct 05, 2018 at 04:22:57PM -0700, Manasi Navare wrote:
> On Icelake, a separate power well PG2 is created for
> VDSC engine us
Hi Ville,
This adds a helper function to get the power well as per
the transcoder as per your suggestion.
Could you please review this one?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:23:04PM -0700, Manasi Navare wrote:
> A separate power well 2 (PG2) is required for VDSC on eDP transco
Hi Jani,
This patch adds the cpu_to_be16 macro and removes the bitfields and
uses macros instead for packing the infoframe as per your feedback
on the previous version of the patch.
Could you please review this patch?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:49PM -0700, Manasi Navare wrote
Hi Jani,
This patch has a verbal ACK from you when we went over the patch together,
This is rebased on top of edp fast/narrow optimized config like we discussed.
could you please review this?
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:51PM -0700, Manasi Navare wrote:
> DSC params like
Ville/Jani,
Could you please look at the logistics of the patch and ACK this?
This has been validated and tested on the DSC panel.
Regards
Manasi
On Fri, Oct 05, 2018 at 04:22:54PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This patches does the following:
>
>
Thanks for your review comments.
On Tue, Oct 16, 2018 at 10:01:11PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 05, 2018 at 04:22:57PM -0700, Manasi Navare wrote:
> > On Icelake, a separate power well PG2 is created for
> > VDSC engine used for eDP/MIPI DSI. This patch adds a new
&g
On Tue, Oct 16, 2018 at 10:19:06PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 16, 2018 at 10:01:11PM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 05, 2018 at 04:22:57PM -0700, Manasi Navare wrote:
> > > On Icelake, a separate power well PG2 is created for
> > > VDSC e
is enabled on the sink.
> >
> >v3:
> >* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
> >are used (Manasi)
> >* Add DSC slice_row_per_frame in PPS16 (Manasi)
> >
> >v2:
> >* Enable PG2 power well for VDSC on eDP
On Tue, Oct 16, 2018 at 10:45:55PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 16, 2018 at 12:42:05PM -0700, Manasi Navare wrote:
> > On Tue, Oct 16, 2018 at 10:19:06PM +0300, Ville Syrjälä wrote:
> > > On Tue, Oct 16, 2018 at 10:01:11PM +0300, Ville Syrjälä wrote:
> > > &
On Tue, Oct 16, 2018 at 02:04:21PM -0700, Manasi Navare wrote:
> On Tue, Oct 16, 2018 at 10:45:55PM +0300, Ville Syrjälä wrote:
> > On Tue, Oct 16, 2018 at 12:42:05PM -0700, Manasi Navare wrote:
> > > On Tue, Oct 16, 2018 at 10:19:06PM +0300, Ville Syrjälä wrote:
> > > &
On Thu, Oct 18, 2018 at 08:02:14PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 05, 2018 at 04:23:02PM -0700, Manasi Navare wrote:
> > Display Stream Splitter registers need to be programmed to enable
> > the joiner if two DSC engines are used and also to enable
> > the left and
Thanks for the review.
Pushed to drm-misc
Manasi
On Tue, Oct 09, 2018 at 04:43:51PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 08, 2018 at 05:23:51PM -0700, Manasi Navare wrote:
> > VESA eDP 1.4 specification has separate fields defined in
> > EDP_DPCD_REV for eDP 1.4a and 1.4
On Fri, Oct 05, 2018 at 04:22:56PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This patch enables decompression support in sink device
> before link training and disables the same during the
> DDI disabling.
>
> v2:(From Manasi)
> * Change the enable/
On Mon, Oct 22, 2018 at 04:34:59PM -0700, Srivatsa, Anusha wrote:
>
>
> From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Manasi
> Navare [manasi.d.nav...@intel.com]
> Sent: Friday, October 05, 2018 4:22
Singh (4):
drm/dsc: Define VESA Display Stream Compression Capabilities
drm/i915/dsc: Define & Compute VESA DSC params
drm/i915/dsc: Compute Rate Control parameters for DSC
drm/i915/dp: Enable/Disable DSC in DP Sink
Manasi Navare (21):
drm/dp: Add DP DSC DPCD receiver capability size de
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha
rjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/drm_dp_helper.c | 90 +
include/drm/drm_dp_helper.h | 30 +++
2 files changed, 120 insertions(+)
diff --git a/driver
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index
: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d7761b8ac07..45fd7894722b 100644
--- a
Sink (Manasi)
v2:
* Change the small joiner RAM buffer constant as bspec changed (Manasi)
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Dhinakaran Pandiyan
Signed-off-by: Manasi Navare
-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0b5939992c2b..3df73f18212e 100644
--- a/drivers/gpu/drm/i915
s for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
R
Cc: Ville Syrjälä
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
include/drm/drm_dsc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 0e5e3368d645..8562d8ee8161 100644
--- a/include/drm
nction (Jani N)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Daniel Vetter
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 32
drivers/gpu/dr
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
ams
* Using <
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Co-developed-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 7 +
drivers/gpu/d
the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Reviewed-by: Gaurav K Singh
---
drivers/gpu/drm
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
VDSC enabling/disabling.
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_vdsc.c | 26 ++
1 file
(Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Co-developed
ro (Manasi)
v2:
- Add define to conditionally check the buffer target depth (James Ausmus)
Suggested-by: Madhav Chauhan
Cc: Madhav Chauhan
Cc: Manasi Navare
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_
)
* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320
v2:
* Add SHIFT define and DECOMPRESSION_EN define missed in prev patch
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
i
kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)
v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Acked-by: Harry Wentland
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_displa
(Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Acked-by: Jani Nikula
---
drivers/gpu/drm/i
Cc: Manasi Navare
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Gaurav K Singh
Cc: Harry Wentland
Signed-off-by: Anusha Srivatsa
Reviewed-by: Manasi Navare
---
include/drm/drm_dsc.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index e9
flag as part of crtc_state (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 15
lle)
v2:
* Rebase (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
: Manasi Navare
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_vdsc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c
b/drivers/gpu/drm/i915/intel_vdsc.c
index b0fc716bbbfd..4b4b812d68f3 100644
--- a/drivers/gpu/drm/i915
.
v3:
* Add the SPDX shorthand (Chris Wilson)
v2:
* Do not use bitfields in the struct (Jani Nikula)
Cc: Gaurav K Singh
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Harry Wentland
Signed-off-by: Manasi Navare
Reviewed-by: Harry Wentland
compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
Signed-off-by: Gaurav K Singh
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 13
error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjala
---
drivers/gpu/drm/i915/intel_display.h| 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4
)
Cc: Rodrigo Vivi
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Lyude Paul
Signed-off-by: Manasi Navare
Reviewed-by: Lyude Paul
---
drivers/gpu/drm/i915/i915_debugfs.c | 71 -
drivers/gpu/drm/i915/intel_dp.c | 1 +
drivers/gpu/drm/i915/intel_drv.h| 3 ++
3
On Thu, Oct 25, 2018 at 05:22:18PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:38PM -0700, Manasi Navare wrote:
> > A separate power well 2 (PG2) is required for VDSC on eDP transcoder
> > whereas all other transcoders use the power wells associated with the
>
On Thu, Oct 25, 2018 at 05:16:58PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:37PM -0700, Manasi Navare wrote:
> > 1. Disable Left/right VDSC branch in DSS Ctrl reg
> > depending on the number of VDSC engines being used
> > 2. Disable joiner in DSS Ctrl
On Thu, Oct 25, 2018 at 05:15:34PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:36PM -0700, Manasi Navare wrote:
> > Display Stream Splitter registers need to be programmed to enable
> > the joiner if two DSC engines are used and also to enable
> > the left and
On Thu, Oct 25, 2018 at 05:09:42PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:34PM -0700, Manasi Navare wrote:
> > DSC PPS secondary data packet infoframes are filled with
> > DSC picure parameter set metadata according to the DSC standard.
> > These infof
On Thu, Oct 25, 2018 at 05:03:06PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:30PM -0700, Manasi Navare wrote:
> > From: Gaurav K Singh
> >
> > This patch enables decompression support in sink device
> > before link training and disables the same d
On Wed, Oct 24, 2018 at 06:28:02PM -0400, Lyude Paul wrote:
> On Wed, 2018-10-24 at 15:28 -0700, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same
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