Tested-by: Jonathan Marek
On 4/11/21 8:01 PM, Dmitry Baryshkov wrote:
msm_dsi_phy_get_clk_provider() always returns two provided clocks, so
return 0 instead of returning incorrect -EINVAL error code.
Fixes: 5d13459650b3 ("drm/msm/dsi: push provided clocks handling into a generic
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
v2:
- rebased on DSI PHY reworks
- reworked getting cphy_mode in dsi_host.c
- documentation change in separate patch
Jonathan Marek
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/drm/msm/dsi/dsi_host.c
Increase the minor version to indicate that MSM_PARAM_SUSPENDS is supported.
Fixes: 3ab1c5cc3939 ("drm/msm: Add param for userspace to query suspend count")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
No one knows what this is for anymore, so just remove it.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index b199942266a2
Add support for MSM_BO_CACHED_COHERENT, a coherent version of MSM_BO_CACHED
which is implemented by setting the IOMMU_CACHE flag.
Jonathan Marek (5):
drm/msm: remove unnecessary mmap logic for cached BOs
drm/msm: replace MSM_BO_UNCACHED with MSM_BO_WC for internal objects
drm/msm: use the
msm_gem_get_vaddr() currently always maps as writecombine, so use the right
flag instead of relying on broken behavior (things don't actually work if
they are mapped as uncached).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/a
Use the same logic as the userspace mapping.
This fixes msm_rd with cached BOs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm
There shouldn't be any reason to ever use uncached over writecombine,
so just use writecombine for MSM_BO_UNCACHED.
Note: userspace never used MSM_BO_UNCACHED anyway
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_gem.c | 4 +---
include/uapi/drm/msm_drm.h| 2 +-
2 files ch
mmu500 targets don't have a "cx_mem" region, set llc_mmio to NULL in that
case to avoid the IS_ERR() condition in a6xx_llc_activate().
Fixes: 3d247123b5a1 ("drm/msm/a6xx: Add support for using system cache on
MMU500 based targets")
Signed-off-by: Jonathan Marek
---
d
The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing
bitshift operation.
Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250: fix display nodes
.../devicetree/bindings/display/msm/dpu.txt | 4 +--
arch/arm64/boot/dts/qcom/sm8250.dtsi
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
v2: do not remove mmcx-supply from dispcc node
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250: fix display nodes
.../devicetree/bindings/display/msm/dpu.txt | 4
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
v2: do not remove mmcx-supply from dispcc node
v3: remove references to dp_phy (missed this in v2, sorry for the spam)
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
---
.../devicetree/bindings/display/msm/dsi.txt | 1 +
drivers/gpu/drm/msm/dsi/dsi.c
On 2/16/21 11:54 AM, Dmitry Baryshkov wrote:
On Mon, 15 Feb 2021 at 19:25, Jonathan Marek wrote:
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP
On 3/5/21 4:48 PM, Rob Herring wrote:
On Mon, Feb 15, 2021 at 11:27:44AM -0500, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jona
On 3/5/21 5:45 PM, Dmitry Baryshkov wrote:
On 15/02/2021 19:27, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Other that fe
Add support for Adreno 660 to the drm/msm driver. Very similar to A650
on the kernel side.
Jonathan Marek (5):
drm/msm: remove unused icc_path/ocmem_icc_path
drm/msm/a6xx: avoid shadow NULL reference in failure path
drm/msm/a6xx: add support for Adreno 660 GPU
drm/msm/a6xx: update
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/a
ned-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 727d111a413f..01bd31b3c504 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_g
g GMU allocations, additional register init,
dummy hfi BW table, entry in gpulist table.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 32 +++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
Accept all SQE firmware versions for A660.
Re-organize the function a bit and print an error message for unexpected
GPU IDs instead of failing silently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +--
1 file changed, 17 insertions
Add a660 hwcg table, ported over from downstream.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 2 +-
3 files changed, 55 insertions(+), 1
Add support for Adreno 660 to the drm/msm driver. Very similar to A650
on the kernel side.
v2:
- added AOP PDC path for a650 and use it for a660 too
- fix UBWC config for a650 (also affects a660)
- add CP_PROTECT update, and corresponding a660 settings in A660 patch
Jonathan Marek (8):
drm
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/a
SM8250 AOP firmware already sets up PDC registers for us, and it only needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff
Value was shifted in the wrong direction, resulting in the field always
being zero, which is incorrect for A650.
Fixes: d0bac4e9cd66 ("drm/msm/a6xx: set ubwc config for A640 and A650")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1
Update CP_PROTECT register programming based on downstream.
A6XX_PROTECT_RW is renamed to A6XX_PROTECT_NORDWR to make things aligned
and also be more clear about what it does.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 143 +++---
drivers/gpu
ned-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 909e3ff08f89..ff3c328604f8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_g
g GMU allocations, additional register init,
dummy hfi BW table, cp protect list, entry in gpulist table.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 32 +++---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
Accept all SQE firmware versions for A660.
Re-organize the function a bit and print an error message for unexpected
GPU IDs instead of failing silently.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +--
1 file changed, 17 insertions
Add a660 hwcg table, ported over from downstream.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 2 +-
3 files changed, 55 insertions(+), 1
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm
dma_ops_bypass part,
this is what I came up with reading the emails.
Jonathan Marek (5):
drm/msm: add MSM_BO_CACHED_COHERENT
dma-direct: add dma_direct_bypass() to force direct ops
drm/msm: call dma_direct_bypass()
drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
drm
Always use direct dma ops and no swiotlb.
Note: arm-smmu-qcom already avoids creating iommu dma ops, but not
everything uses arm-smmu-qcom and this also sets the dma mask.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/msm_drv.c | 8 +---
2 files
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/dr
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/dr
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594
On 11/14/20 2:39 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote:
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm
.
Jonathan Marek (5):
drm/msm: add MSM_BO_CACHED_COHERENT
dma-direct: add dma_direct_bypass() to force direct ops
drm/msm: call dma_direct_bypass()
drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
drm/msm: bump up the uapi version
drivers/gpu/drm/msm/Kconfig
Always use direct dma ops and no swiotlb.
Note: arm-smmu-qcom already avoids creating iommu dma ops, but not
everything uses arm-smmu-qcom and this also sets the dma mask.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/msm_drv.c | 8 +---
2 files
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end
On 11/16/20 12:50 PM, Rob Clark wrote:
On Mon, Nov 16, 2020 at 9:33 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 03:07:20PM -0500, Jonathan Marek wrote:
qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like
dma_sync_single_for_cpu() does deal in some way with the pa
pport the GPU core clock and turning on the GX rail, which is normally
offloaded to the GMU).
Register updates:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15602
Jonathan Marek (4):
drm/msm/adreno: move a6xx CP_PROTECT macros to common code
drm/msm/adreno: use a single reg
These will be used by a7xx, so move them to common code. A6XX_ prefix is
kept because the generic ADRENO_ is already in use.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 17 -
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++
2 files changed, 6
The high half of 64-bit registers is always at +1 offset, so change these
helpers to be more convenient by removing the unnecessary argument.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 3 +--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27
Adds a7xx changes for the kernel driver.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a7xx.xml.h | 666
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 63 +-
2 files changed, 716 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/msm
pport the GPU core clock and turning on the GX rail, which is normally
offloaded to the GMU).
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/adreno/a7xx_gpu.c | 777
drivers/gpu/drm/msm/adreno/a7xx_gpu.h
create a local pagetable")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index bcaddbba564df..22935ef26a3a1 100644
--- a/drivers/gpu/drm/ms
FYI, I already had a patch fixing this error (it is in linux-next:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/include/linux/qcom_scm.h).
This one is probably better though.
On 12/28/2018 02:31 PM, Bjorn Andersson wrote:
On Wed 26 Dec 04:06 PST 2018, Fabio Estevam w
There is an error in the a2xx part of this patch: 0xfff in adreno_gpu.c
became 0xff in a2xx_gpu.c
On 3/1/19 2:38 PM, Jordan Crouse wrote:
Move the address space steup code out of the generic msm GPU code to
to the individual GPU targets. This allows us to do target specific
setup such as gpummu
agetable")
Signed-off-by: Jonathan Marek
---
v2: use for_each_sgtable_sg and update commit message
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index bcaddbba564df..a54ed354578b5
Another thing: did you verify that the panel still runs at 60hz (and not
dropping frames to 30hz)? IIRC that was the behavior with lower clock.
On 3/2/20 10:28 PM, Jonathan Marek wrote:
On 3/2/20 10:13 PM, Brian Masney wrote:
On Mon, Mar 02, 2020 at 03:48:22PM -0500, Jonathan Marek wrote
On 3/2/20 3:34 PM, Ville Syrjala wrote:
From: Ville Syrjälä
The currently listed dotclock disagrees with the currently
listed vrefresh rate. Change the dotclock to match the vrefresh.
Someone tell me which (if either) of the dotclock or vreresh is
correct?
Cc: Jonathan Marek
Cc: Brian Masne
On 3/2/20 10:13 PM, Brian Masney wrote:
On Mon, Mar 02, 2020 at 03:48:22PM -0500, Jonathan Marek wrote:
Hi,
This is a command mode panel and the the msm/mdp5 driver uses the vrefresh
field for the actual refresh rate, while the dotclock field is used for the
DSI clocks. The dotclock needed to
9:16 PM, Brian Masney wrote:
On Tue, Mar 03, 2020 at 08:04:05AM -0500, Jonathan Marek wrote:
What Xorg prints doesn't mean anything. I don't think there will be errors
in dmesg, you need to run something that does pageflips as fast as possible
and see that the refresh rate is still 60. (mod
on, Mar 02, 2020 at 10:36:54PM -0500, Jonathan Marek wrote:
Another thing: did you verify that the panel still runs at 60hz (and not
dropping frames to 30hz)? IIRC that was the behavior with lower clock.
Yes, the panel is running at 60 HZ according to the Xorg log with
Ville's patch applied:
guess you have it force-enabled) since
the results are all 26-27 (X works a bit differently and gets double the
framerate somehow?)
On 3/3/20 9:53 PM, Brian Masney wrote:
On Tue, Mar 03, 2020 at 09:27:50PM -0500, Jonathan Marek wrote:
modetest should be printing "freq: 60.0Hz"
The msm DSI driver does predate the addition of those fields and doesn't
use them at all.
Seems like it would be a bit of a hack too, since the frequency we want
to use is not the "real limits of the hardware"..
On 3/4/20 4:10 AM, Linus Walleij wrote:
On Mon, Mar 2, 2020 at 9
Hi,
I tried this and it works with patches 4+5 from Rob's series and
changing gpummu to use sg_phys(sg) instead of sg->dma_address
(dma_address isn't set now that dma_map_sg isn't used).
Jonathan
On 9/3/19 11:22 AM, Rob Clark wrote:
On Mon, Sep 2, 2019 at 11:03 AM Fabio Estevam wrote:
Hi
On 5/3/21 1:11 PM, Rob Herring wrote:
On Fri, Apr 23, 2021 at 01:24:40PM -0400, Jonathan Marek wrote:
Document qcom,dsi-phy-cphy-mode option, which can be used to control
whether DSI will operate in D-PHY (default) or C-PHY mode.
Given this is a standard MIPI thing, I think this needs to be a
On 5/31/21 3:24 AM, Akhil P Oommen wrote:
On 5/13/2021 10:43 PM, Jonathan Marek wrote:
SM8250 AOP firmware already sets up PDC registers for us, and it only
needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno
On 5/31/21 11:05 AM, Akhil P Oommen wrote:
On 5/13/2021 10:44 PM, Jonathan Marek wrote:
...
@@ -519,7 +519,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
if (!pdcptr)
goto err;
- if (adreno_is_a650(adreno_gpu))
+ if (adreno_is_a650(adreno_gpu
already picked up by robclark
- added patches for missing PC_DBG_ECO_CNTL/GMU_CX_FALNEXT_INTF settings
- changed a660_protect to exclude CP_PERFCTR_CP_SEL
- removed 635 id from adreno_is_a650_family
- squashed a660 patches
Jonathan Marek (5):
drm/msm: remove unused icc_path/ocmem_icc_path
drm
These aren't used by anything anymore.
Signed-off-by: Jonathan Marek
Reviewed-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
drivers/gpu/drm/msm/msm_gpu.h | 9 -
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu
SM8250 AOP firmware already sets up PDC registers for us, and it only needs
to be enabled. This path will be used for other newer GPUs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff
downstream msm-5.14 kernel added a write to this register, so match that.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm
See downstream's "disable_tseskip" flag.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
ind
g GMU allocations, additional register init,
dummy hfi BW table, cp protect list, entry in gpulist table, hwcg table,
updated a6xx_ucode_check_version check.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 32 +++-
driver
On 6/8/21 1:27 PM, Jonathan Marek wrote:
downstream msm-5.14 kernel added a write to this register, so match that.
Note: this should say msm-5.4 (msm-5.14 is not a thing)
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +++-
drivers/gpu/drm/msm/adreno
l bindings
- changed binding to "phy-mode = ;"
Jonathan Marek (3):
dt-bindings: msm: dsi: add missing 7nm bindings
dt-bindings: msm: dsi: document phy-type property for 7nm dsi phy
drm/msm/dsi: support CPHY mode for 7nm pll/phy
.../bindings/display/msm/dsi-phy-7nm.yaml | 70 ++
These got lost when going from .txt to .yaml bindings, add them back.
Signed-off-by: Jonathan Marek
---
.../bindings/display/msm/dsi-phy-7nm.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
Document a new phy-type property which will be used to determine whether
the phy should operate in D-PHY or C-PHY mode.
Signed-off-by: Jonathan Marek
---
.../devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 4
include/dt-bindings/phy/phy.h | 2
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/d
On 6/16/21 1:50 AM, rajee...@codeaurora.org wrote:
On 03-06-2021 01:32, rajee...@codeaurora.org wrote:
On 02-06-2021 02:28, Rob Herring wrote:
On Mon, May 31, 2021 at 07:03:53PM +0530, Rajeev Nandan wrote:
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-7nm
When woul
l bindings
- changed binding to "phy-type = ;"
v4:
- PHY_TYPE_{DPHY,CPHY} instead of PHY_TYPE_DSI_{DPHY,CPHY}
- use enum/default for phy-type property
- remove a stray semicolon in dts example
Jonathan Marek (3):
dt-bindings: msm: dsi: add missing 7nm bindings
dt-bindings: msm: ds
These got lost when going from .txt to .yaml bindings, add them back.
Signed-off-by: Jonathan Marek
---
.../bindings/display/msm/dsi-phy-7nm.yaml | 66 +++
1 file changed, 66 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
Document a new phy-type property which will be used to determine whether
the phy should operate in D-PHY or C-PHY mode.
Signed-off-by: Jonathan Marek
Reviewed-by: Laurent Pinchart
---
.../devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 5 +
include/dt-bindings/phy/phy.h
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/d
This won't work because a2xx freedreno userspace expects to own all the
perfcounters.
This will break perfcounters for userspace, and when userspace isn't
using perfcounters, this won't count correctly because userspace writes
0 to CP_PERFMON_CNTL at the start of every submit.
On 2/23/23 5:5
This patch broke drm/msm in 6.2-rc1 for me. drm_sched_entity_destroy()
never returns when exiting a process from gdb if it has a drm/msm fd
opened (if the fd is closed normally then it doesn't have this problem).
AFAIK GMU_ALWAYS_ON_COUNTER does not have the same value as
CP_ALWAYS_ON_COUNTER (only the same frequency), so changing this would
break userspace expecting to be able to compare the value returned by
MSM_PARAM_TIMESTAMP with CP timestamp values.
On 5/17/23 12:50 PM, Konrad Dybcio wrote:
Use
On 5/17/23 3:08 PM, Konrad Dybcio wrote:
On 17.05.2023 20:09, Jonathan Marek wrote:
AFAIK GMU_ALWAYS_ON_COUNTER does not have the same value as
CP_ALWAYS_ON_COUNTER (only the same frequency), so changing this would break
userspace expecting to be able to compare the value returned by
sm8550 has 16 vbif clients.
This fixes the extra 2 clients (DMA4/DMA5) not having their memtype
initialized. This fixes DMA4/DMA5 planes not displaying correctly.
Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
---
.../msm/disp/dpu1/catalog/dpu_
Note that with this, DMA4/DMA5 are still non-functional, but at least
display *something* in modetest instead of nothing or underflow.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 ++
cause INIT_LIST_HEAD won't have
been called on the list yet when going through the defer error path.
Changes in v2:
* Changed to not only check for EPROBE_DEFER
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 ++---
drivers/gpu/drm/msm/msm_gpu.c
On 7/9/20 4:00 PM, Akhil P Oommen wrote:
Newer targets support changing gpu frequency through HFI. So
use that wherever supported instead of the legacy method.
It was already using HFI on newer targets. Don't break it in one commit
then fix it in the next.
Signed-off-by: Akhil P Oommen
--
All DPU versions starting from 4.0 use the sdm845 version, so check for
that instead of checking each version individually. This chooses the right
function for sm8150 and sm8250.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 5 ++---
1 file changed, 2 insertions
This will allow supporting different hwcg tables for a6xx.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 25 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 8 +++
3 files changed, 20
Calculate the correct timings for displayport, from downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers
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