[PATCH v3 4/5] drm/msm/a6xx: add missing PC_DBG_ECO_CNTL bit for a640/a650

[Jonathan Marek]

See downstream's "disable_tseskip" flag.

Signed-off-by: Jonathan Marek <jonat...@marek.ca>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 853be7651623..bbbf90d86828 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -844,13 +844,15 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
        /* Setting the mem pool size */
        gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
 
-       /* Setting the primFifo thresholds default values */
+       /* Setting the primFifo thresholds default values,
+        * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
+       */
        if (adreno_is_a650(adreno_gpu))
-               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
+               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
        else if (adreno_is_a640(adreno_gpu))
-               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
+               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
        else
-               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
+               gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
 
        /* Set the AHB default slave response to "ERROR" */
        gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
-- 
2.26.1