On 23.02.21 13:07, Daniel Vetter wrote:
On Thu, Feb 18, 2021 at 5:02 PM Andrzej Hajda wrote:
Hi Michael,
W dniu 18.02.2021 o 09:04, Michael Tretter pisze:
On Wed, 10 Feb 2021 10:10:37 +0100, Frieder Schrempf wrote:
On 04.02.21 18:46, Daniel Vetter wrote:
On Thu, Feb 4, 2021 at 6:26 PM
On 22.04.21 00:31, Marek Vasut wrote:
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge
and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS
bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on,
but easy to add.
The driver operates the chip
On 22.04.21 00:31, Marek Vasut wrote:
Add DT binding document for TI SN65DSI83 and SN65DSI84 DSI to LVDS bridge.
Signed-off-by: Marek Vasut
Cc: Douglas Anderson
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Rob Herring
Cc: Sam Ravnborg
Cc: Stephen Boyd
Cc: devicet...@vger.ker
On 28.04.21 09:51, Frieder Schrempf wrote:
On 22.04.21 00:31, Marek Vasut wrote:
Add driver for TI SN65DSI83 Single-link DSI to Single-link LVDS bridge
and TI SN65DSI84 Single-link DSI to Dual-link or 2x Single-link LVDS
bridge. TI SN65DSI85 is unsupported due to lack of hardware to test on
On 28.04.21 16:16, Marek Vasut wrote:
On 4/28/21 11:24 AM, Neil Armstrong wrote:
[...]
+static int sn65dsi83_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ enum sn65dsi83_model model;
+ struct sn65dsi83 *ctx;
+
On 04.02.21 18:46, Daniel Vetter wrote:
On Thu, Feb 4, 2021 at 6:26 PM Laurent Pinchart
wrote:
Hi Daniel,
On Thu, Feb 04, 2021 at 06:19:22PM +0100, Daniel Vetter wrote:
On Thu, Feb 4, 2021 at 5:28 PM Andrzej Hajda wrote:
W dniu 04.02.2021 o 17:05, Daniel Vetter pisze:
On Thu, Feb 04, 2021
in the panel driver I get
distorted colors. I need to use MEDIA_BUS_FMT_RGB888_1X24 to make it work, but
this is not valid for LVDS. Again I don't think this driver is to blame as I
can't see where it does anything wrong, but my experience here is very limited
so I still want
On 06.05.21 17:46, Marek Vasut wrote:
> On 5/6/21 5:38 PM, Frieder Schrempf wrote:
> [...]
>> Works on i.MX8MM with SN65DSI84 and a single link LVDS display (1024x600)
>> and from my perspective everything else also looks good. Thanks for your
>> work!
>>
>>
ented, the
> LVDS666 is not supported, but could be added if needed.
>
> Reviewed-by: Linus Walleij
> Reviewed-by: Frieder Schrempf
> Tested-by: Frieder Schrempf
> Signed-off-by: Marek Vasut
> Cc: Douglas Anderson
> Cc: Jagan Teki
> Cc: Laurent Pinchart
> Cc: Linus W
Hi Maxime,
On 03.12.20 14:25, Maxime Ripard wrote:
From: Dave Stevenson
The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register
definitions were swapped, so trying to use more than a single data
lane failed as lane 1 would get powered down.
(In theory a 4 lane device would work as a
On 05.10.20 15:42, Marek Vasut wrote:
The value programmed into horizontal porch and sync registers must be
scaled to the correct number of DSI lanes and bpp, make it so.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Guido Günther
Cc: Jaehoon Chung
Cc: Lucas Stach
Cc: Marek Szyprowski
C
Hi Jagan,
Am 03.03.22 um 17:36 schrieb Jagan Teki:
> Updated series about drm bridge conversion of exynos dsi.
>
> Previous version can be accessible, here [1].
>
> Patch 1: tc358764 panel_bridge API
>
> Patch 2: connector reset
>
> Patch 3: bridge attach in MIC
>
> Patch 4: panel_bridge API
Hi Jagan,
Am 09.03.22 um 15:01 schrieb Jagan Teki:
> Hi Frieder,
>
> On Wed, Mar 9, 2022 at 6:54 PM Frieder Schrempf
> wrote:
>>
>> Hi Jagan,
>>
>> Am 03.03.22 um 17:36 schrieb Jagan Teki:
>>> Updated series about drm bridge conversion of exynos ds
Am 10.03.22 um 14:03 schrieb Frieder Schrempf:
> Hi Jagan,
>
> Am 09.03.22 um 15:01 schrieb Jagan Teki:
>> Hi Frieder,
>>
>> On Wed, Mar 9, 2022 at 6:54 PM Frieder Schrempf
>> wrote:
>>>
>>> Hi Jagan,
>>>
>>> Am 03.03
Hi Lucas,
On 14.12.20 14:06, Lucas Stach wrote:
Hi Frieder,
Am Montag, den 14.12.2020, 13:33 +0100 schrieb Frieder Schrempf:
Hi Lucas, hi Marek,
while doing some tests on i.MX8MM with Etnaviv and mxsfb-drm (using the
patches for DSIM, GPC, BLK-CTL, etc., see branch at [1]), I noticed that
I
Hi Lucas, hi Marek,
while doing some tests on i.MX8MM with Etnaviv and mxsfb-drm (using the
patches for DSIM, GPC, BLK-CTL, etc., see branch at [1]), I noticed that
I don't seem to be able to run glmark2:
~# glmark2-es2-drm
===
glmark2 2
Am 10.06.22 um 09:52 schrieb Lucas Stach:
> Hi,
>
> Am Mittwoch, dem 11.05.2022 um 16:58 +0200 schrieb Marek Szyprowski:
>> Hi Dave,
>>
>> On 05.04.2022 13:43, Dave Stevenson wrote:
>>> On Fri, 18 Mar 2022 at 12:25, Dave Stevenson
>>> wrote:
On Fri, 4 Mar 2022 at 15:18, Dave Stevenson
Hi Dave,
Am 06.07.22 um 12:27 schrieb Dave Stevenson:
> Hi Frieder.
>
> Apologies Lucas - I missed your response.
>
> On Wed, 6 Jul 2022 at 08:09, Frieder Schrempf
> wrote:
>>
>> Am 10.06.22 um 09:52 schrieb Lucas Stach:
>>> Hi,
>>>
>>>
Am 05.04.22 um 23:36 schrieb Marek Vasut:
> On 4/5/22 17:24, Dave Stevenson wrote:
>
> Hi,
>
>> If we can initialise the DSI host before the bridge for the
>> pre_enable, then all the configuration moves to the atomic_pre_enable
>> and there should be no need to have the delay.
>>
Hi Jagan, Marek,
Am 07.09.22 um 12:04 schrieb Marek Szyprowski:
> Hi Jagan,
>
> On 06.09.2022 21:07, Jagan Teki wrote:
>> On Mon, Sep 5, 2022 at 4:54 PM Marek Szyprowski
>> wrote:
>>> On 02.09.2022 12:47, Marek Szyprowski wrote:
On 29.08.2022 20:40, Jagan Teki wrote:
> Samsung MIPI DSIM
Hi Jagan,
On 24.06.21 10:30, Krzysztof Kozlowski wrote:
> On 24/06/2021 04:48, Fabio Estevam wrote:
>> Hi Jagan/Laurent,
>>
>> On Wed, Jun 23, 2021 at 7:23 PM Laurent Pinchart
>> wrote:
>>
>>> Looking at the register set, it seems to match the Exynos 5433,
>>> supported by drivers/gpu/drm/exynos/
>
> Patch 0012 - 0013: component vs bridge
>
> Patch 0014 : DSIM bridge
>
> Patch 0015 - 0016: i.MX8M Mini/Nano
>
> Patch 0017 - 0018: i.MX8M Plus
>
> Changes for v12:
> - collect RB from Marek V
> - add te_irq_handler hook
> - fix comments from Marek V
>
On 03.02.23 13:29, Rasmus Villemoes wrote:
> On 01/02/2023 23.00, Marek Vasut wrote:
>> On 1/30/23 13:45, Rasmus Villemoes wrote:
>>> On 27/01/2023 12.30, Marek Vasut wrote:
On 1/27/23 12:04, Jagan Teki wrote:
>>>
>> Thanks, but that's exactly what I'm doing, and I don't see any
>> mod
On 17.02.23 19:22, Rasmus Villemoes wrote:
> On 07/02/2023 10.09, Rasmus Villemoes wrote:
>
>> I managed to get the whole chain lcdif -> mipi -> bridge -> dp-connector
>> to probe with these settings
>>
> [...]
>> Now hotplug-detect doesn't work with the current sn65dsi86 driver, but
>> that's a s
On 05.03.23 20:45, Patrick Boettcher wrote:
> [Sie erhalten nicht häufig E-Mails von patrick.boettc...@posteo.de. Weitere
> Informationen, warum dies wichtig ist, finden Sie unter
> https://aka.ms/LearnAboutSenderIdentification ]
>
> On Mon, 6 Mar 2023 00:05:03 +0530
> Jagan Teki wrote:
>
>> O
On 20.01.23 20:42, Dave Stevenson wrote:
> Hi Jagan
>
> On Fri, 20 Jan 2023 at 19:10, Jagan Teki wrote:
>>
>> Hi Dave,
>>
>> On Sat, Jan 21, 2023 at 12:26 AM Dave Stevenson
>> wrote:
>>>
>>> Hi Jagan
>>>
>>> Responding due to Marek's comment on the "Add Samsung MIPI DSIM
>>> bridge" series, alth
On 23.01.23 13:23, Jagan Teki wrote:
> Samsung MIPI DSIM bridge can also be found in i.MX8M Plus SoC.
>
> Add dt-bingings for it.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v11:
> - collect ACK from Rob
Tag is missing
> Changes for v10, v9:
> - none
>
> Documentation/devicetree/bindin
Hi Jagan,
On 10.11.22 19:38, Jagan Teki wrote:
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
>
> The final bridge supports both the Exynos and i.MX8M Mini/Nano/Plus.
>
> Changes for v8:
> * fixed comment lines
> * fixed commit mes
On 15.11.22 09:09, Marek Szyprowski wrote:
> Hi Jagan,
>
> On 14.11.2022 18:07, Jagan Teki wrote:
>> On Mon, Nov 14, 2022 at 8:10 PM Marek Szyprowski
>> wrote:
>>> On 14.11.2022 11:57, Marek Szyprowski wrote:
On 10.11.2022 19:38, Jagan Teki wrote:
> Finding the right input bus format thr
From: Frieder Schrempf
The datasheet specifies a delay of 10 milliseconds, but the current
driver only waits for 1 ms. Fix this to make sure the initialization
sequence meets the spec.
Fixes: ceb515ba29ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84
driver")
Sig
On 24.11.22 12:00, Alexander Stein wrote:
> Am Dienstag, 22. November 2022, 09:12:18 CET schrieb Frieder Schrempf:
>> From: Frieder Schrempf
>>
>> The datasheet specifies a delay of 10 milliseconds, but the current
>> driver only waits for 1 ms. Fix this to m
> Patch 0009: document fsl,imx8mm-mipi-dsim
>
> Patch 0010: add i.MX8MM DSIM support
>
> Tested in Engicam i.Core MX8M Mini SoM.
>
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v7
>
> Any inputs?
> Jagan.
I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
and a Jenson 7" LVDS Display.
Thanks for your work, Jagan!
Tested-by: Frieder Schrempf # Kontron DL
i.MX8MM
On 02.12.22 15:55, Dave Stevenson wrote:
> Hi Marek
>
> On Fri, 2 Dec 2022 at 12:21, Marek Vasut wrote:
>>
>> On 12/2/22 11:52, Marek Szyprowski wrote:
>>> Hi,
>>>
>>> Sorry for delay, I was on a sick leave last 2 weeks.
>>>
>>> On 28.11.2022 15:43, Jagan Teki wrote:
,On Sat, Nov 26, 2022 at
rea (optional).
>>>
>>> 0 = Disables transfer
>>> 1 = Enables transfer
>>>
>>> In command mode, this bit is ignored.
>>
>> Okay. I'd suggest adding a comment in the code, it'd be so tempting to
>> attempt to "fix" this as the if/or pattern looks different from the
>> others.
>>
>> But it's up to you all.
>
> I agree. Clearly the discrepancy is confusing and leads to mistakes.
+1 for a comment in the code that explains the misnamed bit.
Otherwise:
Reviewed-By: Frieder Schrempf
On 10.11.22 19:38, Jagan Teki wrote:
> HSA/HBP/HFP/HSE mode bits in Exynos DSI host specify a naming
> conversion as 'disable mode bit' due to its bit definition,
> 0 = Enable and 1 = Disable.
>
> Fix the naming convention of the mode bits.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/gpu/drm/
M Mini SoM.
>
> Repo:
> https://gitlab.com/openedev/kernel/-/commits/imx8mm-dsi-v8
>
> Any inputs?
> Jagan.
I tested this on the Kontron DL i.MX8MM which uses a TI SN65DSI84 bridge
and a Jenson 7" LVDS Display.
Tested-by: Frieder Schrempf # Kontron DL
i.MX8MM
Hi Dave,
On 05.12.22 16:20, Dave Stevenson wrote:
> Hi Frieder
>
> On Mon, 5 Dec 2022 at 07:30, Frieder Schrempf
> wrote:
>>
>> On 02.12.22 15:55, Dave Stevenson wrote:
>>> Hi Marek
>>>
>>> On Fri, 2 Dec 2022 at 12:21, Marek Vasut wrote:
ng
the function calls and capturing the DSI data signal and the SN65DSI84
enable GPIO (EN) on a scope.
I've also gone through the code of this patch and it all makes sense to
me. There is only one small nitpick (see below).
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
On 05.12.22 16:37, Frieder Schrempf wrote:
> Hi Dave,
>
> On 05.12.22 16:20, Dave Stevenson wrote:
>> Hi Frieder
>>
>> On Mon, 5 Dec 2022 at 07:30, Frieder Schrempf
>> wrote:
>>>
>>> On 02.12.22 15:55, Dave Stevenson wrote:
>>>> Hi
On 09.12.22 15:49, Marek Vasut wrote:
> On 12/9/22 14:38, Alexander Stein wrote:
>> Am Freitag, 9. Dezember 2022, 13:43:02 CET schrieb Marek Vasut:
>>> On 12/9/22 13:21, Alexander Stein wrote:
Hi Marek,
Am Freitag, 9. Dezember 2022, 13:02:10 CET schrieb Marek Vasut:
> On 12/9/22
On 12.12.22 10:32, Laurent Pinchart wrote:
> On Mon, Dec 12, 2022 at 10:09:45AM +0100, Frieder Schrempf wrote:
>> On 09.12.22 15:49, Marek Vasut wrote:
>>> On 12/9/22 14:38, Alexander Stein wrote:
>>>> Am Freitag, 9. Dezember 2022, 13:43:02 CET schrieb Marek
On 12.12.22 10:23, Krzysztof Kozlowski wrote:
> On 12/12/2022 10:09, Frieder Schrempf wrote:
>>>>> This does seem like a hardware bug right there, can you double-check
>>>>> this with the hardware engineer ?
>>>>
>>>> Yep, checked with hardw
ung-s6e panels for this change.
>
> This makes sure that the previous controller, likely to be a DSI
> host controller should be initialized to LP-11 before the panel
> is powered up.
>
> Signed-off-by: Marek Szyprowski
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
ious bridge should be initialized
> properly before the tc358764 bridge is powered up.
>
> Signed-off-by: Marek Szyprowski
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
rek Szyprowski
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
orted-by: Sébastien Szymanski
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
sable
> bit however the driver logic for handling HSE is based on the
> MIPI_DSI_MODE_VIDEO_HSE flag itself.
>
> Cc: Nicolas Boichat
> Reviewed-by: Marek Vasut
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
i.MX8M blk-ctrl driver.
>
> So, mark the phy get as optional.
>
> Reviewed-by: Marek Vasut
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
3250,
> + DSIM_TYPE_EXYNOS4210,
> + DSIM_TYPE_EXYNOS5410,
> + DSIM_TYPE_EXYNOS5422,
> + DSIM_TYPE_EXYNOS5433,
> +
The empty line looks a bit awkward to me. Otherwise:
Reviewed-by: Frieder Schrempf
> + DSIM_TYPE_COUNT,
> +};
> +
[...]
s common across all classes of DSI device drivers.
>
> The host init during pre_enable is conditional and not invoked for Exynos
> as existing downstream drm panels and bridges in Exynos are expecting
> the host initialization during DSI transfer.
>
> Signed-off-by: Jagan Tek
e inverted HS/VS/DE signals, i.e. active LOW.
>
> No clear evidence about whether it can be documentation issues or
> something, so added a comment FIXME for this and updated the active low
> sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type.
>
> Comments are suggested by Marek Vasut.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
On 15.12.22 09:39, Frieder Schrempf wrote:
> On 14.12.22 13:58, Jagan Teki wrote:
>> Look like an explicit fixing up of mode_flags is required for DSIM IP
>> present in i.MX8M Mini/Nano SoCs.
>>
>> At least the LCDIF + DSIM needs active low sync polarities in order
>&
l bus flags DE_LOW setting via input_bus_flags
> for i.MX8M Mini/Nano platforms.
>
> Suggested-by: Marek Vasut
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
ats
>
> Tested-by: Marek Szyprowski
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
On 14.12.22 13:59, Jagan Teki wrote:
> Samsung MIPI DSIM master can also be found in i.MX8M Mini/Nano SoC.
>
> Add compatible and associated driver_data for it.
>
> Reviewed-by: Laurent Pinchart
> Signed-off-by: Marek Szyprowski
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
th the i.MX8M Mini/Nano one.
>
> Signed-off-by: Marek Vasut
> Signed-off-by: Jagan Teki
Reviewed-by: Frieder Schrempf
From: Frieder Schrempf
This patchset contains a proposal to fix the initialization flow for
the display pipeline used on our i.MX8MM Kontron boards:
i.MX8MM LCDIF -> i.MX8MM DSIM -> TI SN65DSI84 -> 7" LVDS Panel
Without these changes the display works most of the time, but fa
From: Frieder Schrempf
According to the documentation [1] the proper enable flow is:
1. Enable DSI link and keep data lanes in LP-11 (stop state)
2. Disable stop state to bring data lanes into HS mode
Currently we do this all at once within enable(), which doesn't
allow to mee
From: Frieder Schrempf
The datasheet describes the following initialization flow including
minimum delay times between each step:
1. DSI data lanes need to be in LP-11 and the clock lane in HS mode
2. toggle EN signal
3. initialize registers
4. enable PLL
5. soft reset
6. enable DSI stream
7
From: Frieder Schrempf
Assuming that with the init flow fixed to meet the documentation at
[1] and the pre_enable_prev_first flag set in downstream bridge/panel
drivers which require it, we can use the default flow for Exynos as
already done for i.MX8M.
[1] https://docs.kernel.org/gpu/drm-kms
On 18.04.23 15:12, Marek Szyprowski wrote:
> On 18.04.2023 12:42, Frieder Schrempf wrote:
>> From: Frieder Schrempf
>>
>> Assuming that with the init flow fixed to meet the documentation at
>> [1] and the pre_enable_prev_first flag set in downstream bridge/panel
>
> Signed-off-by: Lucas Stach
> Signed-off-by: Adam Ford
> Tested-by: Chen-Yu Tsai
Tested-by: Frieder Schrempf
m: Add i.MX8M Mini/Nano
> support")
> Signed-off-by: Adam Ford
> Reviewed-by: Lucas Stach
> Tested-by: Chen-Yu Tsai
Tested on Kontron BL i.MX8MM with SN65DSI84 and ADV7535 bridges.
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
ord
> Tested-by: Chen-Yu Tsai
Tested on Kontron BL i.MX8MM with SN65DSI84 and ADV7535 bridges.
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
Adam Ford
This fixes the build error which existed in v2!
Tested on Kontron BL i.MX8MM with SN65DSI84 and ADV7535 bridges.
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
herwise:
Tested on Kontron BL i.MX8MM with SN65DSI84 and ADV7535 bridges.
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
> ---
> drivers/gpu/drm/bridge/samsung-dsim.c | 79 +++
> include/drm/bridge/samsung-dsim.h | 1 +
> 2 files changed, 7
e like an HDMI bridge chip. This should have no
> impact for people using burst-mode and setting the burst
> clock rate is still required for those users.
>
> Signed-off-by: Adam Ford
> Tested-by: Chen-Yu Tsai
Tested on Kontron BL i.MX8MM with SN65DSI84 and ADV7535 bridges.
T
from that:
Tested on Kontron BL i.MX8MM with SN65DSI84 and ADV7535 bridges.
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
> ---
> drivers/gpu/drm/bridge/samsung-dsim.c | 4 +++-
> include/drm/bridge/samsung-dsim.h | 1 +
> 2 files changed, 4 insertions(+), 1 deletion(
From: Frieder Schrempf
This patchset contains a proposal to fix the initialization flow for
the display pipeline used on our i.MX8MM Kontron boards:
i.MX8MM LCDIF -> i.MX8MM DSIM -> TI SN65DSI84 -> 7" LVDS Panel
Without these changes the display works most of the time, but fa
From: Frieder Schrempf
According to the documentation [1] the proper enable flow is:
1. Enable DSI link and keep data lanes in LP-11 (stop state)
2. Disable stop state to bring data lanes into HS mode
Currently we do this all at once within enable(), which doesn't
allow to mee
From: Frieder Schrempf
The datasheet describes the following initialization flow including
minimum delay times between each step:
1. DSI data lanes need to be in LP-11 and the clock lane in HS mode
2. toggle EN signal
3. initialize registers
4. enable PLL
5. soft reset
6. enable DSI stream
7
On 17.05.23 00:22, Fabio Estevam wrote:
> On Thu, May 4, 2023 at 6:12 AM Alexander Stein
> wrote:
>>
>> Am Mittwoch, 3. Mai 2023, 18:33:07 CEST schrieb Frieder Schrempf:
>>> From: Frieder Schrempf
>>>
>>> The datasheet describes the following initiali
On 19.07.23 18:34, Tim Harvey wrote:
> On Wed, Jul 19, 2023 at 12:05 AM Frieder Schrempf
> wrote:
>>
>> Hi Tim,
>>
>> On 19.07.23 01:03, Tim Harvey wrote:
>>> On Thu, Jul 13, 2023 at 3:01 AM Frieder Schrempf
>>> wrote:
>>>>
>
v7533: Initial support for ADV7533")
> Reviewed-by: Robert Foss
> Reviewed-by: Nuno Sa
> Signed-off-by: Bogdan Togorean
> Signed-off-by: Alexandru Ardelean
Reviewed-by: Frieder Schrempf
From: Frieder Schrempf
In case the downstream bridge or panel uses DSI transfers before the
DSI host was actually initialized through samsung_dsim_atomic_enable()
which clears the stop state (LP11) mode, all transfers will fail.
This happens with downstream bridges that are controlled by DSI
From: Frieder Schrempf
In case the downstream bridge or panel uses DSI transfers before the
DSI host was actually initialized through samsung_dsim_atomic_enable()
which clears the stop state (LP11) mode, all transfers will fail.
This happens with downstream bridges that are controlled by DSI
Vasut
I tested this on our Kontron BL i.MX8MP board. Feel free to add:
Tested-by: Frieder Schrempf
wered up and told about the polarity of the video
> sync signals to act in bypass mode.
>
> Signed-off-by: Lucas Stach
> Tested-by: Marek Vasut
I tested this on our Kontron BL i.MX8MP board. Feel free to add:
Tested-by: Frieder Schrempf
Lucas, any chance that you can revive this seri
On 07.07.23 21:00, Vladimir Lypak wrote:
> [Sie erhalten nicht häufig E-Mails von vladimir.ly...@gmail.com. Weitere
> Informationen, warum dies wichtig ist, finden Sie unter
> https://aka.ms/LearnAboutSenderIdentification ]
>
> In function drm_atomic_bridge_chain_post_disable handling of
> pre_e
Hi Tim,
On 13.07.23 00:34, Tim Harvey wrote:
> On Wed, May 3, 2023 at 9:33 AM Frieder Schrempf wrote:
>>
>> From: Frieder Schrempf
>>
>> According to the documentation [1] the proper enable flow is:
>>
>> 1. Enable DSI link and keep data lanes in LP-11 (
Hi Tim,
On 13.07.23 09:18, Frieder Schrempf wrote:
> Hi Tim,
>
> On 13.07.23 00:34, Tim Harvey wrote:
>> On Wed, May 3, 2023 at 9:33 AM Frieder Schrempf wrote:
>>>
>>> From: Frieder Schrempf
>>>
>>> According to the documentation [1] the pr
On 14.07.23 19:16, Dave Stevenson wrote:
> Hi Frieder
>
> On Mon, 10 Jul 2023 at 08:46, Frieder Schrempf
> wrote:
>>
>> On 07.07.23 21:00, Vladimir Lypak wrote:
>>> [Sie erhalten nicht häufig E-Mails von vladimir.ly...@gmail.com. Weitere
>>> Informa
Hi Tim,
On 19.07.23 01:03, Tim Harvey wrote:
> On Thu, Jul 13, 2023 at 3:01 AM Frieder Schrempf
> wrote:
>>
>> Hi Tim,
>>
>> On 13.07.23 09:18, Frieder Schrempf wrote:
>>> Hi Tim,
>>>
>>> On 13.07.23 00:34, Tim Harvey wrote:
&g
Hi Adam,
On 27.08.24 2:25 AM, Adam Ford wrote:
> On Wed, Aug 21, 2024 at 8:59 PM Adam Ford wrote:
>>
>> On Wed, Aug 21, 2024 at 7:45 AM Adam Ford wrote:
>>>
>>> On Tue, Aug 20, 2024 at 10:58 PM Dominique MARTINET
>>> wrote:
Adam Ford wrote on Tue, Aug 20, 2024 at 09:49:03PM -0500:
>>>
From: Frieder Schrempf
The Jenson BL-JT60050-01A is a 7" 1024x600 LVDS display.
Signed-off-by: Frieder Schrempf
Acked-by: Conor Dooley
---
Changes for v2:
* Add tag from Conor (thanks!)
---
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++
1 file changed, 2 inser
From: Frieder Schrempf
This add support for the display bridges (DSI->LVDS and DSI->HDMI)
on the BL i.MX8MM and the 7" LVDS panel in a separate overlay.
Only one of the interfaces (HDMI or LVDS) is supported at the same
time. Enabling the LVDS overlay will disable the HDMI interface.
On 04.09.24 10:31 AM, Dominique Martinet wrote:
> This allows the hdmi driver to pick e.g. 64.8MHz instead of 65Mhz when we
> cannot output the exact frequency, enabling the imx8mp HDMI output to
> support more modes
>
> Signed-off-by: Dominique Martinet
Reviewed-by: Frieder Schr
On 06.09.24 3:46 AM, Adam Ford wrote:
> I have been testing various settings on the HDMI out of the i.MX8MP.
>
> I noticed that sometimes my monitor would not sync, but sometimes it
> would on the same resolution/refresh rate. Frieder noted the LCDIF
> was sometimes underflowing, so read up on it
On 09.09.24 5:00 AM, Peng Fan wrote:
>> Subject: Re: i.MX8MP IMX-LCDIF Underrun Question(s)
>>
>> On 06.09.24 3:46 AM, Adam Ford wrote:
>>> I have been testing various settings on the HDMI out of the i.MX8MP.
>>>
>>> I noticed that sometimes my monitor would not sync, but sometimes
>> it
>>> would
s. Maybe there is still an error in the
> calculation of the porches and someone at NXP can chime in.
Thanks for working on this! We tested these patches with our Kontron BL
i.MX8MM board and a "10.1inch HDMI LCD (E)" display from Waveshare [1].
Without this series we don't
On 04.09.23 16:02, Frieder Schrempf wrote:
> Hi Michael,
>
> On 28.08.23 17:59, Michael Tretter wrote:
>> I tested the i.MX8M Nano EVK with the NXP supplied MIPI-DSI adapter,
>> which uses an ADV7535 MIPI-DSI to HDMI converter. I found that a few
>> modes were wo
Hi Michael,
On 06.09.23 11:56, Michael Tretter wrote:
> Hi Frieder,
>
> On Wed, 06 Sep 2023 11:31:45 +0200, Frieder Schrempf wrote:
>> On 04.09.23 16:02, Frieder Schrempf wrote:
>>> On 28.08.23 17:59, Michael Tretter wrote:
>>>> I tested the i.MX8M Nano EVK wi
On 07.03.24 09:09, Sean Nyekjaer wrote:
> Hi,
>
> We are using the stm32mp1 together with the sn65dsi83 bridge.
> The ti,sn65dsi83 driver is (hard) enabling MIPI_DSI_MODE_VIDEO_BURST, then
> the st,stm32-dsi driver is adding +20% to the clock speed.
>
> That means our LVDS is +20% higher than ex
h the ADV7535 bridge and
I don't see any change when trying the 30 different modes the monitor
reports as supported. 18 of those work and 12 don't work.
So at least there is no negative impact in this case.
Tested-by: Frieder Schrempf # Kontron BL
i.MX8MM with HDMI monitor
Thanks
Frieder
On 26.10.23 13:30, Emil Abildgaard Svendsen wrote:
> [Sie erhalten nicht häufig E-Mails von e...@bang-olufsen.dk. Weitere
> Informationen, warum dies wichtig ist, finden Sie unter
> https://aka.ms/LearnAboutSenderIdentification ]
>
> Currently reading EDID only works because usually only two EDI
From: Frieder Schrempf
The Jenson BL-JT60050-01A is a 7" 1024x600 LVDS display.
Signed-off-by: Frieder Schrempf
---
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/
From: Frieder Schrempf
This add support for the display bridges (DSI->LVDS and DSI->HDMI)
on the BL i.MX8MM and the 7" LVDS panel in a separate overlay.
Only one of the interfaces (HDMI or LVDS) is supported at the same
time. Enabling the LVDS overlay will disable the HDMI interface.
Hi Dominique, hi Lucas,
On 17.06.24 6:32 PM, Lucas Stach wrote:
> Hi Dominique,
>
> Am Montag, dem 17.06.2024 um 15:16 +0900 schrieb Dominique MARTINET:
>> Adam Ford wrote on Sat, Feb 03, 2024 at 10:52:50AM -0600:
>>> From: Lucas Stach
>>>
>>> Add a simple wrapper driver for the DWC HDMI bridge
ipment to verify the changes back then.
Instead, we had an automated test setup to do cyclic on/off switching
for the display and check for a black screen using a sensor. It is quite
a hassle to set up and I'm currently not planning to spend that much
effort to verify this change again.
Anyway, I currently don't see any reasons to not revert my changes. Your
revert looks correct and seems to work fine as far as I can tell.
Reviewed-by: Frieder Schrempf
Thanks
Frieder
On 29.02.24 10:47, Luca Ceresoli wrote:
> Hello Alexander,
>
> On Wed, 28 Feb 2024 09:15:46 +0100
> Alexander Stein wrote:
>
>
> [...]
>
>> Oh I mistook this DSI-LVDS bridge with the DSI-DP bridge on a different
>> board, my bad. I hope I can provide some insights. My platform is
>> imx8mm-tqm
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