On Tue, Apr 20, 2021 at 3:18 AM Daniel Stone wrote:
>
> Hi,
>
> On Mon, 19 Apr 2021 at 13:06, Simon Ser wrote:
>>
>> I'm working on a Wayland extension [1] that, among other things, allows
>> compositors to advertise the preferred device to be used by Wayland
>> clients.
>>
>> In general, composi
This enables the adreno-specific SMMU path that sets HUPCF so
(user-managed) page faults don't wedge the GPU.
Signed-off-by: Eric Anholt
---
We've been seeing a flaky test per day or so in Mesa CI where the
kernel gets wedged after an iommu fault turns into CP errors. With
this pat
db820c wants to use the qcom smmu path to get HUPCF set (which keeps
the GPU from wedging and then sometimes wedging the kernel after a
page fault), but it doesn't have separate pagetables support yet in
drm/msm so we can't go all the way to the TTBR1 path.
Signed-off-by: Eric Anholt
On Mon, Mar 29, 2021 at 7:47 AM Will Deacon wrote:
>
> On Fri, Mar 26, 2021 at 04:13:02PM -0700, Eric Anholt wrote:
> > db820c wants to use the qcom smmu path to get HUPCF set (which keeps
> > the GPU from wedging and then sometimes wedging the kernel after a
> > page fau
We were using the same force-poweron bit in the two codepaths, so they
could race to have one of them lose GPU power early.
Signed-off-by: Eric Anholt
Cc: sta...@vger.kernel.org # v5.9
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 ++---
drivers/gpu/drm/msm/adreno
given that we start many tests in parallel, and waiting for NFS
to page in code probably means that lots of tests hit the same point
of screen init at the same time).
Signed-off-by: Eric Anholt
Cc: sta...@vger.kernel.org # v5.9
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
1 file changed, 4
Now that the bug is fixed in the minimal way for stable, go make the
code table-driven.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 124 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 55
2 files changed, 77 insertions(+), 102
Now that the bug is fixed in the minimal way for stable, go make the
code table-driven.
Signed-off-by: Eric Anholt
---
Previous version hadn't been rebased off of a bit of debug code I had,
so it wouldn't cleanly apply.
drivers/gpu/drm/msm/adreno/a6xx_g
On Thu, Jan 28, 2021 at 10:52 AM Jordan Crouse wrote:
>
> On Wed, Jan 27, 2021 at 03:39:44PM -0800, Eric Anholt wrote:
> > We were using the same force-poweron bit in the two codepaths, so they
> > could race to have one of them lose GPU power early.
> >
> > Sign
Updated commit messages over v2, no code changes.
Eric Anholt (3):
drm/msm: Fix race of GPU init vs timestamp power management.
drm/msm: Fix races managing the OOB state for timestamp vs timestamps.
drm/msm: Clean up GMU OOB set/clear handling.
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 105
patch, the message seems to
have completely gone away.
Signed-off-by: Eric Anholt
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/
.
Signed-off-by: Eric Anholt
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 ++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 8
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-
Now that the bug is fixed in the minimal way for stable, go make the
code table-driven.
Signed-off-by: Eric Anholt
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 124 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 55
2 files changed
On Thu, Feb 4, 2021 at 10:09 AM Chema Casanova wrote:
>
> On 3/9/20 18:48, Yukimasa Sugizaki wrote:
> > From: Yukimasa Sugizaki
> >
> > The default timeout is 500 ms which is too short for some workloads
> > including Piglit. Adding this parameter will help users to run heavier
> > tasks.
> >
>
Clean up GMU OOB set/clear handling")
> > Signed-off-by: Jonathan Marek
>
> Thanks. I feel silly that I missed that.
>
> Reviewed-by: Jordan Crouse
Yeah, oops.
Reviewed-by: Eric Anholt
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On Thu, Nov 5, 2020 at 10:25 AM Deepak R Varma wrote:
>
> idr_init() uses base 0 which is an invalid identifier for this driver.
> The idr_alloc for this driver uses VC4_PERFMONID_MIN as start value for
> ID range and it is #defined to 1. The new function idr_init_base allows
> IDR to set the ID l
R to set the ID lookup from base 1. This avoids all lookups that
> otherwise starts from 0 since 0 is always unused / available.
>
> References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
>
> Signed-off-by: Deepak R Varma
> ---
> Changes since v1:
&
Mario Kleiner writes:
> Hi Eric and all,
>
> this batch prevents setting modes one shouldn't set,
> adds precise vblank timestamping for interlaced video
> modes, and one fix for vblank en/disable during crtc
> en/disable.
>
> All successfully tested, also with timing measurement equipment,
> on
This came from the initial bringup code, which always idled the GPU
and always reset the overflow. That massively increases the size of
the working set when you're doing lots of small draws, though, as is
common on X desktops or piglit.
Signed-off-by: Eric Anholt
---
drivers/gpu/dr
with the Linux
> +kernel's guarantee to keep existing userspace running for 10+ years this is
> +already rather painful for the DRM subsystem, with multiple different uAPIs
> for
> +the same thing co-existing. If we'd add a few more complete mistakes into the
"If we&
Paul Kocialkowski writes:
> Hi,
>
> On Thu, 2019-04-25 at 10:42 -0700, Eric Anholt wrote:
>> Paul Kocialkowski writes:
>>
>> > The binner BO is not required until the V3D is in use, so avoid
>> > allocating it at probe and do it on the first non-dumb
James Clarke writes:
> Like GNU/Linux, GNU/kFreeBSD's sys/types.h does not define the uintX_t
> types, which differs from the BSDs' headers. Thus we should include
> stdint.h to ensure we have all the required integer types.
>
> Signed-off-by: James Clarke
ck wants to be:
if (vc4->bin_bo)
kref_get(&vc4->bin_bo_kref);
else
ret = bin_bo_alloc(vc4);
if (ret == 0 && used)
*used = true;
(so we don't flag used if bin_bo_alloc fails)
If you agree, then the s
Paul Kocialkowski writes:
> Changes sinve v8:
> * Added collected Reviewed-by;
> * Fixed up another problematic case as discussed on v8.
I think this is ready to go. Thanks!
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Eric Anholt writes:
> [ Unknown signature status ]
> James Clarke writes:
>
>> Like GNU/Linux, GNU/kFreeBSD's sys/types.h does not define the uintX_t
>> types, which differs from the BSDs' headers. Thus we should include
>> stdint.h to ensure we have all the
Daniel Vetter writes:
> On Wed, Apr 24, 2019 at 03:06:38PM -0700, Eric Anholt wrote:
>> I was trying to figure out if it was permissible to merge the Mesa
>> side of V3D's CSD support yet while it's in drm-misc-next but not
>> drm-next, and developers on #dri-deve
Alyssa Rosenzweig writes:
>> @@ -55,6 +63,15 @@ struct drm_panfrost_submit {
>>
>> /** A combination of PANFROST_JD_REQ_* */
>> __u32 requirements;
>> +
>> +/** Pointer to a u32 array of perfmons that should be attached to the
>> job. */
>> +__u64 perfmon_handles;
>> +
>> +
Hoegeun Kwon writes:
> On 4/2/19 2:48 AM, Eric Anholt wrote:
>> Hoegeun Kwon writes:
>>
>>> There is a problem when often dpms goes from off to on. pm idle is not
>>> in sync and the problem occurs. Modify pm_runtime_put from
>>> asynchronous to s
Rob Herring writes:
> On Mon, Apr 1, 2019 at 10:43 AM Eric Anholt wrote:
>>
>> Chris Wilson writes:
>>
>> > Quoting Daniel Vetter (2019-04-01 14:06:48)
>> >> On Mon, Apr 1, 2019 at 9:47 AM Rob Herring wrote:
>> >> > +{
>> >>
, void *data,
> + struct drm_file *file_priv)
> +{
> + struct drm_panfrost_get_bo_offset *args = data;
> + struct drm_gem_object *gem_obj;
> + struct panfrost_gem_object *bo;
> +
Missing check for pad == 0. With that fixed,
Reviewed-by: Eric Anholt
> +
Eric Anholt writes:
> [ Unknown signature status ]
> Rob Herring writes:
>
>> This adds the initial driver for panfrost which supports Arm Mali
>> Midgard and Bifrost family of GPUs. Currently, only the T860 and
>> T760 Midgard GPUs have be
Paul Kocialkowski writes:
> Since the OOM interrupt directly deals with the binner bo, it doesn't
> make sense to try and handle it without a binner buffer registered.
>
> Signed-off-by: Paul Kocialkowski
> ---
> drivers/gpu/drm/vc4/vc4_irq.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff
Paul Kocialkowski writes:
> The binner bo is not required until the V3D is in use, so avoid
> allocating it at probe and do it on the first non-dumb BO allocation.
> Keep track of which clients are using the V3D and liberate the buffer
> when there is none left (through a kref) and protect it wit
Andrey Grodzovsky writes:
> From: Christian König
>
> We now destroy finished jobs from the worker thread to make sure that
> we never destroy a job currently in timeout processing.
> By this we avoid holding lock around ring mirror list in drm_sched_stop
> which should solve a deadlock reported
Qiang Yu writes:
> Indeed not that important, so patch 5&7 is:
> Reviewed-and-tested-by: Qiang Yu
Merged these two. Thanks for trying it out!
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All consumers wanted drm_gem_object * now.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.h | 4 ++--
drivers/gpu/drm/v3d/v3d_gem.c | 42 +--
2 files changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/v3d/v3d_drv.h b/drivers/gpu
code between the 4 queues.
v2: Fix missing error path in TFU ioctl's bo[] allocation.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.h | 77 +++
drivers/gpu/drm/v3d/v3d_gem.c | 365
drivers/gpu/drm/v3d/v3d_irq.c | 8 +-
drivers/gpu/dr
We only set the excl (possible-writing) fence pointer and never add a
shared (read-only) fence.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_gem.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index
ng in parallel,
particularly GL apps and compositors.
v2: Fix a missing refcount on the CSD done fence for L2 cleaning.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.h | 11 +++---
drivers/gpu/drm/v3d/v3d_gem.c | 63 +++--
drivers/gpu/drm/v3d/v3d_sched.c
This is a resend of my April 1st series, rebased on the merge of the
fence array helpers, and with little fixes for bugs reported by static
analysis and one minor race fix I noticed while re-reviewing.
Eric Anholt (5):
drm/v3d: Switch the type of job-> to reduce casting.
drm/v3d: Refactor
ed by userspace
before L2 cleaning is finished.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 22 +
drivers/gpu/drm/v3d/v3d_drv.c | 10 +-
drivers/gpu/drm/v3d/v3d_drv.h | 28 +-
drivers/gpu/drm/v3d/v3d_fence.c | 2 +
drivers/gpu/drm/v3d/v3d_
Christian König writes:
> Am 16.04.19 um 02:35 schrieb Karol Herbst:
>> Kobjects are supposed to be dynamically allocated, but with recent changes
>> this rule was violated. Reverting those commits fixes crashes when a drm
>> driver using TTM gets loaded again.
>>
>> The object in question is "tt
Eric Anholt writes:
> The compute shader dispatch interface is pretty simple -- just pass in
> the regs that userspace has passed us, with no CLs to run. However,
> with no CL to run it means that we need to do manual cache flushing of
> the L2 after the HW execution completes (for
g was based on the MMU VA_WIDTH for
the first platform I worked on and was wrong on others. In short,
this was a thorough mess from early HW enabling.
Tested on V3D 4.1 and 4.2 with intentional L2T, CLE, PTB, and TLB
faults.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.c
Looking at a hang recently, I noticed these registers that might tell
me if something obvious was wrong. They didn't help in this case, but
keep it around for the future.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 5
drivers/gpu/drm/v3d/v3d_gem.c
They're in the hub, not the individual cores.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c
b/drivers/gpu/drm/v3d/v3d_debugfs.c
index a2dc4262955e..356a8ac
On 7278, we've got 40 bits to work with.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 1 +
drivers/gpu/drm/v3d/v3d_drv.c | 6 +-
drivers/gpu/drm/v3d/v3d_regs.h| 8
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
Paul Kocialkowski writes:
> The binner BO is not required until the V3D is in use, so avoid
> allocating it at probe and do it on the first non-dumb BO allocation.
>
> Keep track of which clients are using the V3D and liberate the buffer
> when there is none left, using a kref. Protect the logic
Dave Airlie writes:
> I've been looking a bit at 5.0 for a few things recently, and I've
> noticed it shipped with a bunch of regressions, that I'm trying to
> smash.
>
> udl driver regression due to gem unlocked cleanup
> udl driver unload regression due to other unplug changes
> i915 + atomic x
s.
Signed-off-by: Eric Anholt
---
Personally, I thought the rule was "has to be in drm-next", but
assuming our review processes aren't totally broken, this should be
enough.
Documentation/gpu/drm-uapi.rst | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Docum
The point of this review process is that userspace using the new uAPI
can actually live with the uAPI being provided, and it's hard to know
that without having actually looked into a kernel patch yourself.
Signed-off-by: Eric Anholt
Suggested-by: Daniel Vetter
---
Documentation/gp
"Zhou, David(ChunMing)" writes:
> Will linux be only mesa-linux? I thought linux is an open linux.
> Which will impact our opengl/amdvlk(MIT open source), not sure Rocm:
> 1. how to deal with one uapi that opengl/amdvlk needs but mesa dont need?
> reject?
> 2. one hw feature that opengl/amdvlk
arning: Function parameter or member 'obj' not described in
> 'drm_gem_fence_array_add_implicit'
> drm_gem.c:1435: warning: Function parameter or member 'write' not described
> in 'drm_gem_fence_array_add_implicit'
Hopefully some day we can move t
's request.
Signed-off-by: Eric Anholt
---
Documentation/gpu/drm-uapi.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst
index c9fd23efd957..b7a96dc02d21 100644
--- a/Documentation/gpu/drm-uapi.rst
+++
ck);
if (vc4file->bin_bo_used) {
mutex_unlock(&vc4->bin_bo_lock);
vc4_v3d_bin_bo_put(vc4);
} else {
vc4file->bin_bo_used = true;
mutex_unlock(&vc4->bin_bo_lock);
}
that will be the last change we n
Boris Brezillon writes:
> +Rob, Eric, Mark and more
>
> Hi,
>
> On Fri, 5 Apr 2019 16:20:45 +0100
> Steven Price wrote:
>
>> On 04/04/2019 16:20, Boris Brezillon wrote:
>> > Hello,
>> >
>> > This patch adds new ioctls to expose GPU counters to userspace.
>> > These will be used by the mesa driv
Paul Kocialkowski writes:
> During an atomic commit, the HVS is configured with a display list
> for the channel matching the associated CRTC. The Pixel Valve (CRTC)
> and encoder are also configured for the new setup at that time.
> While the Pixel Valve and encoder are reconfigured synchronousl
Paul Kocialkowski writes:
> From: Boris Brezillon
>
> The DRM framework provides a generic way to report underrun errors.
> Let's implement the necessary hooks to support it in the VC4 driver.
>
> Signed-off-by: Boris Brezillon
> ---
> Changes in v3:
> - Generic underrun report function has bee
or cases where they have unique dma_fence_ops, and
>> > preferring to have descriptors for the whole fence context). strings do
>> > not pack as well into the ftrace ringbuffer and we would prefer to
>> > reduce the amount of indirect callbacks required for frequent tracepoin
Paul Kocialkowski writes:
> Hi Eric,
>
> On Wed, 2019-01-23 at 10:47 -0800, Eric Anholt wrote:
>> Paul Kocialkowski writes:
>> > +void vc4_hvs_mask_underrun(struct drm_device *dev)
>> > +{
>> > + struct vc4_dev *vc4 = to_vc4_dev(dev);
>&
Paul Kocialkowski writes:
> Hi,
>
> On Wed, 2019-01-23 at 10:34 -0800, Eric Anholt wrote:
>> Paul Kocialkowski writes:
>>
>> > During an atomic commit, the HVS is configured with a display list
>> > for the channel matching the associated CRTC. The Pixel
Noralf Trønnes writes:
> Den 28.01.2019 21.57, skrev Rob Herring:
>> On Sun, Dec 2, 2018 at 9:59 AM Noralf Trønnes wrote:
>>>
>>>
>>> Den 30.11.2018 00.58, skrev Eric Anholt:
>>>> Daniel Vetter writes:
>>>>
>>>>> On Wed
Rob Herring writes:
> Now that the base struct drm_gem_object has a reservation_object, use it
> and remove the private BO one.
>
> Cc: Eric Anholt
> Cc: Daniel Vetter
> Cc: David Airlie
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Rob Herr
Rob Herring writes:
> Now that the base struct drm_gem_object has a reservation_object, use it
> and remove the private BO one.
Reviewed-by: Eric Anholt
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Daniel Vetter writes:
>
> Zooming out more looking at the big picture I'd say all your work in the
> past few years has enormously simplified drm for simple drivers already.
> If we can't resolve this one here right now that just means you "only"
> made drm 98% simpler instead of maybe 99%. It's s
Qiang Yu writes:
> From: Lima Project Developers
>
> Signed-off-by: Andreas Baierl
> Signed-off-by: Erico Nunes
> Signed-off-by: Heiko Stuebner
> Signed-off-by: Marek Vasut
> Signed-off-by: Neil Armstrong
> Signed-off-by: Qiang Yu
> Signed-off-by: Simon Shields
> Signed-off-by: Vasily Kho
llback.
>
> With the addition, add a drm_gem_reservation_object_wait() helper
> function for drivers to use in wait ioctls.
1, 4, 5 are:
Reviewed-by: Eric Anholt
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The HW only executes a load once the tile coordinates packet happens,
and only tracks one at a time, so by emitting our two MSAA loads back
to back we would end up with an undefined color or Z buffer.
Fixes dEQP-EGL.functional.render.multi_context.gles2.rgb888_window
Signed-off-by: Eric Anholt
Paul Kocialkowski writes:
> When the pipeline is reconfigured with a different mode, changes take
> effect immediately for the CRTC and encoder while the HVS takes some
> time to switch the active display list. This results in a period of
> time where the pipeline is out of sync, that is very lik
ers/gpu/drm/vc4/vc4_kms.c
> @@ -139,6 +139,8 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
> struct drm_device *dev = state->dev;
> struct vc4_dev *vc4 = to_vc4_dev(dev);
>
> + vc4_hvs_mask_underrun(dev);
> +
> drm_atomic_help
Qiang Yu writes:
> On Thu, Feb 7, 2019 at 3:17 AM Eric Anholt wrote:
>>
>> Qiang Yu writes:
>> > +int lima_gem_wait(struct drm_file *file, u32 handle, u32 op, u64
>> > timeout_ns)
>> > +{
>> > + bool write = op & LIM
You'll get garbage measurements if the registers always read back
0xdeadbeef
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c
b/drivers/gpu/drm/v3d/v3d_debugfs.c
index eb2b2d2
ge is going away in favor of an external reset
controller in a larger HW module.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.c | 18 ++
drivers/gpu/drm/v3d/v3d_drv.h | 1 +
drivers/gpu/drm/v3d/v3d_gem.c | 12 +++-
drivers/gpu/drm/v3d/v3d_irq.c
The register now has another field, QRMAXCNT for how many TMU requests
get serviced before thread switch. We were accidentally reducing it
from its default of 0x3 (4 requests) to 0x0 (1).
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_gem.c | 4 +++-
drivers/gpu/drm/v3d/v3d_regs.h | 2
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c
index 22fff0d3aecd..1f22ce542a04 100644
--- a/drivers/gpu/drm/v3d/v3d_drv.c
+++ b/drivers/gpu/drm
"Gustavo A. R. Silva" writes:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
> struct foo {
> int stuff;
> void *entr
"Koenig, Christian" writes:
> Am 07.12.18 um 20:16 schrieb Eric Anholt:
>> The entity->dependency can go away completely once we've called
>> drm_sched_entity_add_dependency_cb() (if the cb is called before we
>> get around to tracing). The tracepo
We always decrement at GEM free, so make sure we increment at GEM
creation for dma-bufs.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_bo.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/v3d/v3d_bo.c b/drivers/gpu/drm/v3d/v3d_bo.c
index a08766d39eab
Thomas Spurden writes:
> On Thu, 7 Feb 2019 at 20:10, Eric Anholt wrote:
>>
>> Signed-off-by: Eric Anholt
>
> Reviewed-by: Thomas Spurden
Merged this one, will send out respins of the others.
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Daniel Vetter writes:
> On Thu, Feb 07, 2019 at 03:26:13PM -0800, Eric Anholt wrote:
>> We always decrement at GEM free, so make sure we increment at GEM
>> creation for dma-bufs.
>
> Indeed. Reviewed-by: Daniel Vetter
Merged to drm-misc-next. Thanks!
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the old field.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_gem.c | 3 ++-
drivers/gpu/drm/v3d/v3d_regs.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index 3ee3ae4d3cac..06538ffa3014 100644
--- a
You'll get garbage measurements if the registers always read back
0xdeadbeef
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c
b/drivers/gpu/drm/v3d/v3d_debugfs.c
index eb2b2d2
ge is going away in favor of an external reset
controller in a larger HW module.
v2: Use consistent checks for whether we're on 4.2, and fix a leak in
an error path.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.c | 19 +++
drivers/gpu/drm/v3d/v3d_drv.h | 1
Rob Herring writes:
> On Thu, Feb 7, 2019 at 9:51 AM Daniel Vetter wrote:
>>
>> On Thu, Feb 07, 2019 at 11:21:52PM +0800, Qiang Yu wrote:
>> > On Thu, Feb 7, 2019 at 5:09 PM Daniel Vetter wrote:
>> > >
>> > > On Wed, Feb 06, 2019 at 09:14:55PM +0800, Qiang Yu wrote:
>> > > > Kernel DRM driver f
Nicolas Saenz Julienne writes:
> This patch exposes backlight control into userspace by creating a
> backlight device instead of directly accessing the PWM registers.
>
> The backlight driver can't go on a separate file as it shares the I2C
> bus & address with the panel.
I remember some concern
Alex Deucher writes:
> On Fri, Dec 21, 2018 at 9:16 AM Liviu Dudau wrote:
>>
>> On Thu, Dec 20, 2018 at 04:36:19PM +0100, Daniel Vetter wrote:
>> > On Thu, Dec 20, 2018 at 09:56:57AM -0500, Alex Deucher wrote:
>> > > I'm not familiar enough with ARM to know if write combining
>> > > is actually
Paul Kocialkowski writes:
> The KMS mode_config elements are currently configured in vc4_kms_load,
> that is called after all components are binded (component_bind_all).
> However, the CRTC component (for the Pixel Valve) needs to access the
> allow_fb_modifiers element at bind time, when initial
Brian Starkey writes:
> Hi Matt,
>
> On Thu, Nov 15, 2018 at 02:13:45PM -0800, Matt Roper wrote:
>>Some display controllers can be programmed to present non-black colors
>>for pixels not covered by any plane (or pixels covered by the
>>transparent regions of higher planes). Compositors that want
Daniel Vetter writes:
> On Tue, Jan 15, 2019 at 03:04:18PM +, James Clarke wrote:
>> Like GNU/Linux, GNU/kFreeBSD's sys/types.h does not define the uintX_t
>> types, which differs from the BSDs' headers. Thus we should include
>> stdint.h to ensure we have all the required integer types.
>>
all the concerns raised in the RFC discussions,
> and assuming there's enough Acks and no new issues that pop up, we can
> go ahead with this.
>
> 1: https://patchwork.kernel.org/patch/10648851/
> Cc: Petri Latvala
> Cc: Arkadiusz Hiler
> Cc: Liviu Dudau
> Cc: Sean Pau
Tomi Valkeinen writes:
> The DRM device minor numbers are allocated according to the registration
> order. This causes confusion in cases where the registration order can
> change, or when, say, a modesetting capable device is preferred to be
> card0, and a rendering device is preferred to be car
Kuo-Hsin Yang writes:
> The gem drivers use shmemfs to allocate backing storage for gem objects.
> On Samsung Chromebook Plus, the drm/rockchip driver may call
> rockchip_gem_get_pages -> drm_gem_get_pages -> shmem_read_mapping_page
> to pin a lot of pages, breaking the page reclaim mechanism and
YueHaibing writes:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/vc4/vc4_txp.c: In function 'vc4_txp_connector_atomic_check':
> drivers/gpu/drm/vc4/vc4_txp.c:252:29: warning:
> variable 'gem' set but not used [-Wunused-but-set-variable]
> struct drm_gem_cma_object *gem;
for avoiding underrun reports when reconfiguring the
> pipeline. It is now based on detection instead of delaying the underrun
> interrupt unmasking.
>
> It can be tested with a dedicated IGT GPU Tools series:
> VC4 load tracker testing
Series is:
Reviewed-by: Eric Anholt
Thanks for
The debugfs_regset32 is nice to use for reducing boilerplate in
dumping a bunch of regs in debugfs, but we also want to be able to
print to dmesg them at runtime for driver debugging. drm_printer lets
us format debugfs and the printk the same way.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm
One might want to use the VC4 display stack without using Mesa.
Similar to the debugfs fixes for not having all of the possible
display bits enabled, make sure you can't oops in vc4 if v3d isn't
enabled.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_drv.c | 11 ++
Now I can extend the stats without more copy and pasting between the
two.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_bo.c | 48 +++-
1 file changed, 14 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4
4_debugfs.c out of the business of knowing the whole list of
components.
Thanks to this change, dsi0 (if it existed) would register its node.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_bo.c | 6 +--
drivers/gpu/drm/vc4/vc4_crtc.c| 33 +++-
drivers/gpu/drm/vc4/vc4
Otherwise, you sometimes decode the ident fields based on 0xdeadbeef
register reads.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_v3d.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm
This makes sure the vc4_reset doesn't hit an obscure race with the
GET_PARAM ioctl, fixes a decrement outside of the lock, and prevents
future code from making mistakes with the weird return value of
pm_runtime_get_sync().
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_drv.c
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