On Tue, Aug 20, 2024 at 11:15 AM Konrad Dybcio wrote:
>
> On 15.08.2024 8:26 PM, Antonino Maniscalco wrote:
> > The bv_fence field of rbmemptrs was being used incorrectly as the BV
> > rptr shadow pointer in some places.
> >
> > Add a bv_rptr field and change the code to use that instead.
> >
> >
On Mon, Aug 19, 2024 at 9:31 PM Akhil P Oommen wrote:
>
> On Thu, Aug 15, 2024 at 08:26:16PM +0200, Antonino Maniscalco wrote:
> > Some userspace changes are necessary so add a flag for userspace to
> > advertise support for preemption.
>
> So the intention is to fallback to level 0 preemption unt
On Mon, Aug 19, 2024 at 9:09 PM Akhil P Oommen wrote:
>
> On Thu, Aug 15, 2024 at 08:26:14PM +0200, Antonino Maniscalco wrote:
> > This patch implements preemption feature for A6xx targets, this allows
> > the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> > hardware as such
On Thu, Aug 22, 2024 at 9:06 PM Akhil P Oommen wrote:
>
> On Wed, Aug 21, 2024 at 05:02:56PM +0100, Connor Abbott wrote:
> > On Mon, Aug 19, 2024 at 9:09 PM Akhil P Oommen
> > wrote:
> > >
> > > On Thu, Aug 15, 2024 at 08:26:14PM +0200, Antonino Maniscalco
On Fri, Aug 23, 2024 at 10:21 AM Connor Abbott wrote:
>
> On Thu, Aug 22, 2024 at 9:06 PM Akhil P Oommen
> wrote:
> >
> > On Wed, Aug 21, 2024 at 05:02:56PM +0100, Connor Abbott wrote:
> > > On Mon, Aug 19, 2024 at 9:09 PM Akhil P Oommen
> > > wrote:
>
On Fri, Aug 23, 2024 at 9:30 AM wrote:
>
> On 15/08/2024 20:26, Antonino Maniscalco wrote:
> > This series implements preemption for A7XX targets, which allows the GPU to
> > switch to an higher priority ring when work is pushed to it, reducing
> > latency
> > for high priority submissions.
> >
>
On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
>
> On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> wrote:
> >
> > This patch implements preemption feature for A6xx targets, this allows
> > the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> > hardware as such support
On Fri, Aug 30, 2024 at 8:00 PM Rob Clark wrote:
>
> On Fri, Aug 30, 2024 at 11:54 AM Connor Abbott wrote:
> >
> > On Fri, Aug 30, 2024 at 7:08 PM Rob Clark wrote:
> > >
> > > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
> > > wrote:
>
erent SoCs out there with different UBWC
configurations and I cannot test them all.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578
Signed-off-by: Connor Abbott
---
Connor Abbott (3):
drm/msm: Update a6xx register XML
drm/msm: Expand UBWC config setting
drm/msm: Expose
ry on a663.
ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on
the display side. Similarly macrotile_mode should match the display
side.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4
drivers/gpu/drm/msm/adreno/a6xx_gp
Update to Mesa commit 81fd13913a97 ("freedreno: Fix RBBM_NC_MODE_CNTL
variants").
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1617 -
1 file changed, 1603 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm
This adds extra parameters that affect UBWC tiling that will be used by
the Mesa implementation of VK_EXT_host_image_copy.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++
include/uapi/drm/msm_drm.h | 2 ++
2 files changed, 8 insertions(+)
diff
On Tue, Jul 2, 2024 at 3:31 PM Rob Clark wrote:
>
> On Tue, Jul 2, 2024 at 5:56 AM Connor Abbott wrote:
> >
> > According to downstream we should be setting RBBM_NC_MODE_CNTL to a
> > non-default value on a663 and a680, we don't support a663 and on a680
>
erent SoCs out there with different UBWC
configurations and I cannot test them all.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578
Signed-off-by: Connor Abbott
---
Changes in v2:
- Move ubwc_config field descriptions to kerneldoc comments on the struct
- Link to v1:
https://lore.kern
Update to Mesa commit 81fd13913a97 ("freedreno: Fix RBBM_NC_MODE_CNTL
variants").
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1617 -
1 file changed, 1603 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm
This adds extra parameters that affect UBWC tiling that will be used by
the Mesa implementation of VK_EXT_host_image_copy.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++
include/uapi/drm/msm_drm.h | 2 ++
2 files changed, 8 insertions(+)
diff
ry on a663.
ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on
the display side. Similarly macrotile_mode should match the display
side.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4
drivers/gpu/drm/msm/adreno/a6xx_gp
On Thu, Jul 11, 2024 at 11:10 AM Vladimir Lypak
wrote:
>
> There are several issues with preemption on Adreno A5XX GPUs which
> render system unusable if more than one priority level is used. Those
> issues include persistent GPU faults and hangs, full UI lockups with
> idling GPU.
>
> ---
> Vladi
On Wed, Jul 17, 2024 at 5:33 PM Vladimir Lypak wrote:
>
> On Wed, Jul 17, 2024 at 10:40:26AM +0100, Connor Abbott wrote:
> > On Thu, Jul 11, 2024 at 11:10 AM Vladimir Lypak
> > wrote:
> > >
> > > There are several issues with preemption on Adreno A5XX GPUs w
On Thu, Jul 11, 2024 at 11:10 AM Vladimir Lypak
wrote:
>
> On A5XX GPUs when preemption is used it's invietable to enter a soft
> lock-up state in which GPU is stuck at empty ring-buffer doing nothing.
> This appears as full UI lockup and not detected as GPU hang (because
> it's not). This happens
On Thu, Aug 1, 2024 at 1:25 PM Vladimir Lypak wrote:
>
> On Mon, Jul 29, 2024 at 06:26:45PM +0100, Connor Abbott wrote:
> > On Thu, Jul 11, 2024 at 11:10 AM Vladimir Lypak
> > wrote:
> > >
> > > On A5XX GPUs when preemption is used it's invietable to ente
On Thu, Aug 1, 2024 at 3:26 PM Vladimir Lypak wrote:
>
> On Thu, Aug 01, 2024 at 01:52:32PM +0100, Connor Abbott wrote:
> > On Thu, Aug 1, 2024 at 1:25 PM Vladimir Lypak
> > wrote:
> > >
> > > On Mon, Jul 29, 2024 at 06:26:45PM +0100, Connor Abbott wrote
erent SoCs out there with different UBWC
configurations and I cannot test them all.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578
Signed-off-by: Connor Abbott
---
Changes in v3:
- Further update register XML.
- Add commit to fix macrotile_mode on a680.
- Link to v2:
https://lore.kern
This adds extra parameters that affect UBWC tiling that will be used by
the Mesa implementation of VK_EXT_host_image_copy.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++
include/uapi/drm/msm_drm.h | 2 ++
2 files changed, 8 insertions(+)
diff
Make it match the MDSS settings for sc8180x and downstream.
Note that without the previous commit that exposes the value of
macrotile_mode to mesa, this will break mesa which expects the legacy
default value of 0. Therefore we do *not* want to backport it.
Signed-off-by: Connor Abbott
ry on a663.
ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on
the display side. Similarly macrotile_mode should match the display
side.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4
drivers/gpu/drm/msm/adreno/a6xx_gp
Update to Mesa commit 36a13d2b3b0 ("freedreno: fix a7xx perfcntr
countables").
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1118 -
1 file changed, 1097 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/regist
check. Thus it ends up rewriting hardware registers with the default
> (incorrect) values. Add the !a618 check to this function.
>
> Reported-by: Leonard Lausen
> Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49
> Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC config se
check.
>
> Rather than adding the check to a6xx_set_ubwc_config(), fill in the
> UBWC config for a618 (based on readings from SC7180).
>
> Reported-by: Leonard Lausen
> Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49
> Fixes: 8814455a0e54 ("drm/msm: Refactor UBWC con
On Fri, Feb 23, 2024 at 9:28 PM Konrad Dybcio wrote:
>
> The A702 is a weird mix of 600 and 700 series.. Perhaps even a
> testing ground for some A7xx features with good ol' A6xx silicon.
> It's basically A610 that's been beefed up with some new registers
> and hw features (like APRIV!), that was
On Tue, Mar 26, 2024 at 7:47 PM Dmitry Baryshkov
wrote:
>
> On Tue, 26 Mar 2024 at 21:32, Abhinav Kumar wrote:
> >
> >
> >
> > On 3/26/2024 12:10 PM, Dmitry Baryshkov wrote:
> > > On Tue, 26 Mar 2024 at 20:31, Abhinav Kumar
> > > wrote:
> > >>
> > >>
> > >>
> > >> On 3/26/2024 11:19 AM, Dmitry
Remove the scm call since it's not done downstream either and
> works fine without.
>
> Fixes: 14b27d5df3ea ("drm/msm/a7xx: Initialize a750 "software fuse"")
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Connor Abbott
On Mon, Apr 1, 2024 at 3:52 AM Dmitry Baryshkov
wrote:
>
> Import Adreno registers database for A6xx from the Mesa, commit
> 639488f924d9 ("freedreno/registers: limit the rules schema").
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4970
> +
On Fri, Sep 6, 2024 at 9:03 PM Akhil P Oommen wrote:
>
> On Thu, Sep 05, 2024 at 04:51:22PM +0200, Antonino Maniscalco wrote:
> > This patch implements preemption feature for A6xx targets, this allows
> > the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> > hardware as such
On Mon, Sep 9, 2024 at 2:15 PM Antonino Maniscalco
wrote:
>
> On 9/6/24 9:54 PM, Akhil P Oommen wrote:
> > On Thu, Sep 05, 2024 at 04:51:22PM +0200, Antonino Maniscalco wrote:
> >> This patch implements preemption feature for A6xx targets, this allows
> >> the GPU to switch to a higher priority ri
On Tue, Sep 17, 2024 at 9:39 PM Akhil P Oommen wrote:
>
> From: Puranam V G Tejaswi
>
> Add support for Adreno 663 found on sa8775p based platforms.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++
In the future, the right thing to do is open a mesa MR with just the
register changes and then copy the file from mesa once it's merged,
because all of the XML files are supposed to flow from mesa to keep
mesa and the kernel in sync. I've opened a mesa MR [1] based on this
that will hopefully get q
On Fri, Sep 13, 2024 at 8:51 PM Rob Clark wrote:
>
> From: Rob Clark
>
> The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> devices (x1-85, possibly others), it seems to pass that barrier while
> there are still things in the event completion FIFO waiting to be
> written back to
On Tue, Sep 17, 2024 at 12:14 PM Antonino Maniscalco
wrote:
>
> Add documentation about the preemption feature supported by the msm
> driver.
>
> Signed-off-by: Antonino Maniscalco
> ---
> Documentation/gpu/msm-preemption.rst | 98
>
> 1 file changed, 98 ins
On Mon, Dec 9, 2024 at 3:20 AM Akhil P Oommen wrote:
>
> When kernel is booted in EL2, SECVID registers are accessible to the
> KMD. So we can use that to switch GPU's secure mode to avoid dependency
> on Zap firmware. Also, we can't load a secure firmware without a
> hypervisor that supports it.
On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
wrote:
>
> On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
> > On 12/13/24 5:50 PM, Akhil P Oommen wrote:
> >> On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> >>> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
> On 12/5/2024 10:24 PM, Rob Cla
On Wed, Mar 19, 2025 at 10:55 AM Rob Clark wrote:
>
> From: Rob Clark
>
> If userspace has opted-in to VM_BIND, then GPU faults and VM_BIND errors
> will mark the VM as unusable.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gem.h| 17 +
> drivers/gpu/drm/
On Wed, Apr 9, 2025 at 11:40 AM Konrad Dybcio
wrote:
>
> On 4/9/25 5:30 PM, Connor Abbott wrote:
> > On Wed, Apr 9, 2025 at 11:22 AM Konrad Dybcio
> > wrote:
> >>
> >> On 4/9/25 5:12 PM, Connor Abbott wrote:
> >>> On Wed, Apr 9, 2025 at 10:48 AM
On Wed, Apr 9, 2025 at 10:48 AM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> The Highest Bank address Bit value can change based on memory type used.
>
> Attempt to retrieve it dynamically, and fall back to a reasonable
> default (the one used prior to this change) on error.
>
> Signed-off-by
On Wed, Apr 9, 2025 at 11:22 AM Konrad Dybcio
wrote:
>
> On 4/9/25 5:12 PM, Connor Abbott wrote:
> > On Wed, Apr 9, 2025 at 10:48 AM Konrad Dybcio
> > wrote:
> >>
> >> From: Konrad Dybcio
> >>
> >> The Highest Bank address Bit value can
On Thu, Apr 17, 2025 at 3:45 AM Akhil P Oommen wrote:
>
> On 4/10/2025 11:13 PM, Konrad Dybcio wrote:
> > From: Konrad Dybcio
> >
> > The Highest Bank address Bit value can change based on memory type used.
> >
> > Attempt to retrieve it dynamically, and fall back to a reasonable
> > default (the
On Thu, Apr 17, 2025, 1:50 PM Akhil P Oommen wrote:
>
> On 4/17/2025 9:02 PM, Connor Abbott wrote:
> > On Thu, Apr 17, 2025 at 3:45 AM Akhil P Oommen
> > wrote:
> >>
> >> On 4/10/2025 11:13 PM, Konrad Dybcio wrote:
> >>> From: Konrad Dybcio
&g
On Fri, May 9, 2025 at 8:45 AM Konrad Dybcio
wrote:
>
> On 5/8/25 8:33 PM, Connor Abbott wrote:
> > On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio wrote:
> >>
> >> From: Konrad Dybcio
> >>
> >> SC8180X (A680) and SA8775P (A663) require a write to th
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> The value the UBWC hardware expects is 13 less than the actual value.
> To make it easier to migrate to a common UBWC configuration table,
> defer that logic to the data source (which is currently a number of
> if-els
On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> This bit is set iff the UBWC version is 1.0. That notably does not
> include QCM2290's "no UBWC".
While this is technically true, AFAIK the only difference between UBWC
1.0 and 2.0 is that newer UBWC disables level 1
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
> as a separate field.
For these sorts of things, it's probably best to add a helper to the
common ubwc config header. Other blocks also have bi
On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> On A663 (SA8775P) the value matches exactly.
>
> On A610, the value matches on SM6115, but is different on SM6125. That
> turns out not to be a problem, as the bits that differ aren't even
> interpreted.
This is defi
On Fri, May 9, 2025 at 9:37 AM Konrad Dybcio
wrote:
>
> On 5/9/25 3:17 PM, Konrad Dybcio wrote:
> > On 5/8/25 9:26 PM, Connor Abbott wrote:
> >> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio
> >> wrote:
> >>>
> >>> From: Konrad Dybcio
&
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> Add a file that will serve as a single source of truth for UBWC
> configuration data for various multimedia blocks.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/soc/qcom/Kconfig | 8 ++
> drivers/soc/qco
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> Instead of setting it on a gpu-per-gpu basis, converge it to the
> intended "is A650 family or A7xx".
Can we also set this based on the UBWC version?
Connor
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/dr
On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio wrote:
>
> From: Konrad Dybcio
>
> SC8180X (A680) and SA8775P (A663) require a write to that register,
> while other SKUs are fine with the default value. Don't overwrite it
> needlessly, requiring the developer to read the value back from
> hardware j
On Thu, May 15, 2025 at 12:15 PM Rob Clark wrote:
>
> On Thu, May 15, 2025 at 2:28 AM Philipp Stanner wrote:
> >
> > Hello,
> >
> > On Wed, 2025-05-14 at 09:59 -0700, Rob Clark wrote:
> > > From: Rob Clark
> > >
> > > Similar to the existing credit limit mechanism, but applying to jobs
> > > enq
> wrote:
> > > > > > >
> > > > > > > (Cc: Boris)
> > > > > > >
> > > > > > > On Thu, May 15, 2025 at 12:22:18PM -0400, Connor Abbott wrote:
> > > > > > > > For some context, other drivers
userspace submission in one context could cause another context to
function incorrectly and hang, effectively a denial of service (although
without leaking data). This was missed during initial a7xx bringup.
Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support")
Signed-off-by: Connor Abbo
Based on kgsl.
Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support")
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_
he initial a7xx support landed before the register XML modified in
patch 1 was introduced, but the XML seems to have landed in the same
cycle so we shouldn't need a separate backport of the generated C
headers.
Signed-off-by: Connor Abbott
---
Connor Abbott (2):
drm/msm: Fix CP_RESE
On Mon, May 19, 2025 at 5:51 PM Rob Clark wrote:
>
> On Mon, May 19, 2025 at 2:45 PM Dave Airlie wrote:
> >
> > On Tue, 20 May 2025 at 07:25, Rob Clark wrote:
> > >
> > > On Mon, May 19, 2025 at 2:15 PM Dave Airlie wrote:
> > > >
> > > > On Tue, 20 May 2025 at 03:54, Rob Clark wrote:
> > > > >
On Thu, May 22, 2025 at 11:46 AM Konrad Dybcio
wrote:
>
> On 5/21/25 12:28 AM, Connor Abbott wrote:
> > Calling this packet is necessary when we switch contexts because there
> > are various pieces of state used by userspace to synchronize between BR
> > and BV that are p
On Mon, Jul 28, 2025 at 4:43 PM Rob Clark wrote:
>
> This is needed to properly interpret some of the sections.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
On Tue, Jul 29, 2025 at 9:40 AM Rob Clark wrote:
>
> On Mon, Jul 28, 2025 at 3:15 PM Rob Clark wrote:
> >
> > On Mon, Jul 28, 2025 at 2:04 PM Connor Abbott wrote:
> > >
> > > On Mon, Jul 28, 2025 at 4:43 PM Rob Clark
> > > wrote:
> > >
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