NC)
> + val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
> +
> + regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
> + } else {
> + val = SUN4I_TCON1_IO_POL_UNKNOWN;
I think a comment for the origin of this is warranted.
Othe
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
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Fix that by removing set_rate quirk and always set clock rate.
>
> Fixes: 40bb9d3147b2 ("drm/sun4i: Add support for H6 DW HDMI controller")
> Tested-by: Andre Heider
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
_
On Fri, Feb 5, 2021 at 2:48 AM Jernej Skrabec wrote:
>
> cpce value for 594 MHz is set differently in BSP driver. Fix that.
>
> Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY")
> Tested-by: Andre Heider
> Signed-off-by: Jernej Skrabec
pronounced with higher frequencies.
>
> Fix that by allowing max. supported frequency in HW and fix the comment.
>
> Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6")
> Tested-by: Andre Heider
> Signed-off-by:
On Sat, Feb 6, 2021 at 12:21 AM Jernej Škrabec wrote:
>
> Dne petek, 05. februar 2021 ob 17:01:30 CET je Maxime Ripard napisal(a):
> > On Fri, Feb 05, 2021 at 11:21:22AM +0800, Chen-Yu Tsai wrote:
> > > On Fri, Feb 5, 2021 at 2:48 AM Jernej Skrabec
> wrote:
> > >
his
> change.
>
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +-
Acked-by: Chen-Yu Tsai
ve the MBUS quirks
> media: cedrus: Remove the MBUS quirks
> media: sun8i-di: Remove the call to of_dma_configure
Whole series looks good to me.
Reviewed-by: Chen-Yu Tsai
Now the question remaining is how do we merge this series so that
the notifier gets merged before all the code dea
From: Chen-Yu Tsai
The SSD130x's command to toggle COM scan direction uses bit 3 and only
bit 3 to set the direction of the scanout. The driver has an incorrect
GENMASK(3, 2), causing the setting to be set on bit 2, rendering it
ineffective.
Fix the mask to only bit 3, so that the requ
From: Chen-Yu Tsai
Currently the ssd130x driver only sets the segment remap setting when
the device tree requests it; it however does not clear the setting if
it is not requested. This leads to the setting incorrectly persisting
if the hardware is always on and has no reset GPIO wired. This
g whether how many bytes.
>
> Signed-off-by: Jitao Shi
> Signed-off-by: Guillaume Ranquet
Reviewed-by: Chen-Yu Tsai
On Tue, Mar 22, 2022 at 4:52 PM Xin Ji wrote:
>
> On Tue, Mar 22, 2022 at 04:43:20PM +0800, Hsin-Yi Wang wrote:
> > On Tue, Mar 22, 2022 at 4:02 PM Xin Ji wrote:
> > >
> > > As downstream sink was set into standby mode while bridge disabled,
> > > this patch used for setting downstream sink into
From: Chen-Yu Tsai
On the SINO WEALTH SH1106, which is mostly compatible with the SSD1306,
only the basic page addressing mode is supported. This addressing mode
is not as easy to use compared to the currently supported horizontal
addressing mode, as the page address has to be set prior to
From: Chen-Yu Tsai
The SINO WEALTH SH1106 is an OLED display driver that is somewhat
compatible with the SSD1306. It supports a slightly wider display,
at 132 instead of 128 pixels. The basic commands are the same, but
the SH1106 doesn't support the horizontal or vertical address modes.
From: Chen-Yu Tsai
The SINO WEALTH SH1106 is an OLED display driver that is somewhat
compatible with the SSD1306. It supports a slightly wider display,
at 132 instead of 128 pixels. The basic commands are the same, but
the SH1106 doesn't support the horizontal or vertical address modes.
From: Chen-Yu Tsai
Add a vendor prefix entry for SINO WEALTH Eletronics Ltd.
(http://www.sinowealth.com).
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor
From: Chen-Yu Tsai
Hi everyone,
This series adds support for SH1106 to the ssd130x OLED display
driver.
The SINO WEALTH SH1106 is an OLED display driver that is somewhat
compatible with the SSD1306. It supports a slightly wider display,
at 132 instead of 128 pixels. The basic commands are the
Hi,
(CC-ed DRM bridge maintainers and the dri-devel ML)
On Wed, Feb 2, 2022 at 1:47 AM Nícolas F. R. A. Prado
wrote:
>
> mt8183-kukui-jacuzzi has an anx7625 bridge connected to the output of
> its DSI host. However, after commit fd0310b6fe7d ("drm/bridge: anx7625:
> add MIPI DPI input feature"),
.
Fixes: 01365f549c88 ("drm/mediatek: Add support for Mediatek SoC MT8192")
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b1
On Sun, Mar 06, 2022 at 07:13:30PM +0200, Laurent Pinchart wrote:
> Hello Xin,
>
> (Question for Rob below, and I'm afraid this is urgent as we need to
> merge a fix in v5.17).
>
> On Fri, Nov 05, 2021 at 11:19:03AM +0800, Xin Ji wrote:
> > The basic anx7625 driver only support MIPI DSI rx signal
On Tue, Mar 8, 2022 at 12:20 AM Robert Foss wrote:
>
> Signed-off-by: Robert Foss
Reviewed-by: Chen-Yu Tsai
I think we need to send this directly to the soc maintainers to get it
picked up before the final 5.17 release?
>
> On Mon, 7 Mar 2022 at 16:46, Robert Foss wrote:
the issue by enclosing macro arguments in parenthesis.
>
> Cc: sta...@vger.kernel.org # 5.12+
> Fixes: 883029390550 ("drm/sun4i: Add DE2 CSC library")
> Reported-by: Roman Stratiienko
> Signed-off-by: Jernej Skrabec
Otherwise,
Reviewed-by: Chen-Yu Tsai
On Mon, Aug 2, 2021 at 3:47 PM Yongqiang Niu wrote:
>
> Change since v5:
> -rebase on linux 5.14-rc1
>
> Yongqiang Niu (3):
> dt-binding: gce: add gce header file for mt8192
> arm64: dts: mt8192: add gce node
> mailbox: cmdq: add mt8192 support
Looks like all the driver parts are in -next,
On Fri, Sep 3, 2021 at 12:31 AM Ezequiel Garcia
wrote:
>
> On Wed, 1 Sept 2021 at 05:32, Yunfei Dong wrote:
> >
> > This series adds support for multi hardware decode into mtk-vcodec, by first
> > adding component framework to manage each hardware information: interrupt,
> > clock, register bases
Hi,
On Sat, Sep 25, 2021 at 7:24 AM Brian Norris wrote:
>
> In commit 59eb7193bef2, we moved most HW configuration to bind(), but we
> didn't move the runtime PM management. Therefore, depending on initial
> boot state, runtime-PM workqueue delays, and other timing factors, we
> may disable our p
dge
> driver")
> Signed-off-by: Brian Norris
Reviewed-by: Chen-Yu Tsai
On Tue, Sep 28, 2021 at 2:00 AM Brian Norris wrote:
>
> Fix some error handling here noticed in review of other changes.
>
> Reported-by: Chen-Yu Tsai
> Signed-off-by: Brian Norris
Fixes: 2d4f7bdafd70 ("drm/rockchip: dsi: migrate to use dw-mipi-dsi
bridge driver")
si: move all lane config except LCDC mux
> to bind()")
> Link:
> https://lore.kernel.org/linux-rockchip/9aedfb528600ecf871885f7293ca4207c84d16c1.ca...@gmail.com/
> Reported-by:
> Cc:
> Signed-off-by: Brian Norris
> Tested-by: Nícolas F. R. A. Prado
Reviewed-by: Chen-Yu Tsai
se as far as I can tell.
>
> Fixes: 43c2de1002d2 ("drm/rockchip: dsi: move all lane config except LCDC mux
> to bind()")
> Cc:
> Signed-off-by: Brian Norris
Reviewed-by: Chen-Yu Tsai
7768 ("ASoC: rockchip: cdn-dp sound output use spdif")
> Signed-off-by: Brian Norris
Reviewed-by: Chen-Yu Tsai
On Sat, Jan 15, 2022 at 7:03 AM Brian Norris wrote:
>
> Some audio servers like to monitor a jack device (perhaps combined with
> EDID, for audio-presence info) to determine DP/HDMI audio presence.
>
> Signed-off-by: Brian Norris
Reviewed-by: Chen-Yu Tsai
odecs are likely
returning the wrong DAI.
For this particular patch it works either way, so
Reviewed-by: Chen-Yu Tsai
> + struct snd_soc_card *card = rtd->card;
> + int ret;
> +
> + /* Enable jack detection. */
> + ret = snd_soc_card_jack_new(card, &qu
On Wed, Jan 19, 2022 at 4:18 AM Brian Norris wrote:
>
> Hi Chen-Yu,
>
> On Mon, Jan 17, 2022 at 05:01:52PM +0800, Chen-Yu Tsai wrote:
> > On Sat, Jan 15, 2022 at 7:03 AM Brian Norris
> > wrote:
> > >
> > > Now that the cdn-dp driver supports plu
Hi,
On Thu, Jan 27, 2022 at 10:56 AM Yunfei Dong wrote:
>
> Init some of VP9 frame decode params to default value.
>
> Signed-off-by: Yunfei Dong
Maybe add
Fixes: b88dbe38dca8 ("media: uapi: Add VP9 stateless decoder controls")
> ---
> drivers/media/v4l2-core/v4l2-ctrls-core.c | 8
>
On Thu, Nov 11, 2021 at 11:49 AM yunfei.d...@mediatek.com
wrote:
>
> Hi Tzung-Bi,
>
> Thanks for your suggestion.
> On Wed, 2021-11-10 at 18:30 +0800, Tzung-Bi Shih wrote:
> > On Tue, Nov 09, 2021 at 08:50:17PM +0800, Yunfei Dong wrote:
> > > Manage each hardware information which includes irq/pow
On Mon, Dec 21, 2020 at 4:03 AM Laurent Pinchart
wrote:
>
> Replace the reference to the DWC HDMI text DT binding with a reference
> to the YAML equivalent.
>
> Signed-off-by: Laurent Pinchart
> Acked-by: Rob Herring
Acked-by: Chen-Yu Tsai
_
On Thu, Jan 6, 2022 at 4:48 PM Chunfeng Yun wrote:
>
> On Mon, 2022-01-03 at 15:53 +0100, AngeloGioacchino Del Regno wrote:
> > All the headers for phy-mtk-mipi-{dsi,dsi-mt8173,dsi-mt8183}.c were
> > included from phy-mtk-mipi-dsi.h, but this isn't optimal: in order to
> > increase readability and
pipeline would allow the decoded video frames to be output
directly.
Add support for this to support the various formats that have U/V
swapped.
Signed-off-by: Chen-Yu Tsai
---
This was tested on an ROC-RK3399-PC with modetest only. Changes to all
other SoC platforms were based on their respective TRMs
On Mon, May 13, 2019 at 2:28 AM Jagan Teki wrote:
>
> On Sun, May 12, 2019 at 11:16 PM wrote:
> >
> > From: Clément Péron
> >
> > Enable and add supply to the Mali GPU node on the
> > Pine H64 board.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6-pine-
the A64 are connected properly,
> but AFAIK currently unsupported by the driver.
>
> Signed-off-by: Harald Geyer
> Signed-off-by: Torsten Duwe
Looks good to me.
Reviewed-by: Chen-Yu Tsai
___
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On Thu, May 23, 2019 at 2:54 PM Torsten Duwe wrote:
>
> From: Icenowy Zheng
>
> Some code can be shared within different DP bridges by Analogix.
>
> Extract them to a new module.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Vasily Khoruzhick
> Signed-off-by: Torsten Duwe
> ---
> drivers/
On Mon, Apr 8, 2019 at 3:23 PM Maxime Ripard wrote:
>
> On Sat, Apr 06, 2019 at 01:45:04AM +0200, meg...@megous.com wrote:
> > From: Ondrej Jirman
> >
> > Orange Pi 3 board requires enabling DDC I2C bus via some GPIO connected
> > transistors, before it can be used. Model this as a power supply f
On Mon, Apr 8, 2019 at 4:11 PM Maxime Ripard wrote:
>
> On Sat, Apr 06, 2019 at 01:06:07AM -0500, Rob Herring wrote:
> > On Mon, Apr 01, 2019 at 10:56:40AM +0200, Maxime Ripard wrote:
> > > Hi,
> > >
> > > We've had for quite some time to hack around in our drivers to take into
> > > account the f
On Mon, Apr 8, 2019 at 4:21 PM Maxime Ripard wrote:
>
> On Mon, Apr 08, 2019 at 04:14:53PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Apr 8, 2019 at 4:11 PM Maxime Ripard
> > wrote:
> > >
> > > On Sat, Apr 06, 2019 at 01:06:07AM -0500, Rob Herring wrote:
> &
On Thu, Apr 11, 2019 at 6:19 PM megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> This series implements support for Xunlong Orange Pi 3 board.
>
> Unfortunately, this board needs some small driver patches, so I have
> split the boards DT patch into chunks that require patches for drivers
On Thu, Apr 18, 2019 at 6:27 AM Paul Kocialkowski
wrote:
>
> For our component-backed driver to be properly removed, we need to
> delete the component master in sun4i_drv_remove and make sure to call
> component_unbind_all in the master's unbind so that all components are
> unbound when the master
of_reserved_mem_device_release(dev);
You should probably mention this change in the commit log as well.
Otherwise,
Reviewed-by: Chen-Yu Tsai
> +
> + drm_dev_put(drm);
> }
>
> static const struct component_master_ops sun4i_drv_master_ops = {
> --
> 2.21.0
On Tue, Apr 23, 2019 at 10:06 AM Paul Kocialkowski
wrote:
>
> Hi,
>
> Le vendredi 19 avril 2019 à 19:10 +0200, Paul Kocialkowski a écrit :
> > Hi,
> >
> > On Fri, 2019-04-19 at 09:02 -0700, Chen-Yu Tsai wrote:
> > > On Fri, Apr 19, 2019 at 1:03 AM Paul
On Tue, Jan 22, 2019 at 1:18 AM Jernej Škrabec wrote:
>
> Dne ponedeljek, 21. januar 2019 ob 16:07:28 CET je Priit Laes napisal(a):
> > On Mon, Jan 21, 2019 at 02:25:17PM +0100, Maxime Ripard wrote:
> > > On Fri, Jan 18, 2019 at 02:51:26PM +, Priit Laes wrote:
> > > > On Fri, Jan 18, 2019 at 0
The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.
Add the 2 LDO enable bits to the gate bits.
Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai
---
drivers/cl
nents.
As the MIPI DSI output device is not officially documented, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +
1 file changed, 5 insertions(+)
diff --
this patch.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index d00055e9eef5..a5e884a8b2ae 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
s the MIPI DSI output device is not officially documented, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 4
drivers/gpu/drm/sun4i/sun4i_drv.c | 2 ++
drivers/gpu/drm/
We might want to use the backend pointer from DRM callbacks that get
called within drm_universal_plane_init(), such as the
.format_mod_supported callback.
Move the assignment of the layer's backend pointer to right after the
structure is allocated.
Signed-off-by: Chen-Yu Tsai
---
driver
e BGRX from list of supported formats by the backend.
Fixes: 3d4265f89d06 ("drm/sun4i: backend: Add a helper and a list for supported
formats")
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/s
display pipeline.
The actual model or compatible string for the panel should be added in
the tablet device tree file.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-q8-common.dtsi | 37 ++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-q8
e close to what was provided in the vendor fex files.
Since there are also A33 Q8 tablets with 1024x600 panels, this patch
only sets the compatible string for A23 Q8 tablets.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 4
1 file changed, 4 insertions(+)
diff --
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 147
arch/arm/boot/dts/sun8i-a33.dtsi | 194 ++-
2 files changed, 185 insertions(+), 156 deletions
as easily be applied for -next
and then backported.
Also, the fixes tags are no longer line wrapped, unlike patches I've
sent in the past.
Regards
ChenYu
Chen-Yu Tsai (11):
clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it
dt-bindings: display: sun4i-drm: Add compatible
tiled modifier support and helper")
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_layer.c | 34 ++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c
b/drivers/gpu/drm/sun4i/sun4i_layer.c
index 95d4aa
or A23/A33")
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index a9c123de5d2c..97ec8b8cec09 10
d_get_value_cansleep().
Fixes: 0c9501f823a4 ("backlight: pwm_bl: Handle gpio that can sleep")
Signed-off-by: Chen-Yu Tsai
---
drivers/video/backlight/pwm_bl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlig
On Wed, Jan 23, 2019 at 11:54 PM Maxime Ripard
wrote:
>
> The current calculation for the video start delay in the current DSI driver
> is that it is the total vertical size, minus the backporch and sync length,
> plus 1.
>
> However, the Allwinner code has it as the active vertical size, plus the
On Wed, Jan 30, 2019 at 11:23 AM Chen-Yu Tsai wrote:
>
> On Wed, Jan 23, 2019 at 11:54 PM Maxime Ripard
> wrote:
> >
> > The current calculation for the video start delay in the current DSI driver
> > is that it is the total vertical size, minus the backporch
On Wed, Jan 23, 2019 at 11:54 PM Maxime Ripard
wrote:
>
> From: Konstantin Sudakov
>
> The current driver doesn't support the DSI burst operation mode.
>
> Let's add the needed quirks to make it work.
>
> Signed-off-by: Konstantin Sudakov
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/
On Wed, Feb 6, 2019 at 10:12 PM Maxime Ripard wrote:
>
> Hi Chen-Yu,
>
> On Wed, Feb 06, 2019 at 12:48:21AM +0800, Chen-Yu Tsai wrote:
> > On Wed, Jan 30, 2019 at 11:23 AM Chen-Yu Tsai wrote:
> > >
> > > On Wed, Jan 23, 2019 at 11:54 PM Maxime Ripard
>
On Thu, Mar 7, 2019 at 11:48 PM Maxime Ripard wrote:
>
> On Thu, Mar 07, 2019 at 05:15:20PM +0200, Georgi Djakov wrote:
> > Hi,
> >
> > On 3/5/19 18:14, Robin Murphy wrote:
> > > On 05/03/2019 15:53, Maxime Ripard wrote:
> > >> Hi,
> > >>
> > >> On Fri, Mar 01, 2019 at 07:48:15PM +0200, Georgi Dja
On Mon, Mar 11, 2019 at 6:11 PM Maxime Ripard wrote:
>
> On Fri, Mar 08, 2019 at 12:09:47AM +0800, Chen-Yu Tsai wrote:
> > On Thu, Mar 7, 2019 at 11:48 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Mar 07, 2019 at 05:15:20PM +0200, Georgi Djakov wrote:
>
at controller over to a YAML schemas.
>
> Signed-off-by: Maxime Ripard
Looks good to me. However not sure why you replaced the clock index macros
with raw numbers.
Reviewed-by: Chen-Yu Tsai
___
dri-devel mailing list
dri-deve
On Fri, May 31, 2019 at 2:54 AM Maxime Ripard wrote:
>
> Hi,
>
> On Thu, May 30, 2019 at 09:48:02PM +0800, Chen-Yu Tsai wrote:
> > On Mon, May 27, 2019 at 8:09 PM Maxime Ripard
> > wrote:
> > >
> > > The Allwinner SoCs have a MIPI-DSI and MIPI-D-PHY co
> Signed-off-by: Jagan Teki
Acked-by: Chen-Yu Tsai
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
> Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
umbers, for more code
> readability.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
Use the existing macros, instead of real numbers for more
> code readability.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
However, you might want to rename the clock first, then switch to
using the index macros?
___
On Fri, Jun 14, 2019 at 11:19 AM Chen-Yu Tsai wrote:
>
> On Fri, Jun 14, 2019 at 2:53 AM Jagan Teki wrote:
> >
> > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > LCD interfaces like RGB, LVDS and DSI.
> >
> > Like TCON TV0, TV1 these LCD0, LC
On Fri, Jun 14, 2019 at 2:54 AM Jagan Teki wrote:
>
> According to Fig 7-2. TCON Top Block Diagram in User manual.
>
> TCON TOP can have an hierarchy for TCON_LCD0, LCD1 like
> TCON_TV0, TV1 so, the tcon top would handle the clocks of
> TCON_LCD0, LCD1 similar like TV0, TV1.
That is not guarantee
On Fri, Jun 14, 2019 at 5:48 PM Jagan Teki wrote:
>
> On Fri, Jun 14, 2019 at 9:16 AM Chen-Yu Tsai wrote:
> >
> > On Fri, Jun 14, 2019 at 2:54 AM Jagan Teki
> > wrote:
> > >
> > > According to Fig 7-2. TCON Top Block Diagram in User manual.
>
On Fri, Jun 14, 2019 at 6:56 PM Jagan Teki wrote:
>
> On Fri, Jun 14, 2019 at 9:05 AM Chen-Yu Tsai wrote:
> >
> > On Fri, Jun 14, 2019 at 11:19 AM Chen-Yu Tsai wrote:
> > >
> > > On Fri, Jun 14, 2019 at 2:53 AM Jagan Teki
> > > wrote:
> > >
On Sat, Jun 15, 2019 at 12:44 AM Jagan Teki wrote:
>
> TCON TOP have clock gates for TV0, TV1, dsi and right
> now these are register during bind call.
>
> Of which, dsi clock gate would required during DPHY probe
> but same can miss to get since tcon top is not bound at
> that time.
>
> To solve,
On Mon, Jun 17, 2019 at 7:45 PM Maxime Ripard wrote:
>
> On Fri, Jun 14, 2019 at 10:13:20PM +0530, Jagan Teki wrote:
> > TCON TOP have clock gates for TV0, TV1, dsi and right
> > now these are register during bind call.
> >
> > Of which, dsi clock gate would required during DPHY probe
> > but same
On Mon, Jun 17, 2019 at 6:30 PM Jagan Teki wrote:
>
> On Sun, Jun 16, 2019 at 11:01 AM Chen-Yu Tsai wrote:
> >
> > On Sat, Jun 15, 2019 at 12:44 AM Jagan Teki
> > wrote:
> > >
> > > TCON TOP have clock gates for TV0, TV1, dsi and right
>
On Tue, Jun 18, 2019 at 3:12 PM Jagan Teki wrote:
>
> On Mon, Jun 17, 2019 at 6:31 PM Chen-Yu Tsai wrote:
> >
> > On Mon, Jun 17, 2019 at 7:45 PM Maxime Ripard
> > wrote:
> > >
> > > On Fri, Jun 14, 2019 at 10:13:20PM +0530, Jagan Teki wrote:
> >
On Tue, Jun 18, 2019 at 3:45 PM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 12:49 PM Chen-Yu Tsai wrote:
> >
> > On Mon, Jun 17, 2019 at 6:30 PM Jagan Teki
> > wrote:
> > >
> > > On Sun, Jun 16, 2019 at 11:01 AM Chen-Yu Tsai wrote:
> > > &g
On Tue, Jun 18, 2019 at 6:34 PM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 1:23 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 3:45 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jun 18, 2019 at 12:49 PM Chen-Yu Tsai wrote:
> > > &
On Tue, Jun 18, 2019 at 6:51 PM Jagan Teki wrote:
>
> On Fri, Jun 14, 2019 at 8:15 PM Maxime Ripard
> wrote:
> >
> > On Fri, Jun 14, 2019 at 12:03:13PM +0530, Jagan Teki wrote:
> > > On Thu, Jun 13, 2019 at 6:56 PM Maxime Ripard
> > > wrote:
> > > >
> > > > On Wed, Jun 05, 2019 at 01:17:11PM +
On Tue, Jun 18, 2019 at 8:11 PM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 5:13 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 6:51 PM Jagan Teki
> > wrote:
> > >
> > > On Fri, Jun 14, 2019 at 8:15 PM Maxime Ripard
> > > wrote:
On Fri, Jun 21, 2019 at 2:51 AM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 8:15 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 8:11 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jun 18, 2019 at 5:13 PM Chen-Yu Tsai wrote:
> > > &
On Fri, Jun 21, 2019 at 12:24 AM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 4:24 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 6:34 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jun 18, 2019 at 1:23 PM Chen-Yu Tsai wrote:
> > > &
On Fri, May 24, 2019 at 6:27 PM Jagan Teki wrote:
>
> On Fri, May 24, 2019 at 2:18 AM Maxime Ripard
> wrote:
> >
> > On Mon, May 20, 2019 at 02:33:10PM +0530, Jagan Teki wrote:
> > > The current code is computing vertical video start delay as
> > >
> > > delay = mode->vtotal - (mode->vsync_end -
Hi,
On Mon, May 20, 2019 at 5:07 PM Jagan Teki wrote:
>
> start value in video start delay computation done in below commit
> is as per the legacy bsp drivers/video/sunxi/legacy..
> "drm/sun4i: dsi: Change the start delay calculation"
> (sha1: da676c6aa6413d59ab0a80c97bbc273025e640b2)
There is a
On Mon, Jun 24, 2019 at 11:49 PM Andrzej Hajda wrote:
>
> On 24.06.2019 17:05, Jernej Škrabec wrote:
> > Dne ponedeljek, 24. junij 2019 ob 17:03:31 CEST je Andrzej Hajda napisal(a):
> >> On 26.05.2019 23:20, Jonas Karlman wrote:
> >>> This patch enables Dynamic Range and Mastering InfoFrame on H6.
On Tue, Jun 25, 2019 at 12:03 AM Jernej Škrabec wrote:
>
> Dne ponedeljek, 24. junij 2019 ob 17:56:30 CEST je Chen-Yu Tsai napisal(a):
> > On Mon, Jun 24, 2019 at 11:49 PM Andrzej Hajda wrote:
> > > On 24.06.2019 17:05, Jernej Škrabec wrote:
> > > > Dne poned
t; +
> tcon0_out_dsi: endpoint@1 {
> reg = <1>;
> remote-endpoint = <&dsi_in_tcon0>;
> diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi
> b/arch/arm/boot/dts/sun8i-q8-common.dtsi
> index 53104f4ccacc..3d9a1524e17e 100644
>
On Fri, Mar 15, 2019 at 4:16 AM Maxime Ripard wrote:
>
> Since most of the display IPs have a single endpoint, having a reg
> property, a unit-address and #address-cells and #size-cells will emit a
> warning.
>
> Let's remove those.
>
> Signed-off-by: Maxime Ri
e address-cells and
> size-cells properties anymore.
>
> Fix those
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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e address-cells and
> size-cells properties anymore.
>
> Fix those
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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e address-cells and
> size-cells properties anymore.
>
> Fix those
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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e address-cells and
> size-cells properties anymore.
>
> Fix those
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
but we're going to end up adding it back if DSI gets added.
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e address-cells and
> size-cells properties anymore.
>
> Fix those
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
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e address-cells and
> size-cells properties anymore.
>
> Fix those
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
___
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