On Sun, 26 May 2019 12:50:51 -0700, Ilpo Järvinen wrote:
>
> Hi all,
>
> I've a workstation which has internal VGA that is detected as AST 2400 and
> with it EDID has been always quite flaky (except for some time it worked
> with 4.14 long enough that I thought the problems would be past until the
synchronisation inside the reset watchdog, nor do we need
such a short timeout before declaring the device as unrecoverable.
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/3575
Signed-off-by: Chris Wilson
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_reset.c | 8
1 file
synchronisation inside the reset watchdog, nor do we need
such a short timeout before declaring the device as unrecoverable.
v2: Restore watchdog timeout to the previous 5 seconds (Ashutosh)
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/3575
Signed-off-by: Chris Wilson
Signed-off-by: Ashutosh Dixit
Perf limit reasons bit positions were off by one.
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Signed-off-by: Ashutosh Dixit
Acked-by: Andi Shyti
Reviewed-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_
Since https://patchwork.freedesktop.org/series/107908/ is now merged,
rebase this series on latest drm-tip and post a clean series.
Ashutosh Dixit (2):
drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL
drm/i915/rps: Freq caps for MTL
Tilak Tangudu (1):
drm/i915/debugfs: Add
PERF_LIMIT_REASONS register for MTL media gt is different now.
v2: Avoid static inline for intel_gt_perf_limit_reasons_reg() (Jani)
Cc: Jani Nikula
Cc: Badal Nilawar
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c| 6 ++
drivers
clear fop clears the upper 16 "log" bits, the get fop
gets all 32 "log" and "status" bits.
v2: Expand commit message and clarify "log" and "status" bits in
comment (Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Signe
For MTL, when reading from HW, RP0, RP1 (actuall RPe) and RPn freq use an
entirely different set of registers with different fields, bitwidths and
units.
v2: Move MTL check into a separate function (Jani)
Cc: Jani Nikula
Cc: Badal Nilawar
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo
From: Chris Wilson
If attempting to perform a GT reset takes long than 5 seconds (including
resetting the display for gen3/4), then we declare all hope lost and
discard all user work and wedge the device to prevent further
misbehaviour. 5 seconds is too short a time for such drastic action, as
we
From: Chris Wilson
If attempting to perform a GT reset takes long than 5 seconds (including
resetting the display for gen3/4), then we declare all hope lost and
discard all user work and wedge the device to prevent further
misbehaviour. 5 seconds is too short a time for such drastic action, as
we
reasons in debugfs")
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt.c| 4
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 10 +-
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.
r address: c9bb81a8
<1> [88.829438] #PF: supervisor read access in kernel mode
<1> [88.829447] #PF: error_code(0x) - not-present page
Bspec: 20008
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/6863
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces
the sysfs portions of 0d2d201095e9. The debugfs portion of
0d2d201095e9 is not available in drm-intel-fixes so has not been
backported.
Bspec: 20008
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/6863
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Signed-off-b
.
Previous discussion on these patches can be seen here:
https://patchwork.freedesktop.org/patch/484238/?series=102665&rev=4
https://patchwork.freedesktop.org/patch/483988/?series=102665&rev=3
Cc: Matt Roper
Cc: Tvrtko Ursulin
Cc: Andi Shyti
Signed-off-by: Ashuto
Add the following sysfs files to gt/gtN/.defaults/:
* rps_min_freq_mhz
* rps_max_freq_mhz
v2: Correct gt/gtN/.defaults/* file names in commit message
v3: Remove rps_boost_freq_mhz since it is not consumed by userspace
Cc: Tvrtko Ursulin
Cc: Andi Shyti
Signed-off-by: Ashutosh Dixit
Reviewed-by
2: Changed 'struct intel_rps_defaults rps_defaults' to
'struct gt_defaults defaults' (Andi)
Cc: Tvrtko Ursulin
Cc: Andi Shyti
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 5 +
drivers/gpu/drm/i915/gt/intel_g
Previous documentation suggested that PL1 power limit is always
enabled. However we now find this not to be the case on some
platforms (such as ATSM). Therefore enable PL1 power limit during hwmon
initialization.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 5 +
1
Previous documentation suggested that PL1 power limit is always
enabled. However we now find this not to be the case on some
platforms (such as ATSM). Therefore enable PL1 power limit during hwmon
initialization.
Bspec: 51864
v2: Add Bspec reference (Gwan-gyeong)
Signed-off-by: Ashutosh Dixit
: 99f55efb79114 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
Signed-off-by: Ashutosh Dixit
Reviewed-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/i915_hwmon.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwm
ed, revert 0349c41b0596.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 468
patches can be squashed if
needed.
Ashutosh Dixit (3):
drm/i915/hwmon: Replace hwm_field_scale_and_write with
hwm_power_max_write
drm/i915/hwmon: Enable PL1 limit when writing limit value to HW
drm/i915/hwmon: Expose power1_max_enable
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 7
limit) values correctly. It can also be used to
enable/disable the PL1 power limit.
Signed-off-by: Ashutosh Dixit
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 7 +++
drivers/gpu/drm/i915/i915_hwmon.c | 48 +--
2 files changed, 51 insertions(+), 4 deletions
: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 85195d61f89c7..7c20a6f47b92e 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm
where the function needs to be extended.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 36 ++-
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 1225bc432f0d5
;d by hwmon) so that the first two
patches can get merged. The first two patches are sufficient to fix the
main ATSM issue.
Ashutosh Dixit (2):
drm/i915/hwmon: Replace hwm_field_scale_and_write with
hwm_power_max_write
drm/i915/hwmon: Enable PL1 limit when writing limit value
where the function needs to be extended.
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_hwmon.c | 36 ++-
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915
: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_hwmon.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 85195d61f89c7..7c20a6f47b92e 100644
--- a/drivers/gpu/drm/i915
puting ilog2(0) but this resulted in the corner-case bug
below. Therefore allow writes of 0 now but special case that write to
x = y = 0.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7754
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 14 +-
1 file c
On newer generations, the GEN12_RPSTAT1 register contains more than freq
information, e.g. see GEN12_VOLTAGE_MASK. Therefore use only the freq bits
to decide whether to fall back to requested freq.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 6 ++
1 file changed, 2
A couple of minor fixes to the PMU requested freq fallback for PMU freq
sampling.
Ashutosh Dixit (2):
drm/i915/pmu: Use only freq bits for falling back to requested freq
drm/i915/pmu: Use correct requested freq for SLPC
drivers/gpu/drm/i915/i915_pmu.c | 13 -
1 file changed, 8
SLPC does not use 'struct intel_rps'. Use UNSLICE_RATIO bits from
GEN6_RPNSWREQ for SLPC. See intel_rps_get_requested_frequency.
Bspec: 52745
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
as older generations (before Gen6) which were previously missed due to the
non-use of common functions across sysfs and PMU.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_rps.c | 36 +
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
2 files changed, 32
code future proof where sometimes code has been updated for
sysfs and PMU has been missed.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_rps.c | 10 --
drivers/gpu/drm/i915/gt/intel_rps.h | 1 -
drivers/gpu/drm/i915/i915_pmu.c | 10 --
3 files changed, 4
(rps) and slpc which was previously missed due to the non-use of
common functions across sysfs and PMU.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_rps.c | 22 +++---
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +-
2 files changed, 20 insertions(+), 4 deletions
code future proof where sometimes code has been updated for
sysfs and PMU has been missed.
Ashutosh Dixit (3):
drm/i915/rps: Expose read_actual_frequency_fw for PMU
drm/i915/rps: Expose get_requested_frequency_fw for PMU
drm/i915/pmu: Use common freq functions with sysfs
drivers/gpu/drm/i915
rtko Ursulin
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 27 ++-
1 file changed, 2 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf1..eda03f264792 100644
--- a/drivers/gpu
Roeck
Signed-off-by: Dale B Stimson
Signed-off-by: Ashutosh Dixit
Signed-off-by: Riana Tauro
Signed-off-by: Badal Nilawar
Acked-by: Guenter Roeck
Reviewed-by: Ashutosh Dixit
Reviewed-by: Anshuman Gupta
Reviewed-by: Andi Shyti
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 20
/ (Ashutosh)
v6: Change contact to intel-gfx (Rodrigo)
GEN12_RPSTAT1 is available for all Gen12+ (Andi)
Signed-off-by: Ashutosh Dixit
Signed-off-by: Dale B Stimson
Signed-off-by: Badal Nilawar
Acked-by: Guenter Roeck
Reviewed-by: Ashutosh Dixit
Reviewed-by: Anshuman Gupta
Reviewed-by: Andi
: Use hwm_ prefix for static functions (Ashutosh)
v5: KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko)
v6: Change contact to intel-gfx (Rodrigo)
Cc: Sujaritha Sundaresan
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
Acked-by: Guenter Roeck
Reviewed-by: Anshuman Gupta
)
Removed else in hwm_attributes_visible (Andi)
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
Acked-by: Guenter Roeck
Reviewed-by: Anshuman Gupta
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 9 ++
drivers/gpu/drm/i915/i915_hwmon.c | 119
-intel-i915-hwmon
to MAINTAINERS
Cc: Guenter Roeck
Cc: Anshuman Gupta
Signed-off-by: Riana Tauro
Signed-off-by: Badal Nilawar
Signed-off-by: Ashutosh Dixit
Acked-by: Guenter Roeck
Reviewed-by: Ashutosh Dixit
Reviewed-by: Anshuman Gupta
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 7
doc (Tvrtko)
v5: Change contact to intel-gfx (Rodrigo)
Change return type of hwm_energy to void (Andi)
Signed-off-by: Dale B Stimson
Signed-off-by: Ashutosh Dixit
Signed-off-by: Riana Tauro
Signed-off-by: Badal Nilawar
Acked-by: Guenter Roeck
Reviewed-by: Ashutosh Dixit
Reviewed-by
)
v6: s/kzalloc/devm_kzalloc/ (Andi)
v7: s/hwmon_device_register_with_info/
devm_hwmon_device_register_with_info/ (Ashutosh)
Cc: Guenter Roeck
Signed-off-by: Dale B Stimson
Signed-off-by: Ashutosh Dixit
Signed-off-by: Riana Tauro
Signed-off-by: Badal Nilawar
Acked-by: Guenter Roeck
Reviewed-by:
)
v8: s/hwmon_device_register_with_info/
devm_hwmon_device_register_with_info/ (Ashutosh)
v9: Addressed review comments from Rodrigo and Andi
Ashutosh Dixit (2):
drm/i915/hwmon: Expose card reactive critical power
drm/i915/hwmon: Expose power1_max_interval
Dale B Stimson (4):
drm
ff-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_rc6.c | 56 +++
drivers/gpu/drm/i915/gt/intel_rc6.h | 9 ++-
drivers/gpu/drm/i9
t;drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
- Addressed review comments, please see individual patches for changelogs
Ashutosh Dixit (1):
drm/i915/gt: Change RC6 residency functions to accept register ID's
Badal Nilawar (2):
From: Badal Nilawar
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
Bspec: 66300
Signed-off-by: Ashutosh Dixit
refactor (Jani N)
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 57 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rc6.c | 17 --
3 files changed, 75 insertions(+), 4
i
Suggested-by: Jani Nikula
Reported-by: Jani Nikula
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_rc6.c | 55 +++
drivers/gpu/drm/i9
Nilawar
Signed-off-by: Ashutosh Dixit
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_rps.c | 32 +
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers/gpu/drm/i915/i915_pmu.c | 3 +--
4 files changed
t;drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Minor changes to other patches, please see indiv
refactor (Jani N)
v4: Move MTL branch to top in drpc_show
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 60 ++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rc6.c | 17
forcewake for Gen12+ and
returning 0 freq in RC6
Bspec: 66300
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff
register for GT freq" to this series
v7: Rebuild, identical to v6
v8:
- Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the series
(based on Rodrigo's review) to consistently use REG_FIELD_GET
- Minor changes to other patches, please see individual pat
forcewake for Gen12+ and
returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)
Bspec: 66300
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++--
2 files
Shyti
Signed-off-by: Don Hiatt
Signed-off-by: Badal Nilawar
Signed-off-by: Ashutosh Dixit
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 32 +
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers
intel_rc6_types.h in intel_rc6.h (Jani)
Suggested-by: Rodrigo Vivi
Suggested-by: Jani Nikula
Reported-by: Jani Nikula
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
drivers/gpu/drm
refactor (Jani N)
v4: Move MTL branch to top in drpc_show
v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm
tches for changelogs
v9: Rebuild, identical to v8
v10: Address review comments from Rodrigo on Patch 5
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Mod
intel_rc6_types.h in intel_rc6.h (Jani)
Suggested-by: Rodrigo Vivi
Suggested-by: Jani Nikula
Reported-by: Jani Nikula
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
refactor (Jani N)
v4: Move MTL branch to top in drpc_show
v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
v6: Add MISSING_CASE for gt_core_status switch statement (Rodrigo)
Change state name for MTL_CC0 to C0 (from "on") (Rodrigo)
Signed-off-by: Ashutosh Dixit
Signed-off-by: Bad
Shyti
Signed-off-by: Don Hiatt
Signed-off-by: Badal Nilawar
Signed-off-by: Ashutosh Dixit
Reviewed-by: Andi Shyti
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 32 +
drivers/gpu/drm/i915/gt
forcewake for Gen12+ and
returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)
Bspec: 66300
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
Reviewed-by: Ashutosh Dixit
Acked-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
drivers/gpu/drm/i915
tches for changelogs
v9: Rebuild, identical to v8
v10: Address review comments from Rodrigo on Patch 5
v11: Change state name for MTL_CC0 to RC0 in Patch 5
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm
ned-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 59 ++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rc6.c | 17 --
3 files changed, 76
intel_rc6_types.h in intel_rc6.h (Jani)
Suggested-by: Rodrigo Vivi
Suggested-by: Jani Nikula
Reported-by: Jani Nikula
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
forcewake for Gen12+ and
returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)
Bspec: 66300
Signed-off-by: Ashutosh Dixit
Signed-off-by: Badal Nilawar
Reviewed-by: Ashutosh Dixit
Acked-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4
drivers/gpu/drm/i915
Shyti
Signed-off-by: Don Hiatt
Signed-off-by: Badal Nilawar
Signed-off-by: Ashutosh Dixit
Reviewed-by: Andi Shyti
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 32 +
drivers/gpu/drm/i915/gt
. The checks are not needed because the mask is formed using
REG_GENMASK (so is actually a compile time constant).
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7354
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion
/7354
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c| 2 +-
drivers/gpu/drm/i915/i915_reg_defs.h | 17 +++--
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/drivers/gpu/drm/i915/i915_hwmon.c
index 9e97814930254
HW allows arbitrary PL1 limits to be set but silently clamps these values
to "typical but not guaranteed" min/max values in pkg_power_sku
register. Follow the same pattern for sysfs, allow arbitrary PL1 limits to
be set but display clamped values when read.
Signed-off-by: Ashu
esktop.org/drm/intel/-/issues/7704
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c| 39
drivers/gpu/drm/i915/intel_mchbar_regs.h | 2 ++
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
b/
In preparation for follow-on patches, refactor hwm_power_max_write to take
hwmon_lock and runtime pm wakeref at start of the function and release them
at the end, therefore acquiring these just once each.
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915
Instead of erroring out when GuC reset is in progress, block waiting for
GuC reset to complete which is a more reasonable uapi behavior.
v2: Avoid race between wake_up_all and waiting for wakeup (Rodrigo)
v3: Remove timeout when blocked (Tvrtko)
Signed-off-by: Ashutosh Dixit
Reviewed-by
rning reported by kernel
build robot by creating new err_rps label
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 13 +++--
drivers/gpu/drm/i915/i915_hwmon.c
v6: Update Patch 3 to remove the timeout when blocked
v1-v5: Please see individual patches for revision history
Ashutosh Dixit (3):
drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write
drm/i915/guc: Disable PL1 power limit when loading GuC firmware
drm/i915/hwmon: Block
ad of enabling it, avoiding the freq drop
issue.
v2: Add explanation for bugs mentioned below (Rodrigo)
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8060
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
..
https://gitlab.freedesktop.org/drm/intel/-/issues/8060
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
.../ABI/testing/sysfs-driver-intel-i915-hwmon | 4 ++-
drivers/gpu/drm/i915/i915_hwmon.c | 26 +++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --
Split the v3 patch into 3 patches for easier review, can squash later if needed.
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Ashutosh Dixit (3):
drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write
drm/i915/guc: Disable PL1 power limit when loading GuC firmware
drm/i915/hwmon
Instead of erroring out when GuC reset is in progress, block waiting for
GuC reset to complete which is a more reasonable uapi behavior.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers
In preparation for follow-on patches, refactor hwm_power_max_write to take
hwmon_lock and runtime pm wakeref at start of the function and release them
at the end, therefore acquiring these just once each.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 28
ssues/8062
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 ++
drivers/gpu/drm/i915/i915_hwmon.c | 40 +++
drivers/gpu/drm/i915/i915_hwmon.h | 7 +
3 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel
rning reported by kernel
build robot by creating new err_rps label
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 13 +++--
drivers/gpu/drm/i915/i915_hwmon.c
Updates to Patch 2/3 and Patch 3/3 in this version.
Ashutosh Dixit (3):
drm/i915/hwmon: Get mutex and rpm ref just once in hwm_power_max_write
drm/i915/guc: Disable PL1 power limit when loading GuC firmware
drm/i915/hwmon: Block waiting for GuC reset to complete
drivers/gpu/drm/i915/gt/uc
In preparation for follow-on patches, refactor hwm_power_max_write to take
hwmon_lock and runtime pm wakeref at start of the function and release them
at the end, therefore acquiring these just once each.
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915
Instead of erroring out when GuC reset is in progress, block waiting for
GuC reset to complete which is a more reasonable uapi behavior.
v2: Avoid race between wake_up_all and waiting for wakeup (Rodrigo)
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 38
LPC. The actual freq
will be 0 when gt is in RC6 which is correct. Also this is rare since PMU
freq sampling happens only when gt is unparked.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
older
generations (prior to Gen6). It also future proofs the PMU where sometimes
code has been updated for sysfs and PMU has been missed.
Ashutosh Dixit (2):
drm/i915/pmu: Use functions common with sysfs to read actual freq
drm/i915/pmu: Remove fallback to requested freq for SLPC
drivers/gpu/drm
older
generations (prior to Gen6). It also future proofs the PMU where sometimes
code has been updated for sysfs and PMU has been missed.
Fixes: 22009b6dad66 ("drm/i915/mtl: Modify CAGF functions for MTL")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8280
Signed-off-by: Ashu
ses: https://gitlab.freedesktop.org/drm/intel/-/issues/8280
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_rps.c | 34 -
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +-
drivers/gpu/drm/i915/i915_pmu.c | 10 -
3 files changed, 24 insertions(+), 22 deletion
older
generations (prior to Gen6). It also future proofs the PMU where sometimes
code has been updated for sysfs and PMU has been missed.
Ashutosh Dixit (2):
drm/i915/pmu: Use functions common with sysfs to read actual freq
drm/i915/pmu: Remove fallback to requested freq for SLPC
drivers/gpu/drm
LPC. The actual freq
will be 0 when gt is in RC6 which is correct. Also this is rare since PMU
freq sampling happens only when gt is unparked.
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
limit was enabled and set to a low value). Therefore disable the PL1 power
limit when possible when loading GuC firmware.
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 ++-
drivers/gpu/drm/i915
/drm/intel/-/issues/8062
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 10 ++-
drivers/gpu/drm/i915/i915_hwmon.c | 39 +++
drivers/gpu/drm/i915/i915_hwmon.h | 7 +
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a
intel_rps_read_punit_req
Fixes: 22009b6dad66 ("drm/i915/mtl: Modify CAGF functions for MTL")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8280
Signed-off-by: Ashutosh Dixit
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_rps.c | 38 -
drivers/gp
explanatory comments
- Function renames
- Type corrections
- Locking annotation
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 +++
drivers/gpu/drm/i915/i915_hwmon.c | 39
PL1 power
limit"). Revert it again.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/8062
Fixes: ee892ea83d99 ("drm/i915/hwmon: Enable PL1 power limit")
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_hwmon.c | 5 -
1 file
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