rnel.org/r/20250430085658.540746-1-oushixiong1025%40163.com
patch subject: [PATCH 1/3] dma-buf: add flags to skip map_dma_buf() for some
drivers
config: arc-randconfig-002-20250501
(https://download.01.org/0day-ci/archive/20250502/202505020434.7efuiajh-...@intel.com/config)
compiler: arc-linu
On Thu, Mar 06, 2025 at 07:11:14PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
> There's a separate path that allows register access from CPUSS.
> Describe it.
>
> Signed-off-by: Konrad Dybcio
> ---
> Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6
> +-
>
On Thu, May 01, 2025 at 01:28:52PM -0700, Matthew Brost wrote:
> On Thu, May 01, 2025 at 12:59:03PM -0700, Kees Cook wrote:
> > Casting through a "void *" isn't sufficient to convince the randstruct
> > GCC plugin that the result is intentional. Instead operate through an
> > explicit union to sile
Casting through a "void *" isn't sufficient to convince the randstruct
GCC plugin that the result is intentional. Instead operate through an
explicit union to silence the warning:
drivers/gpu/drm/ttm/ttm_backup.c: In function 'ttm_file_to_backup':
drivers/gpu/drm/ttm/ttm_backup.c:21:16: note: rand
On Thu, May 01, 2025 at 05:24:38PM -0700, Kees Cook wrote:
> Casting through a "void *" isn't sufficient to convince the randstruct
> GCC plugin that the result is intentional. Instead operate through an
> explicit union to silence the warning:
>
> drivers/gpu/drm/ttm/ttm_backup.c: In function 'tt
Hi Prabhakar,
Thanks for the patch.
> -Original Message-
> From: Prabhakar
> Sent: 30 April 2025 21:41
> Subject: [PATCH v4 03/15] dt-bindings: display: renesas,rzg2l-du: Add support
> for RZ/V2H(P) SoC
>
> From: Lad Prabhakar
>
> The DU block on the RZ/V2H(P) SoC is identical to the
Hi Prabhakar,
> -Original Message-
> From: Prabhakar
> Sent: 30 April 2025 21:41
> Subject: [PATCH v4 05/15] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC
>
> From: Lad Prabhakar
>
> The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
> Compression Processor (FCPV
On Mon, Apr 28, 2025 at 02:15:12PM -0700, Doug Anderson wrote:
Hello Jayesh,
> Hi,
>
> On Thu, Apr 24, 2025 at 6:32 PM Kumar, Udit wrote:
> >
> > Hello Jayesh,
> >
> > On 4/24/2025 4:24 PM, Jayesh Choudhary wrote:
> > > For TI SoC J784S4, the display pipeline looks like:
> > > TIDSS -> CDNS-DSI
These properties are very useful to have and should be accessible.
Signed-off-by: Alexandre Courbot
---
rust/kernel/dma.rs | 14 ++
1 file changed, 14 insertions(+)
diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs
index
605e01e35715667f93297fd9ec49d8e7032e0910..18602d771054fceb
We will extend the firmware methods, so move it to its own module
instead to keep gpu.rs focused.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/firmware.rs | 46 +--
drivers/gpu/nova-core/gpu.rs | 35 +++--
2 files cha
We will need to perform things like allocating DMA memory during device
creation, so make sure to take the device context that will allow us to
perform these actions.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/gpu.rs | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
Note, I just noticed I wrote an earlier (less precise) version of this
patch here, which I completely forgot about:
https://patchwork.freedesktop.org/patch/546972/
It's not obvious off-hand which CRTCs will get a page-flip event
when using this flag in an atomic commit, because it's all
implicitly implied based on the contents of the atomic commit.
Document requirements for using this flag and how to request an
event for a CRTC.
Note, because prepare_signali
Ah, sorry, I missed this message.
On Monday, April 14th, 2025 at 15:28, Ville Syrjälä
wrote:
> Should probably add a caveat that this needs to be a sync commit/flip.
> The way the async flip was specified for atomic explicitly requires the
> driver to ignore the plane when the fb doesn't change
From: Max Krummenacher
The bridge driver currently disables handling the hot plug input and
relies on a always connected eDP panel with fixed delays when the
panel is ready.
If one uses the bridge for a regular display port monitor this
assumption is no longer true.
If used with a display port m
Hi Alex,
Am Dienstag, 22. April 2025, 09:04:39 Mitteleuropäische Sommerzeit schrieb Andy
Yan:
> From: Andy Yan
>
> When preparing to convert the current inno hdmi driver into a
> bridge driver, I found that there are several issues currently
> existing with it:
>
> 1. When the system starts up
On 5/1/2025 11:31 AM, Timur Tabi wrote:
> On Thu, 2025-05-01 at 11:22 -0400, Joel Fernandes wrote:
>> Also not mutating it like that matches the pattern in the rest of this file
>> so
>> I'd leave it as-is.
>
> Oh I see now. One version changes a variable, and the other returns a new
> value.
On 5/1/2025 11:19 AM, Timur Tabi wrote:
> On Thu, 2025-05-01 at 21:58 +0900, Alexandre Courbot wrote:
>
>
>> +impl UsizeAlign for usize {
>> + fn align_up(mut self, align: usize) -> usize {
>> + self = (self + align - 1) & !(align - 1);
>> + self
>> + }
>> +}
>> +
>> +/// A
On Thu, 2025-05-01 at 11:22 -0400, Joel Fernandes wrote:
> Also not mutating it like that matches the pattern in the rest of this file
> so
> I'd leave it as-is.
Oh I see now. One version changes a variable, and the other returns a new
value.
rnel.org/r/20250430085658.540746-2-oushixiong1025%40163.com
patch subject: [PATCH 2/3] drm/prime: Support importing DMA-BUF without sg_table
config: arm64-randconfig-003-20250501
(https://download.01.org/0day-ci/archive/20250501/202505011655.qtmh4ua7-...@intel.com/config)
compiler: clang version
On 01-05-2025 02:10, Prabhakar wrote:
From: Lad Prabhakar
Add support for PLLDSI and PLLDSI divider clocks.
Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
CPG and DSI drivers.
The DSI PLL is functi
On Thu, 2025-05-01 at 21:58 +0900, Alexandre Courbot wrote:
> +impl UsizeAlign for usize {
> + fn align_up(mut self, align: usize) -> usize {
> + self = (self + align - 1) & !(align - 1);
> + self
> + }
> +}
> +
> +/// Aligns `val` upwards to the nearest multiple of `align`.
>
On 4/25/2025 2:35 PM, Konrad Dybcio wrote:
> On 7/15/24 10:04 PM, Akhil P Oommen wrote:
>> On Tue, Jul 09, 2024 at 12:45:29PM +0200, Konrad Dybcio wrote:
>>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>>> abstracted through SMEM, instead of being directly available in a fus
Hi Alok,
Thanks for your email.
> From: ALOK TIWARI
> Sent: 01 May 2025 10:51
> Subject: Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI
> clocks
>
>
> On 01-05-2025 02:10, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add support for PLLDSI and PLLDSI divider clocks.
> >
Acquiring the BAR temporarily to access is going to be a very common
pattern, that typically takes two lines of code and introduces a
short-lived local variable.
Add the Nova-local convenience with_bar!() macro, which uses
Revocable::try_access_with() and converts its returned Option into the
prop
Functions that take a &Devres as argument might need to print error
messages related on behalf the device. Providing the reference here
removes the need for drivers to store their own for that sole purpose.
Signed-off-by: Alexandre Courbot
---
rust/kernel/devres.rs | 6 ++
1 file changed, 6
The FWSEC firmware needs to be extracted from the VBIOS and patched with
the desired command, as well as the right signature. Do this so we are
ready to load and run this firmware into the GSP falcon and create the
FRTS region.
[joelagn...@nvidia.com: give better names to FalconAppifHdrV1's fields
On Wed, Apr 30, 2025 at 10:28:48AM +0200, Heiko Stuebner wrote:
> Working on an upcoming board dts, I noticed a dtc check warning
> about the port node and at the same time the kernel-test-robot
> noticed the same warning with a overlay I added recently.
>
> So allow the port node in the binding o
On 5/1/2025 10:18 AM, Alexandre Courbot wrote:
[..]
>> On Thu, May 01, 2025 at 09:58:33PM +0900, Alexandre Courbot wrote:
>>> Add the common Falcon code and HAL for Ampere GPUs, and instantiate the
>>> GSP and SEC2 Falcons that will be required to boot the GSP.
>>>
>>> Signed-off-by: Alexandre Cour
There's a few issues with this function, mainly:
* This function -probably- should have been unsafe from the start. Pointers
are not always necessarily valid, but you want a function that does
field-projection for a pointer that can travel outside of the original
struct to be unsafe, at leas
Just some patches to fix a handful of minor issues, some of which were already
mentioned on the mailing list. Some of these patches also make it just a
little bit easier to add the shmem bindings from Asahi in the future.
This patch series applies on top of dakr's nova-next branch:
https://gitla
There is usually not much of a reason to use a raw pointer in a data
struct, so move this to NonNull instead.
Signed-off-by: Lyude Paul
---
rust/kernel/drm/gem/mod.rs | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/rust/kernel/drm/gem/mod.rs b/rust/kernel/drm/gem/mod.rs
Currently we are requiring AlwaysRefCounted in most trait bounds for gem
objects, and implementing it by hand for our only current type of gem
object. However, all gem objects use the same functions for reference
counting - and all gem objects support reference counting.
We're planning on adding s
There's a few changes here:
* The rename, of course (this should also let us drop the clippy annotation
here)
* Return *mut bindings::drm_gem_object instead of
&Opaque - the latter doesn't really have any
benefit and just results in conversion from the rust type to the C type
having to be m
Hi Dave, Simona,
Fixes for 6.15.
The following changes since commit b4432656b36e5cc1d50a1f2dc15357543add530e:
Linux 6.15-rc4 (2025-04-27 15:19:23 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.15-2025-05-01
for you to fe
Hello Max,
On 01/05/25 13:42, Max Krummenacher wrote:
On Mon, Apr 28, 2025 at 02:15:12PM -0700, Doug Anderson wrote:
Hello Jayesh,
Hi,
On Thu, Apr 24, 2025 at 6:32 PM Kumar, Udit wrote:
Hello Jayesh,
On 4/24/2025 4:24 PM, Jayesh Choudhary wrote:
For TI SoC J784S4, the display pipeline lo
On Wed, Apr 09, 2025 at 09:24:41AM +0300, Raag Jadav wrote:
> On Wed, Apr 09, 2025 at 09:46:33AM +0800, jiangf...@kylinos.cn wrote:
> > From: Feng Jiang
> >
> > When calling scnprintf() to append recovery method to event_string,
> > the second argument should be `sizeof(event_string) - len`, othe
This adds FOURCCs for 3-plane 10/12/16bit YCbCr formats used by software
decoders like ffmpeg, dav1d and libvpx. The intended use-case is buffer
sharing between decoders and GPUs by allocating buffers with udmabuf or
dma-heaps, avoiding unnecessary copies or format conversions.
Unlike formats typi
Hello Alex,
On Thu, May 01, 2025 at 09:58:33PM +0900, Alexandre Courbot wrote:
> Add the common Falcon code and HAL for Ampere GPUs, and instantiate the
> GSP and SEC2 Falcons that will be required to boot the GSP.
>
> Signed-off-by: Alexandre Courbot
> ---
> drivers/gpu/nova-core/falcon.rs
From: Jeff Layton
Date: Wed, 30 Apr 2025 19:59:23 -0700
> On Wed, 2025-04-30 at 14:29 -0700, Kuniyuki Iwashima wrote:
> > From: Jeff Layton
> > Date: Wed, 30 Apr 2025 08:06:54 -0700
> > > After assigning the inode number to the namespace, use it to create a
> > > unique name for each netns refcou
Hi Tomi
On 24.04.25 18:49, Tomi Valkeinen wrote:
Hi,
On 24/04/2025 16:31, Laurent Pinchart wrote:
On Thu, Apr 24, 2025 at 02:53:18PM +0200, Robert Mader wrote:
Chris, Javier, Laurent - sorry for the noise, but given you reviewed
changes in the respective files before, maybe you can help me mo
On 4/30/2025 10:26 PM, neil.armstr...@linaro.org wrote:
> On 30/04/2025 18:39, Konrad Dybcio wrote:
>> On 4/30/25 6:19 PM, neil.armstr...@linaro.org wrote:
>>> On 30/04/2025 17:36, Konrad Dybcio wrote:
On 4/30/25 4:49 PM, neil.armstr...@linaro.org wrote:
> On 30/04/2025 15:09, Konrad Dybci
Hi Fabrizio,
On Thu, May 1, 2025 at 11:38 AM Fabrizio Castro
wrote:
>
> Hi Alok,
>
> Thanks for your email.
>
> > From: ALOK TIWARI
> > Sent: 01 May 2025 10:51
> > Subject: Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI
> > clocks
> >
> >
> > On 01-05-2025 02:10, Prabhakar wr
On Wed, 23 Apr 2025 18:44:16 +0200, Arnd Bergmann wrote:
> DRM_DISPLAY_DP_AUX_BUS cannot be selected when CONFIG_OF is disabled:
>
> WARNING: unmet direct dependencies detected for DRM_DISPLAY_DP_AUX_BUS
> Depends on [n]: HAS_IOMEM [=y] && DRM [=y] && OF [=n]
> Selected by [y]:
> - DRM_ROC
On 30/04/2025 21:51, Maíra Canal wrote:
When a CL/CSD job times out, we check if the GPU has made any progress
since the last timeout. If so, instead of resetting the hardware, we skip
the reset and let the timer get rearmed. This gives long-running jobs a
chance to complete.
However, when `ti
On Tue, Apr 29, 2025 at 09:39:56PM +0530, Badal Nilawar wrote:
> From: Rodrigo Vivi
>
> Xe PCODE FWCTL implements the generic FWCTL IOCLTs to allow limited
> access from user space (as admin) to some very specific PCODE
> Mailboxes only related to hardware configuration.
>
> PCODE is a Firmware
On 5/1/25 11:29 AM, Akhil P Oommen wrote:
> On 4/30/2025 10:26 PM, neil.armstr...@linaro.org wrote:
>> On 30/04/2025 18:39, Konrad Dybcio wrote:
>>> On 4/30/25 6:19 PM, neil.armstr...@linaro.org wrote:
On 30/04/2025 17:36, Konrad Dybcio wrote:
> On 4/30/25 4:49 PM, neil.armstr...@linaro.or
On Thu, 1 May 2025 at 04:11, Abhinav Kumar wrote:
>
>
>
> On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
> > DisplayPort requires per-segment link training when LTTPR are switched
> > to non-transparent mode, starting with LTTPR closest to the source.
> > Only when each segment is trained indiv
From: Joel Fernandes
This will be used in the nova-core driver where we need to upward-align
the image size to get to the next image in the VBIOS ROM.
[acour...@nvidia.com: handled conflicts due to removal of patch creating
num.rs]
Signed-off-by: Joel Fernandes
Signed-off-by: Alexandre Courbot
On Thu May 1, 2025 at 9:22 AM JST, Joel Fernandes wrote:
> Hi Alex,
>
> On 4/30/2025 8:09 PM, Alexandre Courbot wrote:
I am just not seeing the benefits of not using dyn for
this use case and only drawbacks. IMHO, we should try to not be doing the
compiler's job.
Maybe the
On Thu May 1, 2025 at 10:52 PM JST, Joel Fernandes wrote:
> Hello Alex,
>
> On Thu, May 01, 2025 at 09:58:33PM +0900, Alexandre Courbot wrote:
>> Add the common Falcon code and HAL for Ampere GPUs, and instantiate the
>> GSP and SEC2 Falcons that will be required to boot the GSP.
>>
>> Signed-off-
From: Jeff Layton
Date: Wed, 30 Apr 2025 20:42:40 -0700
> On Wed, 2025-04-30 at 20:07 -0700, Kuniyuki Iwashima wrote:
> > From: Jeff Layton
> > Date: Wed, 30 Apr 2025 19:59:23 -0700
> > > On Wed, 2025-04-30 at 14:29 -0700, Kuniyuki Iwashima wrote:
> > > > From: Jeff Layton
> > > > Date: Wed, 30
From: Jeff Layton
Date: Wed, 30 Apr 2025 08:06:54 -0700
> After assigning the inode number to the namespace, use it to create a
> unique name for each netns refcount tracker with the ns.inum value in
> it, and register a symlink to the debugfs file for it.
>
> init_net is registered before the re
From: Jeff Layton
Date: Wed, 30 Apr 2025 21:07:20 -0700
> On Wed, 2025-04-30 at 20:50 -0700, Kuniyuki Iwashima wrote:
> > From: Jeff Layton
> > Date: Wed, 30 Apr 2025 20:42:40 -0700
> > > On Wed, 2025-04-30 at 20:07 -0700, Kuniyuki Iwashima wrote:
> > > > From: Jeff Layton
> > > > Date: Wed, 30
On 5/1/2025 12:10 AM, Rob Clark wrote:
> On Wed, Apr 30, 2025 at 3:39 AM Konrad Dybcio
> wrote:
>>
>> On 4/29/25 2:17 PM, Dmitry Baryshkov wrote:
>>> On Mon, Apr 28, 2025 at 11:19:32PM +0200, Konrad Dybcio wrote:
On 4/28/25 12:44 PM, Akhil P Oommen wrote:
> On 4/14/2025 4:31 PM, Konrad Dy
Hey Laurent, thanks for the feedback!
On 24.04.25 15:31, Laurent Pinchart wrote:
On Thu, Apr 24, 2025 at 02:53:18PM +0200, Robert Mader wrote:
Chris, Javier, Laurent - sorry for the noise, but given you reviewed
changes in the respective files before, maybe you can help me moving
this forward?
Hey Javier, thanks for the reply anyway. FTR., the formats are very
similar to DRM_FORMAT_Q410, just with different alignment.
On 29.04.25 12:47, Javier Martinez Canillas wrote:
Robert Mader writes:
Hello Robert,
Chris, Javier, Laurent - sorry for the noise, but given you reviewed
changes i
A page of system memory is reserved so sysmembar can perform a read on
it if a system write occurred since the last flush. Do this early as it
can be required to e.g. reset the GPU falcons.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/gpu.rs | 51 ++
While programming the hardware, we frequently need to busy-wait until
a condition (like a given bit of a register to switch value) happens.
Add a basic `wait_on` helper function to wait on such conditions
expressed as a closure, with a timeout argument.
This is temporary as we will switch to `rea
Add the register!() macro, which defines a given register's layout and
provide bit-field accessors with a way to convert them to a given type.
This macro will allow us to make clear definitions of the registers and
manipulate their fields safely.
The long-term goal is to eventually move it to the
linux-firmware contains a directory for GA100, and it is a defined
chipset in Nouveau.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/gpu.rs | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index
4de67a
The layout of NV_PMC_BOOT_0 has two small issues:
- The "chipset" field, while useful to identify a chip, is actually an
aggregate of two distinct fields named "architecture" and
"implementation".
- The "architecture" field is split, with its MSB being at a different
location than the rest o
Hi everyone,
Second revision of this continuation of my previous RFCs [1] to complete
the first step of GSP booting (running the FWSEC-FRTS firmware extracted
from the BIOS) on Ampere devices. Thanks for all the feedback on the
first version.
While this series is still far from bringing the GPU i
We will commonly need to compare chipset versions, so derive the
ordering traits to make that possible. Also derive Copy and Clone since
passing Chipset by value will be more efficient than by reference.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/gpu.rs | 2 +-
1 file changed, 1
We will use this error in the nova-core driver.
Signed-off-by: Alexandre Courbot
---
rust/kernel/error.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/rust/kernel/error.rs b/rust/kernel/error.rs
index
3dee3139fcd4379b94748c0ba1965f4e1865b633..083c7b068cf4e185100de96e520c54437898ee72
100
FWSEC-FRTS is run with the desired address of the FRTS region as
parameter, which we need to compute depending on some hardware
parameters.
Do this in a `FbLayout` structure, that will be later extended to
describe more memory regions used to boot the GSP.
Signed-off-by: Alexandre Courbot
---
d
From: Joel Fernandes
Add support for navigating and setting up vBIOS ucode data required for
GSP to boot. The main data extracted from the vBIOS is the FWSEC-FRTS
firmware which runs on the GSP processor. This firmware runs in high
secure mode, and sets up the WPR2 (Write protected region) before
Add the common Falcon code and HAL for Ampere GPUs, and instantiate the
GSP and SEC2 Falcons that will be required to boot the GSP.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/falcon.rs | 546 ++
drivers/gpu/nova-core/falcon/gsp.rs | 25
FWSEC-FRTS is the first firmware we need to run on the GSP falcon in
order to initiate the GSP boot process. Introduce the structure that
describes it.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/firmware.rs | 43 +++
1 file changed, 43 insertio
Since we will need to allocate lots of distinct memory chunks to be
shared between GPU and CPU, introduce a type dedicated to that. It is a
light wrapper around CoherentAllocation.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/dma.rs | 60 ++
Upon reset, the GPU executes the GFW_BOOT firmware in order to
initialize its base parameters such as clocks. The driver must ensure
that this step is completed before using the hardware.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/devinit.rs | 43 +++
With all the required pieces in place, load FWSEC-FRTS onto the GSP
falcon, run it, and check that it completed successfully by carving out
the WPR2 region out of framebuffer memory.
Signed-off-by: Alexandre Courbot
---
drivers/gpu/nova-core/falcon.rs | 3 ---
drivers/gpu/nova-core/gpu.rs|
Casting through a "void *" isn't sufficient to convince the randstruct
GCC plugin that the result is intentional. Instead operate through an
explicit union to silence the warning:
drivers/gpu/drm/ttm/ttm_backup.c: In function 'ttm_file_to_backup':
drivers/gpu/drm/ttm/ttm_backup.c:21:16: note: rand
From: Mario Limonciello
commit 2965e6355dcd ("drm/amd: Add Suspend/Hibernate notification
callback support") introduced a VRAM eviction earlier in the PM
sequences when swap was still available for evicting to. This helped
to fix a number of memory pressure related bugs but also exposed a
new one
From: Mario Limonciello
Suspend and hibernate notifications are available specifically when
the sequence starts and finishes. However there are no notifications
during the process when tasks have been frozen.
Introduce two new events `PM_SUSPEND_POST_FREEZE` and
`PM_HIBERNATE_POST_FREEZE` that
From: Mario Limonciello
As part of the suspend and hibernate sequences devices supported
by amdgpu will have VRAM evicted. This has been littered with problems
in the past, and now it is called strategically at multiple times
during power management sequences.
Most recently there were a number
There is a chance that obj->dma_buf would be NULL by the time
virtgpu_dma_buf_free_obj() is called. This can happen for imported
prime objects, when drm_gem_object_exported_dma_buf_free() gets
called on them before drm_gem_object_free(). This is because
drm_gem_object_exported_dma_buf_free() explic
On Wed, Apr 30, 2025 at 3:53 PM David Lechner wrote:
>
> On 4/30/25 8:17 AM, Josef Lusticky wrote:
> > The driver supports 3.5" Kingway HW-035P0Z002 display found
> > on Braiins Mini Miner BMM 101 product.
> >
> > Signed-off-by: Josef Lusticky
> > ---
>
> I haven't really looked at the patch yet,
On 5/1/2025 5:02 PM, Alexandre Courbot wrote:
> On Fri May 2, 2025 at 12:19 AM JST, Timur Tabi wrote:
>> On Thu, 2025-05-01 at 21:58 +0900, Alexandre Courbot wrote:
>>
>>
>>> +impl UsizeAlign for usize {
>>> + fn align_up(mut self, align: usize) -> usize {
>>> + self = (self + align -
On Thu, May 01, 2025 at 12:59:03PM -0700, Kees Cook wrote:
> Casting through a "void *" isn't sufficient to convince the randstruct
> GCC plugin that the result is intentional. Instead operate through an
> explicit union to silence the warning:
>
> drivers/gpu/drm/ttm/ttm_backup.c: In function 'tt
From: Michael Kelley
Current deferred I/O code works only for framebuffer memory that is
allocated with vmalloc(). The code assumes that the underlying page
refcount can be used by the mm subsystem to manage each framebuffer
page's lifecycle, which is consistent with vmalloc'ed memory, but not
wi
From: Michael Kelley
Current defio code works only for framebuffer memory that is allocated
with vmalloc(). The code assumes that the underlying page refcount can
be used by the mm subsystem to manage each framebuffer page's lifecycle,
including freeing the page if the refcount goes to 0. This ap
From: Michael Kelley
Export vmf_insert_mixed_mkwrite() for use by fbdev deferred I/O code,
which can be built as a module.
Commit cd1e0dac3a3e ("mm: unexport vmf_insert_mixed_mkwrite") is
effectively reverted.
Signed-off-by: Michael Kelley
---
Changes in v2:
* Exported as GPL symbol [Christoph
From: Michael Kelley
Framebuffer memory allocated using alloc_pages() was added to hyperv_fb in
commit 3a6fb6c4255c ("video: hyperv: hyperv_fb: Use physical memory for fb
on HyperV Gen 1 VMs.") in kernel version 5.6. But mmap'ing such
framebuffers into user space has never worked due to limitatio
On Fri, May 02, 2025 at 03:34:47AM +0100, Al Viro wrote:
> On Thu, May 01, 2025 at 07:13:12PM -0700, Matthew Brost wrote:
> > On Thu, May 01, 2025 at 05:24:38PM -0700, Kees Cook wrote:
> > > Casting through a "void *" isn't sufficient to convince the randstruct
> > > GCC plugin that the result is i
On Thu, May 01, 2025 at 09:26:25PM -0700, Matthew Brost wrote:
> I;m fairly certain is just aliasing... but I do understand a file cannot
> be embedded. Would comment help here indicating no other fields should
> be added to ttm_backup without struct file be converted to pointer or
> that just to
On Fri, May 02, 2025 at 05:31:49AM +0100, Al Viro wrote:
> On Thu, May 01, 2025 at 09:26:25PM -0700, Matthew Brost wrote:
>
> > I;m fairly certain is just aliasing... but I do understand a file cannot
> > be embedded. Would comment help here indicating no other fields should
> > be added to ttm_ba
On Thu, May 01, 2025 at 07:13:12PM -0700, Matthew Brost wrote:
> On Thu, May 01, 2025 at 05:24:38PM -0700, Kees Cook wrote:
> > Casting through a "void *" isn't sufficient to convince the randstruct
> > GCC plugin that the result is intentional. Instead operate through an
> > explicit union to sile
On Thu, May 01, 2025 at 07:13:12PM -0700, Matthew Brost wrote:
> On Thu, May 01, 2025 at 05:24:38PM -0700, Kees Cook wrote:
> > Casting through a "void *" isn't sufficient to convince the randstruct
> > GCC plugin that the result is intentional. Instead operate through an
> > explicit union to sile
On Fri, May 02, 2025 at 03:34:47AM +0100, Al Viro wrote:
> On Thu, May 01, 2025 at 07:13:12PM -0700, Matthew Brost wrote:
> > On Thu, May 01, 2025 at 05:24:38PM -0700, Kees Cook wrote:
> > > Casting through a "void *" isn't sufficient to convince the randstruct
> > > GCC plugin that the result is i
Hi Dave and Sima,
Here are the drm-xe fixes for 6.15-rc5.
The commit touching drm/gpusvm was wrongly pushed to drm-xe rather than
drm-misc, but the fix is good and would otherwise be missed in drm-misc.
So I'm propagating it through our fixes branch.
drm-xe-fixes-2025-05-01:
Driver Changes:
- E
Hi,
On Thu, May 1, 2025 at 12:48 AM wrote:
>
> From: Max Krummenacher
>
> The bridge driver currently disables handling the hot plug input and
> relies on a always connected eDP panel with fixed delays when the
> panel is ready.
Not entirely correct. In some cases we don't have fixed delays and
From: Dave Airlie
This adds the memcg object for any user allocated object,
and adds account_op to necessary paths which might populate
a tt object.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 2 ++
drive
From: Dave Airlie
Doing proper integration of TTM system memory allocations with
memcg is a difficult ask, primarily due to difficulties around
accounting for evictions properly.
However there are systems where userspace will be allocating
objects in system memory and they won't be prone to migr
From: Dave Airlie
Discrete and Integrated GPUs can use system RAM instead of
VRAM for all or some allocations. These allocations happen
via drm/ttm subsystem and are currently not accounted for
in cgroups.
Add a gpu statistic to allow a place to visualise allocations
once they are supported.
Si
From: Dave Airlie
As per the socket hooks, just adds two APIs to charge GPU pages
to the memcg and uncharge them.
Suggested by Waiman.
Signed-off-by: Dave Airlie
---
include/linux/memcontrol.h | 5 +
mm/memcontrol.c| 34 ++
2 files changed, 39
Hey all,
This is my second attempt at adding the initial simple memcg/ttm
integration.
This varies from the first attempt in two major ways:
1. Instead of using __GFP_ACCOUNT and direct calling kmem charges
for pool memory, and directly hitting the GPU statistic, Waiman
suggested I just do what
From: Dave Airlie
This just adds the memcg init and account_op support.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/nouveau/nouveau_bo.c | 1 +
drivers/gpu/drm/nouveau/nouveau_gem.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c
b/drivers/gpu/d
On 4/18/2025 12:50 AM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Add DPU driver support for the Qualcomm SAR2130P platform. It is mostly
the same as SM8550, minor differences in the CDP configuration.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
.../drm/msm/di
1 - 100 of 103 matches
Mail list logo
