On 12/02/2025 08:12, Yongxing Mou wrote:
> We need to enable mst for qcs8300, dp0 controller will support 2 streams
> output. So not reuse sm8650 dp controller driver and will add a new driver
> patch for qcs8300 mst feature. Modify the corresponding dt-bingding file
> to compatible with the qcs830
On 12/02/2025 08:12, Yongxing Mou wrote:
> Support mst for qcs8300 and add the stream 1 clock support in the mdss
> dt-bindings.
>
> Signed-off-by: Yongxing Mou
Your patchset leads to warnings - it is non-bisectable.
Fix original code, don't post buggy patches just to fix them immediately.
>
From: Andy Yan
VOP2 on rk3576:
Three video ports:
VP0 Max 4096x2160
VP1 Max 2560x1600
VP2 Max 1920x1080
2 4K Cluster windows with AFBC/RFBC, line RGB and YUV
4 Esmart windows with line RGB/YUV support:
Esmart0/1: 4K
Esmart2/3: 2k, or worked together as a single 4K plane at shared
line buffer mod
From: Andy Yan
This help avoid "exceeds 100 columns" warning from checkpatch
Signed-off-by: Andy Yan
---
(no changes since v1)
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
d
From: Andy Yan
In the upcoming VOP for rk3576, every VP has it's own LAYER_SEL
register, and the configuration value of each VP for the same
window maybe different, so extend the layer_sel_id to array,
let it can descption the layer select configuration value for
different VP.
Signed-off-by: And
From: Andy Yan
Add vop found on rk3576, the main difference between rk3576 and the
previous vop is that each VP has its own interrupt line.
Signed-off-by: Andy Yan
Reviewed-by: Krzysztof Kozlowski
---
(no changes since v13)
Changes in v13:
- Use maxItems constraint for clocks in allOf block
Hi Dave, Sima,
here's the first PR from drm-misc-next for what will become Linux v6.15.
Most of the changes contain small improvements, fixes and feature additions
to existing drivers. Qaic got support for AIC200 accelerators, mgag200 now
support the new G220eH5 chips, and there's the usual long
On 12/02/2025 08:12, Yongxing Mou wrote:
> This series of patches introduces how to enable MST functionality on
> the qcs8300 platform. The qcs8300 platform uses dpu_8_4 hardware, which
> is the same as the sa8775p, but it only has one DPU. So it only has one
> DP0 controller, supporting 4-stream M
On Wed, Feb 12, 2025 at 12:48:01PM +0530, Akhil P Oommen wrote:
> On 2/12/2025 5:30 AM, Dmitry Baryshkov wrote:
> > On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
> >> On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
> >>> On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote:
On Tue, Feb 11, 2025 at 07:59:19PM -0800, Jessica Zhang wrote:
> Disable pingpong dither in dpu_encoder_helper_phys_cleanup().
>
> This avoids the issue where an encoder unknowingly uses dither after
> reserving a pingpong block that was previously bound to an encoder that
> had enabled dither.
>
Hi,
Thank you for your patches and sorry for being slow to respond.
On 24-Jan-25 9:46 PM, John Edwards wrote:
> From: Andrew Wyatt
>
> The AYA NEO Flip DS and KB both use a 1080x1920 portrait LCD panel. The
> Flip DS additionally uses a 640x960 portrait LCD panel as a second display.
>
> Add
On 12/02/2025 10:49, Maxime Ripard wrote:
> On Wed, Feb 12, 2025 at 10:29:32AM +, Florent Tomasin wrote:
>>
>>
>> On 12/02/2025 10:01, Maxime Ripard wrote:
>>> On Wed, Feb 12, 2025 at 09:49:56AM +, Florent Tomasin wrote:
Note that the CMA patches were initially shared to help reprod
On Wed, Feb 12, 2025 at 09:58:40AM +0200, Svyatoslav Ryhel wrote:
> Add schema and add support for lm3533 mfd to use device
> tree bindings.
Thank you! I'm going to review the series this week, I definitely have
the comments. Stay tuned.
--
With Best Regards,
Andy Shevchenko
On Tue, 2025-02-11 at 12:14 +0100, Philipp Stanner wrote:
> drm_sched_init() has a great many parameters and upcoming new
> functionality for the scheduler might add even more. Generally, the
> great number of parameters reduces readability and has already caused
> one missnaming, addressed in:
>
Hi Andy,
Am Mittwoch, 12. Februar 2025, 10:34:57 MEZ schrieb Andy Yan:
> From: Andy Yan
>
> This help avoid "exceeds 100 columns" warning from checkpatch
>
> Signed-off-by: Andy Yan
I'm not much of a fan of "randomly" renaming individual constants
(especially when one is now named OFFS, while
Hi
Am 12.02.25 um 11:51 schrieb Hans de Goede:
Hi Thomas,
On 11-Feb-25 2:55 PM, Thomas Zimmermann wrote:
Hi
Am 24.01.25 um 21:46 schrieb John Edwards:
Hello.
I am submitting a small number of patches to add panel rotation quirks for
a few handheld gaming PCs. These patches were created by
Hi,
On 12-Feb-25 12:11 PM, Thomas Zimmermann wrote:
> Hi
>
> Am 12.02.25 um 11:51 schrieb Hans de Goede:
>> Hi Thomas,
>>
>> On 11-Feb-25 2:55 PM, Thomas Zimmermann wrote:
>>> Hi
>>>
>>> Am 24.01.25 um 21:46 schrieb John Edwards:
Hello.
I am submitting a small number of patches to
we reuse it. BTW, for dp phy hardware
version, qcs8300 and sm8650 is different.
For this patch series,
https://lore.kernel.org/all/20250212-mst_qcs8300-v1-0-38a8aa083...@quicinc.com/
, it is made on top of
https://lore.kernel.org/all/20241205-dp_mst-v1-0-f8618d42a...@quicinc.com/
which is a new
The I2C driver gets an interrupt upon transfer completion.
When handling multiple messages in a single transfer, this
results in N interrupts for N messages, leading to significant
software interrupt latency.
To mitigate this latency, utilize Block Event Interrupt (BEI)
mechanism. Enabling BEI ins
Hi Andi,
On 2025-02-10 at 14:01:19 GMT, Andi Shyti wrote:
> Hi Janusz,
>
> On Thu, Feb 06, 2025 at 07:07:38PM +0100, Janusz Krzysztofik wrote:
> > We return immediately from i915_driver_register() if drm_dev_register()
> > fails, skipping remaining registration steps. However, the _unregister()
GSI hardware generates an interrupt for each transfer completion.
For multiple messages within a single transfer, this results in
N interrupts for N messages, leading to significant software
interrupt latency.
To mitigate this latency, utilize Block Event Interrupt (BEI) mechanism.
Enabling BEI in
The I2C driver gets an interrupt upon transfer completion.
When handling multiple messages in a single transfer, this
results in N interrupts for N messages, leading to significant
software interrupt latency.
To mitigate this latency, utilize Block Event Interrupt (BEI)
mechanism. Enabling BEI ins
On Wed, 12 Feb 2025 at 12:54, Krzysztof Kozlowski wrote:
>
> On 12/02/2025 11:41, Dmitry Baryshkov wrote:
> > On Wed, Feb 12, 2025 at 03:12:24PM +0800, Yongxing Mou wrote:
> >> We need to enable mst for qcs8300, dp0 controller will support 2 streams
> >> output. So not reuse sm8650 dp controller d
On 12.02.2025 12:53 AM, Dmitry Baryshkov wrote:
> On Tue, Feb 11, 2025 at 02:31:14PM +0100, Konrad Dybcio wrote:
>> On 3.02.2025 7:14 PM, Danila Tikhonov wrote:
>>> From: Eugene Lepshy
>>>
>>> Enable the Adreno GPU and configure the Visionox RM692E5 panel.
>>>
>>> Signed-off-by: Eugene Lepshy
>>>
On 12/02/2025 10:40, Philipp Stanner wrote:
On Wed, 2025-02-12 at 09:32 +, Tvrtko Ursulin wrote:
On 12/02/2025 09:02, Philipp Stanner wrote:
On Fri, 2025-02-07 at 14:50 +, Tvrtko Ursulin wrote:
Idea is to add helpers for peeking and popping jobs from entities
with
the goal of decoup
On 2025-02-11 21:06:19, Danila Tikhonov wrote:
> On 2/9/25 01:09, Marijn Suijten wrote:
> > On 2025-02-03 21:14:26, Danila Tikhonov wrote:
> >> From: Eugene Lepshy
> >>
> >> DRM DSC helper has parameters for various bpc values other than 8:
> > Weird zero-width \u200b spaces here between "values
Hi,
here's a complaint about the lack of process and documentation in
accel/, and ivpu specifically. I came across this series while preparing
the weekly PR for drm-misc-next and found myself unable to extract much
useful information to report. This is a problem for a development
process that
From: Andy Yan
The clock polarity of RGB signal output is controlled by GRF, this
property is already being used in the current device tree, but
forgot to describe it as a required property in the binding file.
Signed-off-by: Andy Yan
Acked-by: Krzysztof Kozlowski
---
(no changes since v13)
On Thu, 23 Jan 2025, Simona Vetter wrote:
> On Wed, Jan 22, 2025 at 04:41:32PM +0200, Jani Nikula wrote:
>> Add CONFIG_DRM_HEADER_TEST to ensure drm headers are self-contained and
>> pass kernel-doc. And for starters, fix one header that this catches.
>>
>> Jani Nikula (2):
>> drm/client: inclu
On 12/02/2025 10:01, Maxime Ripard wrote:
> On Wed, Feb 12, 2025 at 09:49:56AM +, Florent Tomasin wrote:
>> Note that the CMA patches were initially shared to help reproduce my
>> environment of development, I can isolate them in a separate patch
>> series and include a reference or "base-co
On Wed, 12 Feb 2025, Egor Vorontsov wrote:
> Some newer high refresh rate consumer monitors (including those by Samsung)
> make use of DisplayID 2.1 timing blocks in their EDID data, notably for
> their highest refresh rate modes. Such modes won't be available as of now.
>
> Implement partial supp
From: Andy Yan
The Cluster windows of upcoming VOP on rk3576 also support
linear YUV support, we need to set uv swap bit for it.
As the VOP2_WIN_UV_SWA register defined on rk3568/rk3588 is
0x, so this register will not be touched on these
two platforms.
Signed-off-by: Andy Yan
Tested-b
From: Andy Yan
The VOP interface mux, overlay, background delay cycle configuration
of different SOC are much different. Add platform specific callback
ops to let the core driver look cleaner and more refined.
Signed-off-by: Andy Yan
Tested-by: Michael Riesch # on RK3568
Tested-by: Detlev Casa
From: Andy Yan
In the upcoming VOP of rk3576, a Window cannot attach to all Video Ports,
so make sure all VP find it's suitable primary plane, then register the
remain windows as overlay plane will make code easier.
Signed-off-by: Andy Yan
Tested-by: Michael Riesch # on RK3568
Tested-by: Detle
From: Andy Yan
PATCH 1~9 are preparations for rk3576 support
PATCH 10~13 are real support for rk376
I test it with a 1080P/4K HDMI output with modetest and weston
output.
If there are some one want to have a try, I have a tree based on
Linux 6.14-rc1 here[0]
[0]https://github.com/andyshrk/lin
From: Andy Yan
In the upcoming VOP of rk3576, a window cannot attach to all Video
Ports, we introduce a possible_vp_mask for every window to indicate
which Video Ports this window can attach to.
Signed-off-by: Andy Yan
Tested-by: Michael Riesch # on RK3568
Tested-by: Detlev Casanova
---
(no
From: Andy Yan
As more SoCs variants are introduced, each SoC brings its own
unique set of constraints, describe this constraints SoC by
SoC will make things easier.
Signed-off-by: Andy Yan
Reviewed-by: Krzysztof Kozlowski
---
Changes in v14:
- Set maxItems constraint of clocks for rk3588 to
From: Andy Yan
There is a version number hardcoded in the VOP VERSION_INFO
register, and the version number increments sequentially based
on the production order of the SOC.
So using this version number to distinguish different VOP features
will simplify the code.
Signed-off-by: Andy Yan
Teste
From: Heiko Stuebner
Right now vop2_cluster_init() copies the base vop2_cluster_regs
and adapts the reg value with the current window's offset before
adding the fields to the regmap.
This conflicts with the notion of reg_fields being const, see
https://lore.kernel.org/all/20240706-regmap-const-s
On Fri, 2025-02-07 at 14:50 +, Tvrtko Ursulin wrote:
> Idea is to add helpers for peeking and popping jobs from entities
> with
> the goal of decoupling the hidden assumption in the code that
> queue_node
> is the first element in struct drm_sched_job.
>
> That assumption usually comes in the
-Wflex-array-member-not-at-end was introduced in GCC-14, and we are
getting ready to enable it, globally.
So, in order to avoid ending up with flexible-array members in the
middle of other structs, we use the `struct_group_tagged()` helper
to separate the flexible arrays from the rest of the membe
btw. I still believe that it would be helpful (and congruent with the
established norm) to have the version in all patch titles. I do use
threaded view, but inboxes are huge, and everything that helps you
orient yourself is welcome
On Fri, 2025-02-07 at 14:51 +, Tvrtko Ursulin wrote:
> Helper
On Wed, 2025-02-12 at 12:30 +, Tvrtko Ursulin wrote:
>
> On 12/02/2025 10:40, Philipp Stanner wrote:
> > On Wed, 2025-02-12 at 09:32 +, Tvrtko Ursulin wrote:
> > >
> > > On 12/02/2025 09:02, Philipp Stanner wrote:
> > > > On Fri, 2025-02-07 at 14:50 +, Tvrtko Ursulin wrote:
> > > > >
On Fri, 2025-02-07 at 13:36 +0100, Philipp Stanner wrote:
> Changes in v3:
> - timedout_job(): various docu wording improvements. (Danilo)
> - Use the term "ring" consistently. (Danilo)
> - Add fully fledged docu for enum drm_gpu_sched_stat. (Danilo)
>
> Changes in v2:
> - Document what ru
Le 11/02/2025 à 11:43, José Expósito a écrit :
On Thu, Jan 30, 2025 at 02:48:19PM +0100, Louis Chauvet wrote:
On 29/01/25 - 12:00, José Expósito wrote:
Add a list of planes to vkms_config and create as many planes as
configured during output initialization.
For backwards compatibility, add
Le 11/02/2025 à 11:47, José Expósito a écrit :
On Thu, Jan 30, 2025 at 02:48:21PM +0100, Louis Chauvet wrote:
On 29/01/25 - 12:00, José Expósito wrote:
Add a list of possible CRTCs to the plane configuration and helpers to
attach, detach and get the primary and cursor planes attached to a CR
Allow user to provide a low latency hint. When set, KMD sends a hint
to GuC which results in special handling for that process. SLPC will
ramp the GT frequency aggressively every time it switches to this
process.
We need to enable the use of SLPC Compute strategy during init, but
it will apply onl
Hi,
Thanks for your detailed feedback and constructive suggestions. I appreciate
this as it is not easy to learn all process details otherwise.
On 2/12/2025 11:20 AM, Thomas Zimmermann wrote:
> Hi,
>
> here's a complaint about the lack of process and documentation in accel/, and
> ivpu specifi
On 12.02.2025 12:28 PM, Krzysztof Kozlowski wrote:
> On 12/02/2025 12:13, Yongxing Mou wrote:
>>
>>
>> On 2025/2/12 16:35, Krzysztof Kozlowski wrote:
>>> On 12/02/2025 08:12, Yongxing Mou wrote:
We need to enable mst for qcs8300, dp0 controller will support 2 streams
output. So not reuse
Le 11/02/2025 à 11:44, José Expósito a écrit :
On Thu, Jan 30, 2025 at 02:48:20PM +0100, Louis Chauvet wrote:
On 29/01/25 - 12:00, José Expósito wrote:
Add a list of CRTCs to vkms_config and helper functions to add and
remove as many CRTCs as wanted.
For backwards compatibility, add one CRT
Le 12/02/2025 à 09:53, Thomas Zimmermann a écrit :
Am 12.02.25 um 09:49 schrieb José Expósito:
If the driver initialization fails, the vkms_exit() function might
access an uninitialized or freed default_config pointer and it might
double free it.
Fix both possible errors by initializing de
Hello Jerome,
On Tue Feb 11, 2025 at 6:28 PM CET, Jerome Brunet wrote:
> The auxiliary device creation of this driver is simple enough to
> use the available auxiliary device creation helper.
>
> Use it and remove some boilerplate code.
>
> Signed-off-by: Jerome Brunet
Tested the series, it work
On 12.02.2025 3:35 PM, Rob Herring wrote:
> On Wed, Feb 12, 2025 at 03:12:23PM +0800, Yongxing Mou wrote:
>> This series of patches introduces how to enable MST functionality on
>> the qcs8300 platform. The qcs8300 platform uses dpu_8_4 hardware, which
>> is the same as the sa8775p, but it only has
Hello Jerome,
Why the " - take 2" in the commit first line?
Thanks,
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Acked-by: Alex Deucher for the series.
On Thu, Feb 6, 2025 at 5:37 PM Harry Wentland wrote:
>
>
>
> On 2025-01-27 14:59, André Almeida wrote:
> > amdgpu can handle async flips on overlay planes, so allow it for atomic
> > async checks.
> >
> > Signed-off-by: André Almeida
>
> Reviewed-by: Harry
Add support for Y8 and Y10_LE32 formats. We also need to add new csc
matrices for the y-only formats.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_di
Add support for X403 format.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index c820df97aa28..7495e42677a6 100644
--- a/drivers/gpu/drm/xlnx/z
Add support for XVUY2101010 format.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 7495e42677a6..859ee050a668 100644
--- a/drivers/gpu/drm
Add support for XV15 & XV20 formats.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 3d4ade571f0f..32031f52e114 100644
--- a/drivers
Add XVUY2101010, a 10 bits per component YCbCr format in a 32 bit
container.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
inde
Add new DRM pixel formats and add support for those in the Xilinx zynqmp
display driver.
All other formats except XVUY2101010 are already supported in upstream
gstreamer, but gstreamer's kmssink does not have the support yet, as it
obviously cannot support the formats without kernel having the for
drm_format_info_bpp() cannot be used for formats which do not have an
integer bits-per-pixel in a pixel block.
E.g. DRM_FORMAT_XV15's (not yet in upstream) plane 0 has three 10-bit
pixels (Y components), and two padding bits, in a 4 byte block. That is
10.666... bits per pixel when considering the
Add greyscale Y8 format.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index bb0a2294573b..c8c6dd8a8d4a 100644
--- a/drivers/
Add Y10_P32, a 10 bit greyscale format, with 3 pixels packed into
32-bit container.
The fourcc for the format is 'YPA4', which comes from Y - Y only, P -
packed, A - 10 (as in 0xA), 4 - 4 bytes.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 4
include/uapi/drm/drm_fourc
On 12-02-2025 13:02, Borah, Chaitanya Kumar wrote:
-Original Message-
From: Murthy, Arun R
Sent: Wednesday, February 5, 2025 3:57 PM
To:dri-devel@lists.freedesktop.org;intel-...@lists.freedesktop.org; intel-
x...@lists.freedesktop.org
Cc: Borah, Chaitanya Kumar; Syrjala,
Ville; Murthy, Ar
On 2/12/2025 5:35 PM, Jyothi Kumar Seerapu wrote:
GSI hardware generates an interrupt for each transfer completion.
For multiple messages within a single transfer, this results in
N interrupts for N messages, leading to significant software
interrupt latency.
To mitigate this latency, utilize
On 2/12/2025 5:35 PM, Jyothi Kumar Seerapu wrote:
The I2C driver gets an interrupt upon transfer completion.
When handling multiple messages in a single transfer, this
results in N interrupts for N messages, leading to significant
software interrupt latency.
To mitigate this latency, utilize
Add X403, a 3 plane non-subsampled YCbCr format.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/drm_fourcc.c | 4
include/uapi/drm/drm_fourcc.h | 8
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 155482d9a409..c
Userspace can pass damage area clips per plane to track
changes in a plane and some display components can utilze
these damage clips for efficiently handling use cases like
FBC, PSR etc. A merged damage area is generated and its
coordinates are updated relative to viewport and HW and
stored in the
Register definitions for FBC dirty rect support
Bspec: 71675, 73424
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
b/drivers/gpu/drm/i915/display/inte
Dirty rect support for FBC in xe3 onwards based on the comments after the
initial RFC series.
v2: Dirty rect related compute and storage moved to fbc state (Ville)
V3: Dont call fbc activate if FBC is already active
v4: Dirty rect compute and programming moved within DSB scope
New changes ar
If FBC is already active, we don't need to call FBC activate
routine again. This is more relevant in case of dirty rect
support in FBC. Xe doesn't support legacy fences. Hence fence
programming also not required as part of this fbc_hw_activate.
Any FBC related register updates done after enabling t
It is not recommended to have both FBC dirty rect and PSR2
selective fetch be enabled at the same time. If PSR2 selective
fetch or panel replay is on, mark FBC as not possible.
v2: fix the condition to disable FBC if PSR2 enabled (Jani)
v3: use HAS_FBC_DIRTY_RECT()
Bspec: 68881
Signed-off-by: Vi
Dirty rectangle feature allows FBC to recompress a subsection
of a frame. When this feature is enabled, display will read
the scan lines between dirty rectangle start line and dirty
rectangle end line in subsequent frames.
Use the merged damage clip stored in the plane state to
configure the FBC d
Introduce a macro to check if the platform supports FBC dirty
rect capability.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i91
On Wed, Feb 12, 2025 at 11:20:46AM +0100, Thomas Zimmermann wrote:
> Hi,
>
> here's a complaint about the lack of process and documentation in accel/,
> and ivpu specifically. I came across this series while preparing the weekly
> PR for drm-misc-next and found myself unable to extract much useful
Add a const qualifier for the "state" parameter as well as we could
use this helper to get the combined damage in cases of const
drm_plane_state as well. Needed mainly for xe driver big joiner cases
where we need to track the damage from immutable plane state.
Signed-off-by: Vinod Govindapillai
-
Hi Stefan,
On 10/02/25 10:27, Stefan Wahren wrote:
Hi Maíra,
Am 10.02.25 um 13:23 schrieb Maíra Canal:
Hi Stefan,
Thanks for your patch!
On 01/02/25 09:50, Stefan Wahren wrote:
Since the initial commit 57692c94dcbe ("drm/v3d: Introduce a new DRM
driver
for Broadcom V3D V3.x+") the struct v3
> … This patch changes its return type …
See also:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.14-rc2#n94
> Signed-off-by: Wentao Liang
How good does such an email address fit to the Developer's Certificate of
Origi
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Wednesday, January 29, 2025 11:51 PM
> To: Usyskin, Alexander
> Cc: Miquel Raynal ; Richard Weinberger
> ; Vignesh Raghavendra ; De Marchi,
> Lucas ; Thomas Hellström
> ; Maarten Lankhorst
> ; Maxime Ripard
> ; Thomas Zimmermann ;
> David
Hi Boris,
Here are the branch and kernel config I used for reproducing the bug:
https://gitlab.freedesktop.org/larumbe/drm-misc/-/tree/panthor-fdinfo-internalbosizes-10
https://gitlab.collabora.com/-/snippets/426
On 11.02.2025 13:41, Boris Brezillon wrote:
> On Tue, 11 Feb 2025 11:39:49 +
>
On Mon, Feb 10, 2025 at 8:14 PM Jocelyn Falempe wrote:
>
> On 09/02/2025 18:45, Dmitry Osipenko wrote:
> > On 2/6/25 13:42, Ryosuke Yasuoka wrote:
> >> Virtio gpu supports the drm_panic module, which displays a message to
> >> the screen when a kernel panic occurs. It is supported where it has
> >
On Wed, Feb 12, 2025 at 03:12:23PM +0800, Yongxing Mou wrote:
> This series of patches introduces how to enable MST functionality on
> the qcs8300 platform. The qcs8300 platform uses dpu_8_4 hardware, which
> is the same as the sa8775p, but it only has one DPU. So it only has one
> DP0 controller,
Hi,
On Tue, Feb 11, 2025 at 2:16 PM Doug Anderson wrote:
>
> Hi,
>
> On Tue, Feb 4, 2025 at 7:01 AM Maxime Ripard wrote:
> >
> > @@ -374,12 +377,15 @@ static int __maybe_unused ti_sn65dsi86_resume(struct
> > device *dev)
> > * panel (including the aux channel) w/out any need for an inp
Use drm helpers, drm_format_info_plane_width(),
drm_format_info_plane_height() and drm_format_info_min_pitch() to
calculate sizes for the DMA.
This cleans up the code, but also makes it possible to support more
complex formats (like XV15, XV20).
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm
The drm_writeback_cleanup_job() function frees "pos" so call
list_del(&pos->list_entry) first to avoid a use after free.
Fixes: 1914ba2b91ea ("drm: writeback: Create drmm variants for
drm_writeback_connector initialization")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/drm_writeback.c | 2 +
Hey,
I was hoping someone else would look at it, but it seems not.
This patch appears to work on my system, it would be helpful if I could
get the exact sequence failing to write a reproducer, but I don't want
to hold up a bugfix because of it.
Reviewed-by: Maarten Lankhorst
Should I send
If the driver initialization fails, the vkms_exit() function might
access an uninitialized or freed default_config pointer and it might
double free it.
Fix both possible errors by initializing default_config only when the
driver initialization succeeded.
Reported-by: Louis Chauvet
Link: https://
On 20/01/2025 04:49, Yongxing Mou wrote:
> Add compatible string for the DisplayPort controller found on the
> Qualcomm QCS8300 platform.QCS8300 only support one DisplayPort
> controller and have the same base offset with sm8650, so we reuse
> the sm8650 DisplayPort driver.
>
> Reviewed-by: Krzysz
On 20/01/2025 04:49, Yongxing Mou wrote:
> Document the MDSS hardware found on the Qualcomm QCS8300 platform.
> QCS8300 use the same DPU hardware version as SA8775P, so we reuse it's
> driver. But QCS8300 only have one DP controller, and offset is same with
> sm8650, so dp controller reuse the sm86
Hi Thomas,
On Tue, Feb 11, 2025 at 03:33:55PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 11.02.25 um 12:08 schrieb José Expósito:
> > If the driver initialization fails, the vkms_exit() function might
> > access an uninitialized or freed default_config pointer and it might
> > double free it.
>
Am 12.02.25 um 09:49 schrieb José Expósito:
If the driver initialization fails, the vkms_exit() function might
access an uninitialized or freed default_config pointer and it might
double free it.
Fix both possible errors by initializing default_config only when the
driver initialization succe
Hi Nicolas and Krzysztof,
On 09/02/2025 11:56, Krzysztof Kozlowski wrote:
> On 06/02/2025 22:21, Nicolas Dufresne wrote:
>> Le mercredi 05 février 2025 à 10:13 +0100, Krzysztof Kozlowski a écrit :
>>> On 03/02/2025 16:31, Florent Tomasin wrote:
Hi Krzysztof
On 30/01/2025 13:25, Krzy
From: Andy Yan
Now these two function share the same logic, the can
be merged as one.
Signed-off-by: Andy Yan
---
(no changes since v1)
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 42 +---
1 file changed, 11 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/rock
Hi Nicolas,
On 04/02/2025 18:12, Nicolas Dufresne wrote:
> Hi Florent,
>
> Le lundi 03 février 2025 à 13:36 +, Florent Tomasin a écrit :
>>
>> On 30/01/2025 13:28, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Thu, Jan 30, 2025 at 01:08:57PM +, Florent Tomasin wrote:
Introduce a CMA Heap d
On 12/02/2025 09:02, Philipp Stanner wrote:
btw. I still believe that it would be helpful (and congruent with the
established norm) to have the version in all patch titles. I do use
threaded view, but inboxes are huge, and everything that helps you
orient yourself is welcome
On Fri, 2025-02-07
The XLCDC IP supports parallel RGB, MIPI DSI and LVDS Display.
The LCD Generic clock (sys_clk) is used for Parallel RGB and MIPI
displays, while the LVDS PLL clock (lvds_pll_clk) is used for LVDS
displays.Since both the clocks cannot co-exist together in the DT
for a given display, this patch first
From: Dharma Balasubiramani
Add support for encoder type "DRM_MODE_ENCODER_LVDS" with the following
bus formats:
- RGB888_1X7X4_SPWG
- RGB888_1X7X4_JEIDA
- RGB666_1X7X3_SPWG
- RGB666_1X18
Signed-off-by: Dharma Balasubiramani
[manikanda...@microchip.com: move modi
From: Dharma Balasubiramani
The LVDS PLL clock runs at 7 times the panel pixel clock.
For LVDS displays, the PLL clock rate is set based on the
panel pixel clock, eliminating the need for the assigned-clock-rates
Device Tree property for lvds_pll_clk in the LCD node.
Signed-off-by: Dharma Balasu
On Wed, Feb 12, 2025 at 02:55:10AM +0200, Dmitry Baryshkov wrote:
> On Tue, Feb 11, 2025 at 09:48:31AM +0100, Maxime Ripard wrote:
> > On Tue, Feb 11, 2025 at 01:14:28AM +0200, Dmitry Baryshkov wrote:
> > > On Mon, Feb 10, 2025 at 06:12:44PM +0100, Luca Ceresoli wrote:
> > > > Hi Maxime, Dmitry
> >
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