[PATCH v2 3/3] drm: atmel-hlcdc: set LVDS PLL clock rate for LVDS Displays

[Manikandan Muralidharan]

From: Dharma Balasubiramani <dharm...@microchip.com>

The LVDS PLL clock runs at 7 times the panel pixel clock.
For LVDS displays, the PLL clock rate is set based on the
panel pixel clock, eliminating the need for the assigned-clock-rates
Device Tree property for lvds_pll_clk in the LCD node.

Signed-off-by: Dharma Balasubiramani <dharm...@microchip.com>
Signed-off-by: Manikandan Muralidharan <manikanda...@microchip.com>
---
Changes in v2:
- Rephrase commit message and comment block
---
 .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c    | 48 ++++++++++++++++---
 1 file changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index 0e709047369a..cf4f9ccd81a4 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -99,9 +99,15 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc 
*c)
                drm_connector_list_iter_end(&iter);
        }
 
-       ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
-       if (ret)
-               return;
+       if (crtc->dc->hlcdc->lvds_pll_clk) {
+               ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk);
+               if (ret)
+                       return;
+       } else {
+               ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
+               if (ret)
+                       return;
+       }
 
        vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
        vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
@@ -186,7 +192,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc 
*c)
                           ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK),
                           cfg);
 
-       clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+       if (crtc->dc->hlcdc->lvds_pll_clk)
+               clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk);
+       else
+               clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
 }
 
 static enum drm_mode_status
@@ -242,7 +251,11 @@ static void atmel_hlcdc_crtc_atomic_disable(struct 
drm_crtc *c,
                                    10, 1000))
                dev_warn(dev->dev, "Atmel LCDC status register CLKSTS 
timeout\n");
 
-       clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+       if (crtc->dc->hlcdc->lvds_pll_clk)
+               clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk);
+       else
+               clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+
        pinctrl_pm_select_sleep_state(dev->dev);
 
        pm_runtime_allow(dev->dev);
@@ -255,15 +268,38 @@ static void atmel_hlcdc_crtc_atomic_enable(struct 
drm_crtc *c,
 {
        struct drm_device *dev = c->dev;
        struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
+       struct drm_display_mode *adj = &c->state->adjusted_mode;
        struct regmap *regmap = crtc->dc->hlcdc->regmap;
        unsigned int status;
+       int ret;
 
        pm_runtime_get_sync(dev->dev);
 
        pm_runtime_forbid(dev->dev);
 
        pinctrl_pm_select_default_state(dev->dev);
-       clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
+
+       if (crtc->dc->hlcdc->lvds_pll_clk) {
+               /*
+                * For LVDS displays, retrieve the pixel clock from the panel
+                * and set the LVDS PLL clock rate accordingly.
+                * According to the datasheet,the LVDS PLL clock is 7 times the 
pixel clock.
+                */
+               ret = clk_set_rate(crtc->dc->hlcdc->lvds_pll_clk,
+                                  (adj->clock * 7 * 1000));
+               if (ret) {
+                       dev_err(dev->dev, "Failed to set LVDS PLL clk rate: 
%d\n", ret);
+                       return;
+               }
+
+               ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk);
+               if (ret)
+                       return;
+       } else {
+               ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
+               if (ret)
+                       return;
+       }
 
        regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
        if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,
-- 
2.25.1