On Tue, Jul 02, 2024 at 03:02:22PM -0400, Rodrigo Vivi wrote:
> Hi Dave and Sima,
>
> Here goes our actual last PR towards 6.11.
> One extra to make the drm-xe-next-fixes smoother.
>
> Mostly with fixes that would be anyway part of the
> drm-xe-next-fixes, plus some more SRIOV preparation
> and a
The caching mode for buffer objects with VRAM as a possible
placement was forced to write-combined, regardless of placement.
However, write-combined system memory is expensive to allocate and
even though it is pooled, the pool is expensive to shrink, since
it involves global CPU TLB flushes.
More
Add check for the return value of spi_setup() and return the error
if it fails in order to catch the error.
Signed-off-by: Chen Ni
---
drivers/video/backlight/l4f00242t03.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/video/backlight/l4f00242t03.c
b/drivers/vi
Hi Stephen, thanks for reviewing.
On Thu, 4 Jul 2024, at 11:02 AM, Stephen Boyd wrote:
> Quoting Ryan Walklin (2024-07-03 03:51:09)
>> +#include
>
> What is this include for?
>
for writel, however have confirmed this should instead be #include ,
will correct for v3.
>> + if (of_device_is_
On Thu, 4 Jul 2024, at 3:38 AM, Conor Dooley wrote:
> I forgot to reply to, or somehow didn't notice your reply to my comments
> on this patch. I would just drop this change as I think it's a tooling
> issue. I checked the version of dt-schema etc that I have here locally
> and there were no compla
On Thu, 4 Jul 2024, at 3:28 AM, Conor Dooley wrote:
>> Add display engine bus, clock and mixer bindings for the DE33.
>>
>> Signed-off-by: Ryan Walklin
>
> Probably this should be 3 patches given 3 subsystems, but the content is
> Acked-by: Conor Dooley
>
> Cheers,
> Conor.
>
Thanks Conor, will
On Fri, Jul 05, 2024 at 04:38:34PM +0800, Chen Ni wrote:
> Add check for the return value of spi_setup() and return the error
> if it fails in order to catch the error.
>
> Signed-off-by: Chen Ni
> ---
> drivers/video/backlight/l4f00242t03.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletio
On Thu, Jul 04, 2024 at 03:14:50PM +0100, Florian Fainelli wrote:
> On 6/30/2024 4:36 PM, Stefan Wahren wrote:
> > On resume of the Raspberry Pi the dwc2 driver fails to enable
> > HCD_FLAG_HW_ACCESSIBLE before re-enabling the interrupts.
> > This causes a situation where both handler ignore a inco
Hi,
This patch series aims to add Freescale i.MX8qxp Display Controller support.
The controller is comprised of three main components that include a blit
engine for 2D graphics accelerations, display controller for display output
processing, as well as a command sequencer.
Previous patch series
Freescale i.MX8qxp Display Controller is implemented as construction set of
building blocks with unified concept and standardized interfaces.
Document some processing units to support two display outputs.
ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend processing units
are in pixel engin
i.MX8qxp Display Controller display engine consists of all processing units
that operate in a display clock domain.
Signed-off-by: Liu Ying
---
.../imx/fsl,imx8qxp-dc-display-engine.yaml| 166 ++
1 file changed, 166 insertions(+)
create mode 100644
Documentation/devicetree/
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain. Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.
Signed-off-by: Liu Ying
---
.../imx/fsl,imx8qxp-dc-
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.
Signed-off-by: Liu Ying
---
.../fsl,imx8qxp-dc-intc.yaml | 321 ++
1 file changed, 321 insertions(+)
create mode 100644
Documentation/devicetree
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer.
Signed-off-by: Liu Ying
---
.../bindings/display/imx/fsl,imx8qxp-dc.yaml | 243 ++
i.MX8qxp Display Controller display engine consists of all processing
units that operate in a display clock domain. Add minimal feature
support with FrameGen and TCon so that the engine can output display
timings. The display engine driver as a master binds FrameGen and
TCon drivers as components
i.MX8qxp Display Controller pixel engine consists of all processing
units that operate in the AXI bus clock domain. Add drivers for
ConstFrame, ExtDst, FetchLayer, FetchWarp and LayerBlend units, as
well as a pixel engine driver, so that two displays with primary
planes can be supported. The pixe
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit. Add driver for it.
Signed-off-by: Liu Ying
---
drivers/gpu/drm/imx/dc/Kconfig | 1 +
drivers/gpu/drm/imx/dc/Makefile | 2 +-
drivers/gpu/drm/imx/dc/dc-drv.c | 1 +
drivers
i.MX8qxp Display Controller(DC) is comprised of three main components that
include a blit engine for 2D graphics accelerations, display controller for
display output processing, as well as a command sequencer. Add kernel
mode setting support for the display controller part with two CRTCs and
two p
Add myself as the maintainer of i.MX8qxp Display Controller.
Signed-off-by: Liu Ying
---
MAINTAINERS | 19 +++
1 file changed, 19 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 35db18d26c11..29c9d52e74d1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7379,6 +7379,25
Many a times images are blurred or upscaled content is also not as
crisp as original rendered image. Traditional sharpening techniques often
apply a uniform level of enhancement across entire image, which sometimes
result in over-sharpening of some areas and potential loss of natural details.
In
As only second scaler can be used for sharpness check if it
is available and if panel fitting is also not enabled, the
set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Added the panel fitting check before enabling sharpness
Signed-off-by: Nemesa Garg
---
dr
Introduces the new crtc property "SHARPNESS_STRENGTH" that allows
the user to set the intensity so as to get the sharpness effect.
The value of this property can be set from 0-255.
It is useful in scenario when the output is blurry and user
want to sharpen the pixels. User can increase/decrease the
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all values and then dividing each value with a sum.
Add new registers and related bits. Compute the strength
value and tap value based on display mode.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
.../drm/i915/display/intel_display_types.h| 1 +
.../drm/i915/display/intel_sharpen_filter.c | 105 ++
Load the lut values during pipe enable.
v2: Add the display version check
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_crtc.c| 3 +++
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
drivers/gpu/drm/i915/display/skl_scaler.c| 13 -
3 files chan
In adreno_request_fw() when debugging information is printed to the log
after firmware load, an incorrect filename is printed. 'newname' is used
instead of 'fwname', so prefix "qcom/" is being added to filename.
Looks like "copy-paste" mistake.
Fix this mistake by replacing 'newname' with 'fwname'
On Fri, 5 Jul 2024 at 12:15, Aleksandr Mishin wrote:
>
> In adreno_request_fw() when debugging information is printed to the log
> after firmware load, an incorrect filename is printed. 'newname' is used
> instead of 'fwname', so prefix "qcom/" is being added to filename.
> Looks like "copy-paste"
On Wed, Jul 03, 2024 at 04:59:12PM +0900, Inki Dae wrote:
> Hi Dave and Daniel,
>
>Just three cleanup patches to Exynos Virtual Display driver
>for improved management.
>
> Please kindly let me know if there is any problem.
>
> Thanks,
> Inki Dae
>
>
> The following changes since co
On Fri, Jun 28, 2024 at 12:39:33PM +0200, Lucas Stach wrote:
> Hi Dave, hi Sima,
>
> please pull the following changes for the next merge window. Mostly
> fixes, but as they concern new hardware support there's no need to rush
> them into the current -rc.
>
> Regards,
> Lucas
>
> The following c
On Fri, Jun 28, 2024 at 01:46:32PM +, Chun-Kuang Hu wrote:
> Hi, Dave & Daniel:
>
> This includes:
>
> 1. Convert to platform remove callback returning void
> 2. Drop chain_mode_fixup call in mode_valid()
> 3. Fixes the errors of MediaTek display driver found by IGT.
> 4. Add display support
Add check for the return value of spi_setup() and return the error
if it fails in order to catch the error.
Signed-off-by: Chen Ni
---
Changelog:
v1 -> v2:
1. Use dev_err_probe() to match other error paths
---
drivers/video/backlight/l4f00242t03.c | 5 -
1 file changed, 4 insertions(+), 1
On 04/06/2024 15:18, Krzysztof Kozlowski wrote:
> On 27/05/2024 16:47, Alain Volmat wrote:
>> Hi Krzysztof,
>>
>> thanks for your patch, sorry for the delay.
>>
>> On Sat, Mar 30, 2024 at 09:57:21PM +0100, Krzysztof Kozlowski wrote:
>>> Core in platform_driver_register() already sets the .owner, so
On Fri, Jun 28, 2024 at 05:31:35PM -0400, Alex Deucher wrote:
> Hi Dave, Sima,
>
> More stuff for 6.11.
>
> The following changes since commit a78313bb206e0c456a989f380c4cbd8af8af7c76:
>
> Merge tag 'drm-intel-gt-next-2024-06-12' of
> https://gitlab.freedesktop.org/drm/i915/kernel into drm-ne
On Wed, Jul 03, 2024 at 05:13:13PM -0400, Alex Deucher wrote:
> Hi Dave, Sima,
>
> More new stuff for 6.11. There will be a few additional patches next
> week for new IPs that were added in this cycle just to get them tied off,
> but this should be it for general changes.
>
> The following chang
Patches to STI DRM are not being picked up, so even though there is
maintainer activity, it seems that these drivers are not being actively
looked at. Reflect this in maintainer status.
Link:
https://lore.kernel.org/all/77b4e4ad-2b1e-4b6d-bc3b-0c7b339bc...@linaro.org/
Link:
https://lore.kernel.
On 05/07/2024 11:59, Krzysztof Kozlowski wrote:
On 04/06/2024 15:18, Krzysztof Kozlowski wrote:
On 27/05/2024 16:47, Alain Volmat wrote:
Hi Krzysztof,
thanks for your patch, sorry for the delay.
On Sat, Mar 30, 2024 at 09:57:21PM +0100, Krzysztof Kozlowski wrote:
Core in platform_driver_regi
On Thu, Jul 04, 2024 at 07:31:54AM +, Tvrtko Ursulin wrote:
>
> Hi Dave, Sima,
>
> The final pull for 6.11 is quite small and only contains a handful of
> fixes in areas such as stolen memory probing on ATS-M, GuC priority
> handling, out of memory reporting noise downgrade and fence register
Am 05.07.24 um 10:48 schrieb Lukas Wunner:
On Thu, Jul 04, 2024 at 03:14:50PM +0100, Florian Fainelli wrote:
On 6/30/2024 4:36 PM, Stefan Wahren wrote:
On resume of the Raspberry Pi the dwc2 driver fails to enable
HCD_FLAG_HW_ACCESSIBLE before re-enabling the interrupts.
This causes a situation
On Fri, Jul 05, 2024 at 05:28:00PM +0800, Chen Ni wrote:
> Add check for the return value of spi_setup() and return the error
> if it fails in order to catch the error.
>
> Signed-off-by: Chen Ni
Reviewed-by: Daniel Thompson
Daniel.
On Thu, Jul 04, 2024 at 08:40:26AM -0700, Rob Clark wrote:
> On Thu, Jul 4, 2024 at 7:08 AM Daniel Vetter wrote:
> >
> > On Tue, Jul 02, 2024 at 05:32:39AM -0700, Rob Clark wrote:
> > > On Fri, Jun 28, 2024 at 10:44 AM Daniel Vetter wrote:
> > > >
> > > > On Thu, Jun 27, 2024 at 11:51:37AM -0700,
On Fri, 5 Jul 2024 at 13:04, Neil Armstrong wrote:
>
> On 05/07/2024 11:59, Krzysztof Kozlowski wrote:
> > On 04/06/2024 15:18, Krzysztof Kozlowski wrote:
> >> On 27/05/2024 16:47, Alain Volmat wrote:
> >>> Hi Krzysztof,
> >>>
> >>> thanks for your patch, sorry for the delay.
> >>>
> >>> On Sat, M
On Thu, Jul 04, 2024 at 03:17:09PM +0200, Maxime Ripard wrote:
> Hi,
>
> Here's this week drm-misc-next PR, and the last PR for the 6.11 release cycle.
>
> Thanks!
> Maxime
>
> drm-misc-next-2024-07-04:
> drm-misc-next for $kernel-version:
>
> UAPI Changes:
>
> Cross-subsystem Changes:
>
> Co
On Thu, Jul 04, 2024 at 08:48:18AM -0700, Rob Clark wrote:
> Hi Dave, Sima,
>
> This is the main pull for v6.11. It includes a merge of the immutable
> tag qcom/20240430-a750-raytracing-v3-2-7f57c5ac0...@gmail.com to pick
> up dependencies for raytracing and SMEM speedbin.
>
> Further descriptio
On Wed, Jul 03, 2024 at 02:47:23PM -0400, Alex Deucher wrote:
> Hi Dave, Sima,
>
> Fixes for 6.10.
>
> The following changes since commit 22a40d14b572deb80c0648557f4bd502d7e83826:
>
> Linux 6.10-rc6 (2024-06-30 14:40:44 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.
On 05/07/2024 12:37, Dmitry Baryshkov wrote:
> Acked-by: Alain Volmat
What does this ack mean? You are the maintainer, so what is supposed to
happen now? If maintainer does not take patches, then the DRM STI looks
orphaned.
>>>
>>> +Cc Neil, Dmitry,
>>>
>>> I pinged and pin
d test for drm_framebuffer_free()
config: arc-randconfig-001-20240705
(https://download.01.org/0day-ci/archive/20240705/202407051851.5p18lnvw-...@intel.com/config)
compiler: arceb-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20240705/202407051851.5p18lnvw-...
+Alain
On Tue, Jun 04, 2024 at 03:18:55PM GMT, Krzysztof Kozlowski wrote:
> On 27/05/2024 16:47, Alain Volmat wrote:
> > Hi Krzysztof,
> >
> > thanks for your patch, sorry for the delay.
> >
> > On Sat, Mar 30, 2024 at 09:57:21PM +0100, Krzysztof Kozlowski wrote:
> >> Core in platform_driver_reg
On Fri, Jul 05, 2024 at 12:03:56PM +0200, Krzysztof Kozlowski wrote:
> Patches to STI DRM are not being picked up, so even though there is
> maintainer activity, it seems that these drivers are not being actively
> looked at. Reflect this in maintainer status.
Note that since the driver is in drm
On Sat, 30 Mar 2024 21:38:28 +0100, Krzysztof Kozlowski wrote:
> Core in platform_driver_register() already sets the .owner, so driver
> does not need to. Whatever is set here will be anyway overwritten by
> main driver calling platform_driver_register().
>
>
Applied to misc/kernel.git (drm-mis
On Fri, Jul 05, 2024 at 01:19:50PM GMT, Daniel Vetter wrote:
> On Fri, Jul 05, 2024 at 12:03:56PM +0200, Krzysztof Kozlowski wrote:
> > Patches to STI DRM are not being picked up, so even though there is
> > maintainer activity, it seems that these drivers are not being actively
> > looked at. Ref
On Thu, 4 Jul 2024 22:17:08 +0300, Dmitry Baryshkov wrote:
> Currently the DRM DSC functions are selected by the
> DRM_DISPLAY_DP_HELPER Kconfig symbol. This is not optimal, since the DSI
> code (both panel and host drivers) end up selecting the seemingly
> irrelevant DP helpers. Split the DSC code
On 05/07/2024 13:22, Maxime Ripard wrote:
> On Fri, Jul 05, 2024 at 01:19:50PM GMT, Daniel Vetter wrote:
>> On Fri, Jul 05, 2024 at 12:03:56PM +0200, Krzysztof Kozlowski wrote:
>>> Patches to STI DRM are not being picked up, so even though there is
>>> maintainer activity, it seems that these drive
On 05/07/2024 13:14, Maxime Ripard wrote:
> +Alain
>
> On Tue, Jun 04, 2024 at 03:18:55PM GMT, Krzysztof Kozlowski wrote:
>> On 27/05/2024 16:47, Alain Volmat wrote:
>>> Hi Krzysztof,
>>>
>>> thanks for your patch, sorry for the delay.
>>>
...
>>>
>>> Acked-by: Alain Volmat
>>
>> What does thi
(was: Rate-limit shadow-FB-to-console-update to screen refresh)
Implement support for VBLANK events in mgag200.
Patches 1 to 5 prepare mgag200's modesetting code by renaming or
adding variables for various hardware fields. This makes the code
more readable and aligns it with the programming manua
In mgag200_set_mode_regs(), use hexadecimal indices for accessing
registers. Aligns the code with the register indices in the Matrox
programming manuals. Also convert to lower-case hexadecimal values.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 50 +-
Use the values with the crtc_ prefix from struct drm_display_mode to
program hardware. The DRM core adjusted these values to the requirements
of CRTC hardware.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 16
1 file changed, 8 insertions(+), 8 de
Represent fields for horizontal and vertical blanking with ,
, and . Aligns the code with the Matrox
programming manuals.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 29 ++
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/
In mgag200_set_mode_regs(), align variable names with the field names
given in the Matrox programming manuals. Makes the code and docs grep-
able.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 56 +-
1 file changed, 28 insertions(+), 28 del
Replace the line-compare value of with a dedicated variable
. Improves readability and prepares for vblank support.
Signed-off-by: Thomas Zimmermann
Acked-by: Sam Ravnborg
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a
There's no VBLANK interrupt on Matrox chipsets. The workaround that is
being used here and in other free Matrox drivers is to program
to the value of and enable the VLINE interrupt. This triggers
an interrupt at the time when VBLANK begins.
VLINE uses separate registers for enabling and clearing
Implement struct drm_crtc_funcs.get_vblank_timestamp with the DRM
helper drm_crtc_vblank_helper_get_vblank_timestamp() with its helper
get_scanout_position. Read the scanout position from the MGAREG_VCOUNT
register.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/mgag200/mgag200_drv.h | 10
Am 03.07.24 um 17:51 schrieb Thomas Hellström:
On Wed, 2024-07-03 at 15:25 +0200, Christian König wrote:
Some contended objects might never be locked again in the case of
eviction
handling for example.
Make sure that those doesn't show up in the list of locked objects
until
they are explicitely
Hello Liu,
On Fri, Jul 05, 2024 at 05:09:22PM +0800, Liu Ying wrote:
> This patch series aims to add Freescale i.MX8qxp Display Controller support.
I really appreciate your work here, I am looking forward for a better
support in mainline Linux for both i.MX8QXP and i.MX8QP.
With that said, would
The caching mode for buffer objects with VRAM as a possible
placement was forced to write-combined, regardless of placement.
However, write-combined system memory is expensive to allocate and
even though it is pooled, the pool is expensive to shrink, since
it involves global CPU TLB flushes.
More
On Fri, 2024-07-05 at 14:41 +0200, Christian König wrote:
> Am 03.07.24 um 17:51 schrieb Thomas Hellström:
> > On Wed, 2024-07-03 at 15:25 +0200, Christian König wrote:
> > > Some contended objects might never be locked again in the case of
> > > eviction
> > > handling for example.
> > >
> > > Ma
On Fri, Jul 05, 2024 at 01:33:38PM +0200, Krzysztof Kozlowski wrote:
> On 05/07/2024 13:22, Maxime Ripard wrote:
> > On Fri, Jul 05, 2024 at 01:19:50PM GMT, Daniel Vetter wrote:
> >> On Fri, Jul 05, 2024 at 12:03:56PM +0200, Krzysztof Kozlowski wrote:
> >>> Patches to STI DRM are not being picked u
On Thu, Jul 04, 2024 at 02:24:49PM GMT, Maxime Ripard wrote:
> On Fri, Jun 28, 2024 at 04:42:35PM GMT, Thierry Reding wrote:
> > On Fri, Jun 28, 2024 at 03:08:46PM GMT, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Fri, Jun 28, 2024 at 01:29:17PM GMT, Thierry Reding wrote:
> > > > On Tue, May 21,
On Thu, Jul 04, 2024 at 06:45:36PM GMT, Marc Gonzalez wrote:
> From: Arnaud Vrac
>
> Ported from the downstream driver.
Please write some sensible commit message.
>
> Signed-off-by: Arnaud Vrac
> Signed-off-by: Marc Gonzalez
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
>
On Fri, Jul 05, 2024 at 12:22:33PM +0200, Stefan Wahren wrote:
> Am 05.07.24 um 10:48 schrieb Lukas Wunner:
> > A similar issue was reported for Agilex platforms back in 2021:
> >
> > https://lore.kernel.org/all/5e8cbce0-3260-2971-484f-fc73a3b2b...@synopsys.com/
> >
> > It was fixed by commit 3d8
Hi Linus,
Dave is on vacations, should be back next week. Just small fixes all over
here, all quiet as it should.
Cheers, Sima
drm-fixes-2024-07-05:
drm-fixes for v6.10-rc7
drivers:
- amd: mostly amdgpu display fixes + radeon vm NULL deref fix
- xe: migration error handling + typoed register na
Hi Krzysztof, Daniel, and Maxime,
On Fri, Jul 05, 2024 at 03:41:26PM +0200, Daniel Vetter wrote:
> On Fri, Jul 05, 2024 at 01:33:38PM +0200, Krzysztof Kozlowski wrote:
> > On 05/07/2024 13:22, Maxime Ripard wrote:
> > > On Fri, Jul 05, 2024 at 01:19:50PM GMT, Daniel Vetter wrote:
> > >> On Fri, Ju
Adding dri-devel
On Fri, 5 Jul 2024 at 17:14, Stefan Wahren wrote:
> Hi,
> last year my Raspberry Pi 3B Plus died, so i didn't noticed this sooner.
> If I ran Raspberry Pi OS Bullseye with X11 and a recent Mainline Kernel
> (arm/multi_v7_defconfig) on my new Raspberry Pi 3 B+, i'm getting the
>
Hi Jeremy,
Am 05.07.24 um 17:03 schrieb Lukas Wunner:
On Fri, Jul 05, 2024 at 12:22:33PM +0200, Stefan Wahren wrote:
Am 05.07.24 um 10:48 schrieb Lukas Wunner:
The real question is whether BCM2848 platforms likewise cannot disable
the clock of the dwc2 controller or whether this is specific to
These are cherry-picks from the xe shrinker series here:
https://patchwork.freedesktop.org/series/131815/
extracted to speed up review progress and inclusion.
The series provides a restartable LRU walk and makes it possible
resume the walk after dropping the lock to evict or swap out.
Patch 1-4
To be able to handle list unlocking while traversing the LRU
list, we want the iterators not only to point to the next
position of the list traversal, but to insert themselves as
list nodes at that point to work around the fact that the
next node might otherwise disappear from the list while
the it
Have iterators insert themselves into the list they are iterating
over using hitch list nodes. Since only the iterator owner
can remove these list nodes from the list, it's safe to unlock
the list and when continuing, use them as a starting point. Due to
the way LRU bumping works in TTM, newly adde
To address the problem with hitches moving when bulk move
sublists are lru-bumped, register the list cursors with the
ttm_lru_bulk_move structure when traversing its list, and
when lru-bumping the list, move the cursor hitch to the tail.
This also means it's mandatory for drivers to call
ttm_lru_bu
To make the transition to using lru hitches easier,
simplify the ttm_resource_manager_next() interface to only take
the cursor and reuse ttm_resource_manager_next() functionality
from ttm_resource_manager_first().
Cc: Christian König
Cc: Somalapuram Amaranath
Cc: Matthew Brost
Cc:
Signed-off-b
Provide a generic LRU walker in TTM, in the spirit of drm_gem_lru_scan()
but building on the restartable TTM LRU functionality.
The LRU walker optionally supports locking objects as part of
a ww mutex locking transaction, to mimic to some extent the
current functionality in ttm. However any -EDEAD
Rework the TTM swapping to use the LRU walker helper.
This helps fixing up the ttm_bo_swapout() interface
to be consistent about not requiring any locking.
For now mimic the current behaviour of using trylock
only. We could be using ticket-locks here but defer
that until it's deemed necessary. The
Use the LRU walker for eviction. This helps
removing a lot of code with weird locking
semantics.
The functionality is slightly changed so that
when trylocked buffer objects are exhausted, we
continue to interleave walks with ticket-locks while
there is still progress made. The list walks are
not r
Make the interface more symmetric by providing and using a
ttm_resource_cursor_init().
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/ttm/ttm_bo.c | 3 ++-
drivers/gpu/drm/ttm/ttm_bo_util.c | 4 +++-
drivers/gpu/drm/ttm/ttm_resource.c | 34 +-
include/dr
Just figured I'll jump in on one detail here.
On Fri, Jul 05, 2024 at 04:31:34PM +0200, Thierry Reding wrote:
> On Thu, Jul 04, 2024 at 02:24:49PM GMT, Maxime Ripard wrote:
> > On Fri, Jun 28, 2024 at 04:42:35PM GMT, Thierry Reding wrote:
> > > On Fri, Jun 28, 2024 at 03:08:46PM GMT, Maxime Ripard
https://bugzilla.kernel.org/show_bug.cgi?id=219007
Bug ID: 219007
Summary: opening and closing /dev/dri/card0 in a QEMU KVM
instance will shutdown system, 6.10.0-rc6+
Product: Drivers
Version: 2.5
Hardware: All
https://bugzilla.kernel.org/show_bug.cgi?id=219007
Colin Ian King (colin.i.k...@gmail.com) changed:
What|Removed |Added
Hardware|All |Intel
https://bugzilla.kernel.org/show_bug.cgi?id=219007
--- Comment #1 from Colin Ian King (colin.i.k...@gmail.com) ---
Note this also can reproduce when running *without* root privileged too, so
this is a user space DoS attack vector.
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Hi,
Am 05.07.24 um 17:19 schrieb Daniel Vetter:
Adding dri-devel
On Fri, 5 Jul 2024 at 17:14, Stefan Wahren wrote:
Hi,
last year my Raspberry Pi 3B Plus died, so i didn't noticed this
sooner.
If I ran Raspberry Pi OS Bullseye with X11 and a recent Mainline
Kernel
(arm/
On Fri, Jul 05, 2024 at 05:09:32PM +0800, Liu Ying wrote:
> Add myself as the maintainer of i.MX8qxp Display Controller.
>
> Signed-off-by: Liu Ying
> ---
> MAINTAINERS | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 35db18d26c11..
On Fri, Jul 5, 2024 at 3:36 AM Daniel Vetter wrote:
>
> On Thu, Jul 04, 2024 at 08:40:26AM -0700, Rob Clark wrote:
> > On Thu, Jul 4, 2024 at 7:08 AM Daniel Vetter wrote:
> > >
> > > On Tue, Jul 02, 2024 at 05:32:39AM -0700, Rob Clark wrote:
> > > > On Fri, Jun 28, 2024 at 10:44 AM Daniel Vetter
The pull request you sent on Fri, 5 Jul 2024 17:14:38 +0200:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2024-07-05
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/dd9d7390b2de008448eb3328d4a0504c76c74572
Thank you!
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ht
The perf counter read functions don't just read registers, but they
also mutate state to direct the reads towards the correct pipe and
engine. Assert that the GPU mutex is held at this point, so that
those state changes don't interfere with others.
Signed-off-by: Lucas Stach
---
v2: new patch
---
Update state_hi.xml.h header from etna_viv commit
8f43a34fd9cd ("rndb: document FE current primitve debug reg")
Signed-off-by: Lucas Stach
---
v2: no changes
---
drivers/gpu/drm/etnaviv/state_hi.xml.h | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/d
A later change will use the FE debug registers to improve GPU
progress monitoring. Instead of having to keep track of the
usage state of the debug registers and lock access to the
VIVS_HI_CLOCK_CONTROL register, statically enable debug
register access during GPU init.
The Vivante downstream driver
The perfmon sampling mutates shared GPU state (e.g. VIVS_HI_CLOCK_CONTROL
to select the pipe for the perf counter reads). To avoid clashing with
other functions mutating the same state (e.g. etnaviv_gpu_update_clock)
the perfmon sampling needs to hold the GPU lock.
Fixes: 68dc0b295dcb ("drm/etnavi
Large draws can make the GPU appear to be stuck to the current hangcheck
logic as the FE address will not move until the draw is finished. However,
the FE has a debug register, which records the current primitive ID within
a draw. Using this debug register we can extend the timeout as long as the
d
Hello Vivek and Andrew,
On Sun, 23 Jun 2024 23:36:11 -0700 Vivek Kasireddy
wrote:
> For drivers that would like to longterm-pin the folios associated
> with a memfd, the memfd_pin_folios() API provides an option to
> not only pin the folios via FOLL_PIN but also to check and migrate
> them if t
On Fri, Jul 05, 2024 at 12:16:14PM -0500, Jeremy Linton wrote:
> > Am 05.07.24 um 17:03 schrieb Lukas Wunner:
> > > Careful there, the patch vaguely says...
> > >
> > > With that added and identified as "BCM2848",
> > > an id in use by other OSs for this device, the dw2
> > > controlle
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