Hi Dave
Am 11.10.23 um 17:52 schrieb Dave Stevenson:
Hi Thomas (and everyone else)
Maxime has suggested you're the person for DRM framebuffer emulation.
I'm getting some unexpected behaviour when there are multiple DRM
drivers in play. In this case it happens to be vc4 and the tiny
hx8357d SPI
On 12/10/2023 08:54, Yong Wu (吴勇) wrote:
>
> Thanks Jeffrey for the addition.
>
> Hi Rob, krzysztof,
>
> Just a ping. Is Jeffrey's reply ok for you?
I did not see any patch posted and I am way behind reviewing patches to
review also non-patches-patches...
Best regards,
Krzysztof
On Thu, Oct 12, 2023 at 12:27:49PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> On Thu, 12 Oct 2023 12:22:09 +1100 Stephen Rothwell
> wrote:
> >
> > After merging the drm-misc tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> > drivers/usb/typec/altmodes/displaypo
On Thu, 12 Oct 2023 08:58:14 +0200, Javier Martinez Canillas wrote:
> There are DT properties that can be shared across different Solomon OLED
> Display Controller families. Split them into a separate common schema to
> avoid these properties to be duplicated in different DT bindings schemas.
>
Hi Javier
Am 12.10.23 um 08:58 schrieb Javier Martinez Canillas:
[...]
+struct ssd130x_funcs {
+ int (*init)(struct ssd130x_device *ssd130x);
+ int (*set_buffer_sizes)(struct ssd130x_device *ssd130x);
+ void (*align_rect)(struct ssd130x_device *ssd130x, struct drm_rect
*rec
Hi,
sorry, I missed this patch at first.
Am 01.10.23 um 00:14 schrieb Randy Dunlap:
Correct spelling of "beginning".
Signed-off-by: Randy Dunlap
Cc: Thomas Zimmermann
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Thomas Zimmermann
---
include/linux/iosys-map.h |4 ++--
1 file
Hi Javier,
On Thu, Oct 12, 2023 at 8:58 AM Javier Martinez Canillas
wrote:
> The Solomon SSD132x controllers (such as the SSD1322, SSD1325 and SSD1327)
> are used by 16 grayscale dot matrix OLED panels, extend the driver to also
> support this chip family.
>
> Signed-off-by: Javier Martinez Canil
Hi Javier,
On Thu, Oct 12, 2023 at 8:58 AM Javier Martinez Canillas
wrote:
> There are DT properties that can be shared across different Solomon OLED
> Display Controller families. Split them into a separate common schema to
> avoid these properties to be duplicated in different DT bindings schem
On čtvrtek 5. října 2023 15:56:47 CEST Matthew Wilcox (Oracle) wrote:
> If the shared memory object is larger than the DRM object that it backs,
> we can overrun the page array. Limit the number of pages we install
> from each folio to prevent this.
>
> Signed-off-by: Matthew Wilcox (Oracle)
> R
Thomas Zimmermann writes:
Hello Thomas,
Thanks a lot for your feedback.
> Hi Javier
>
> Am 12.10.23 um 08:58 schrieb Javier Martinez Canillas:
> [...]
>>
>> +struct ssd130x_funcs {
>> +int (*init)(struct ssd130x_device *ssd130x);
>> +int (*set_buffer_sizes)(struct ssd130x_device *ssd
Geert Uytterhoeven writes:
Hello Geert,
Thanks for your feedback.
> Hi Javier,
>
[...]
>> + u32 array_idx = 0;
>> + int ret, i, j;
>
> unsigned int i, j;
>
Right, I'll change that in v3.
--
Best regards,
Javier Martinez Canillas
Core Platforms
Red Hat
Hi
Am 10.10.23 um 19:46 schrieb Joey Gouly:
The `res` variable is already a `struct resource *`, don't take the address of
it.
Fixes incorrect output:
simple-framebuffer 9e20dc000.framebuffer: [drm] *ERROR* could not
acquire memory range [??? 0x4be88a387d00-0xfefffde0a240 fla
Geert Uytterhoeven writes:
> Hi Javier,
>
> On Thu, Oct 12, 2023 at 8:58 AM Javier Martinez Canillas
> wrote:
>> There are DT properties that can be shared across different Solomon OLED
>> Display Controller families. Split them into a separate common schema to
>> avoid these properties to be du
Hi Javier
Am 12.10.23 um 10:02 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Hello Thomas,
Thanks a lot for your feedback.
Hi Javier
Am 12.10.23 um 08:58 schrieb Javier Martinez Canillas:
[...]
+struct ssd130x_funcs {
+ int (*init)(struct ssd130x_device *ssd130x);
Hi
Am 11.10.23 um 16:32 schrieb Thierry Reding:
From: Thierry Reding
We need to check if a link is non-NULL before trying to delete it.
Signed-off-by: Thierry Reding
Reviewed-by: Thomas Zimmermann
I'm going to merge the patch into drm-misc-next with the additional
Fixes tag
Fixes: 61d
Changes since v6:
- Rebase on v6.6-rc5.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=792079
- Depends on:
Message ID = 20231006073831.10402-5-shawn.s...@mediatek.com
- Discard splitting RDMA's common properties and instead use 'allOf' to
isolate dif
The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names.
In addition, fix improper space indent in example.
Fixes: 4ad7b39623ab ("media: dt-binding: mediatek: add bindings for MediaTek
MDP3 components")
Signed-off-by: Moudy Ho
Acked-by: Rob Herring
---
.../bindings/media/med
Add the fundamental hardware configuration of component FG,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-fg.yaml | 61 +++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/med
To simplify maintenance and avoid branches, the identical component
should be merged and placed in the path belonging to the MDP
(from display/* to media/*).
In addition, currently only MDP utilizes RDMA through CMDQ, and the
necessary properties for "mediatek,gce-events", and "mboxes" have been
s
Add the fundamental hardware configuration of component HDR,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-hdr.yaml | 60 +++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/me
MT8195 WROT inherited from MT8183, add the corresponding
compatible name to it.
Signed-off-by: Moudy Ho
---
.../devicetree/bindings/media/mediatek,mdp3-wrot.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-w
Add a compatible string for the COLOR block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
---
.../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek
Add a compatible string for the OVL block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
---
.../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,o
Add the fundamental hardware configuration of component TCC,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++
1 file changed, 62 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/me
MT8195 RSZ inherited from MT8183, add the corresponding
compatible name to it.
Signed-off-by: Moudy Ho
---
.../devicetree/bindings/media/mediatek,mdp3-rsz.yaml| 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rs
Add the fundamental hardware configuration of component STITCH,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-stitch.yaml | 61 +++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media
Add a compatible string for the PAD block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
---
.../bindings/display/mediatek/mediatek,padding.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/display/med
Add a compatible string for the AAL block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
Acked-by: Conor Dooley
---
.../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/dis
Added the configuration for MT8195 RDMA. In comparison to MT8183, it
no longer shares SRAM with RSZ, and there are now preconfigured 5 mbox.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-rdma.yaml| 26 ++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff -
Add compatible string and GCE property for MT8195 SPLIT, of
which is operated by MDP3.
Signed-off-by: Moudy Ho
---
.../display/mediatek/mediatek,split.yaml | 27 +++
1 file changed, 27 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,s
Add a compatible string for the MERGE block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek
Add the fundamental hardware configuration of component TDSHP,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/
From: Markus Niebel
The DE signal is active high on this display, fill in the missing
bus_flags. This aligns panel_desc with its display_timing.
Fixes: 9a2654c0f62a ("drm/panel: Add and fill drm_panel type field")
Fixes: b3bfcdf8a3b6 ("drm/panel: simple: add Tianma TM070JVHG33")
Signed-off-by:
On Thu, 05 Oct 2023 14:56:47 +0100, Matthew Wilcox (Oracle) wrote:
> If the shared memory object is larger than the DRM object that it backs,
> we can overrun the page array. Limit the number of pages we install
> from each folio to prevent this.
>
>
Applied to drm/drm-misc (drm-misc-fixes).
T
.
*/
if (of_count_phandle_with_args(dev->of_node, "power-domains",
"#power-domain-cells") != 1)
return 0;
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/base/power/domain.c?h=n
On Wed, 11 Oct 2023 11:42:24 +0200
Daniel Vetter wrote:
> On Wed, Oct 11, 2023 at 11:48:16AM +0300, Pekka Paalanen wrote:
> > On Tue, 10 Oct 2023 10:06:02 -0600
> > jim.cro...@gmail.com wrote:
> >
> > > since I name-dropped you all,
> >
> > Hi everyone,
> >
> > I'm really happy to see this
Add an helper to setup the force clock control as it will
be used in multiple HW files.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 23 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21
Starting with the SM8550 platform, the SSPP & WB Clock Controls are
no more in the MDP TOP registers, but in the SSPP & WB register space.
Add the corresponding SSPP & WB ops and use them before/after calling the
QoS and OT limit setup functions.
WB tested with:
$ modetest -M msm -a -s 40@103:102
Now SSPP and WB can have setup_force_clk_ctrl() ops, it's simpler to call
them from the plane and wb code and call into the mdp ops if not present.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 37 +--
driver
The SM8550 has the SSPP clk_ctrl in the SSPP registers, remove the
duplicate clock controls from the MDP top.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 20
1 file changed, 20 deletions(-)
diff --g
Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.
Implement setup_clk_force_ctrl() only starting from major version 9
which corresponds to SM8550 MDSS.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstro
Enable WB2 hardware block, enabling writeback support on this platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/cata
Hi Biju,
On Mon, Oct 2, 2023 at 2:28 PM Biju Das wrote:
> The LCD controller is composed of Frame Compression Processor (FCPVD),
> Video Signal Processor (VSPD), and Display Unit (DU).
>
> It has DPI/DSI interfaces and supports a maximum resolution of 1080p
> along with 2 RPFs to support the blen
On Mon, 09 Oct 2023 11:32:23 +0200, Uwe Kleine-König wrote:
> Since commit 00e7e698bff1 ("backlight: pwm_bl: Configure pwm only once
> per backlight toggle") calling pwm_backlight_power_off() doesn't disable
> the PWM any more. However this is necessary to suspend because PWM
> drivers usually refu
drm-misc-next-2023-10-12:
drm-misc-next for v6.7-rc1:
Contains the previous pull request drm-misc-next-2023-10-06 + following:
Cross-subsystem Changes:
- Rename fb_pgprot to pgprot_framebuffer and remove file argument/
- Update iosys-map documentation typos.
Core Changes:
- Assorted fixes to dr
Hi Geert Uytterhoeven,
Thanks for the feedback.
> Subject: Re: [PATCH v11 3/4] drm: renesas: Add RZ/G2L DU Support
>
> Hi Biju,
>
> On Mon, Oct 2, 2023 at 2:28 PM Biju Das
> wrote:
> > The LCD controller is composed of Frame Compression Processor (FCPVD),
> > Video Signal Processor (VSPD), an
Hello Adrián Larumbe,
The patch 730c2bf4ad39: "drm/panfrost: Add support for devcoredump"
from Jul 29, 2022 (linux-next), leads to the following Smatch static
checker warning:
drivers/gpu/drm/panfrost/panfrost_dump.c:226 panfrost_core_dump()
warn: 'page' isn't an ERR_PTR
drivers/
Hello Andrzej Hajda,
The patch 67fbf3a3ef84: "drm/exynos/iommu: merge IOMMU and DMA code"
from Oct 12, 2018 (linux-next), leads to the following Smatch static
checker warning:
drivers/gpu/drm/exynos/exynos_drm_dma.c:120 exynos_drm_register_dma()
warn: 'mapping' isn't an ERR_PTR
d
On Thu, Oct 12, 2023 at 11:55:48AM +0300, Pekka Paalanen wrote:
> On Wed, 11 Oct 2023 11:42:24 +0200
> Daniel Vetter wrote:
>
> > On Wed, Oct 11, 2023 at 11:48:16AM +0300, Pekka Paalanen wrote:
> > > On Tue, 10 Oct 2023 10:06:02 -0600
> > > jim.cro...@gmail.com wrote:
> > >
> > > > since I nam
missing AAL_GAMMA_LUT_EN bit setting to mtk_aal_gamma_set()
- Rebased over next-20231012
Changes in v10:
- Moved snippet from patch [7/15] to patch [6/15] as that was
intended to be there instead; fixes build issue for patch [6/15]
as pointed out by the kernel text robot (oops, sorry
From: "Jason-JH.Lin"
Adjust the parameters in mtk_drm_gamma_set_common()
- add (struct device *dev) to get lut_diff from gamma's driver data
- remove (bool lut_diff) and use false as default value in the function
Signed-off-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergnat
Reviewed-by: CK Hu
Invert the check for state->gamma_lut and move it at the beginning
of the function to reduce indentation: this prepares the code for
keeping readability on later additions.
This commit brings no functional changes.
Reviewed-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergnat
Reviewed-by: CK Hu
Sig
Use drm_color_lut_extract() to avoid open-coding the bits reduction
calculations for each color channel and use a struct drm_color_lut
to temporarily store the information instead of an array of u32.
Also, slightly improve the precision of the HW LUT calculation in the
LUT DIFF case by performing
In preparation for adding a 12-bits gamma support for the DISP_GAMMA
IP, remove the mtk_gamma_set_common() function and move the relevant
bits in mtk_gamma_set() for DISP_GAMMA and mtk_aal_gamma_set() for
DISP_AAL: since the latter has no more support for gamma manipulation
(being moved to a differ
The kerneldoc for struct mtk_disp_aal is missing: write one and
document this structure.
Reviewed-by: CK Hu
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
Reviewed-by: CK Hu
Reviewed-by: Nícolas F. R. A. Prado
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 10 --
1 file changed, 8 ins
The mtk_disp_gamma structure was completely undocumented: add some
kerneldoc documentation to it.
Reviewed-by: CK Hu
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
Now that this driver supports 12-bit LUTs, we can add support for the
DISP_GAMMA found on the MT8195 SoC: add its driver data and compatible.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/driv
New SoCs, like MT8195, not only may support bigger lookup tables, but
have got a different register layout to support bigger precision:
support specifying the number of `lut_bits` for each SoC and use it
in mtk_gamma_set_common() to perform the right calculations and add
support for 12-bit gamma lo
Disable relay mode at the end of LUT programming to make sure that the
processed image goes through in both DISP_GAMMA and DISP_AAL for gamma
setting.
Reviewed-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergnat
Reviewed-by: CK Hu
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/med
Newer SoCs support a bigger Gamma LUT table: wire up a callback
to retrieve the correct LUT size for each different Gamma IP.
Co-developed-by: Jason-JH.Lin
Signed-off-by: Jason-JH.Lin
[Angelo: Rewritten commit message/description + porting]
Reviewed-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergn
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Reviewed-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergnat
R
Hi Danilo,
Thanks for the feedback. The change has been made and will be in the next
version.
Thanks,
Donald
On Tue, 2023-10-10 at 18:31 +0200, Danilo Krummrich wrote:
> *** CAUTION: This email originates from a source not known to Imagination
> Technologies. Think before you click a link or o
Compress the entry for mediatek,mt8173-disp-aal, as it fits in one
line, and fix the style; while at it, also add the usual sentinel
comment to the last entry.
This commit brings no functional changes.
Reviewed-by: CK Hu
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/m
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after
programming the actual table to avoid potential visual glitches during
table modification.
Note:
GAMMA should get enabled in between vblanks, but this requires many
efforts in order to make this happen, as that requires migrating al
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
While at it, also add a definition for LUT_BITS_DEFAULT.
Reviewed-by: Jason-JH.Lin
Reviewed-by: Alexandre Mergnat
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/med
Newer Gamma IP have got multiple LUT banks: support specifying the
size of the LUT banks and handle bank-switching before programming
the LUT in mtk_gamma_set_common() in preparation for adding support
for MT8195 and newer SoCs.
Suggested-by: Jason-JH.Lin
[Angelo: Refactored original commit]
Revi
On Wed, Oct 11, 2023 at 02:10:16AM +0300, Dmitry Baryshkov wrote:
> Define a helper for creating simple transparent bridges which serve the
> only purpose of linking devices into the bridge chain up to the last
> bridge representing the connector. This is especially useful for
> DP/USB-C bridge cha
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add a compatible string for the OVL block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
Reviewed-by: AngeloGioacchino Del Regno
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add a compatible string for the MERGE block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
Reviewed-by: AngeloGioacchino Del Regno
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add a compatible string for the AAL block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
Acked-by: Conor Dooley
Reviewed-by: AngeloGioacchino Del Regno
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add a compatible string for the COLOR block in MediaTek MT8195 that
is controlled by MDP3.
Signed-off-by: Moudy Ho
Reviewed-by: AngeloGioacchino Del Regno
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add the fundamental hardware configuration of component TDSHP,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++
1 file changed, 61 insertions(+)
create mode 100
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add the fundamental hardware configuration of component TCC,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++
1 file changed, 62 insertions(+)
create mode 10064
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add the fundamental hardware configuration of component HDR,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-hdr.yaml | 60 +++
1 file changed, 60 insertions(+)
create mode 10064
On 21/09/2023 19:20, john.c.harri...@intel.com wrote:
From: John Harrison
If an active context has been banned (e.g. Ctrl+C killed) then it is
likely to be reset as part of evicting it from the hardware. That
results in a 'ignoring context reset notification: banned = 1'
message at info level
Il 12/10/23 10:40, Moudy Ho ha scritto:
Add the fundamental hardware configuration of component FG,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho
---
.../bindings/media/mediatek,mdp3-fg.yaml | 61 +++
1 file changed, 61 insertions(+)
create mode 100644
Il 12/10/23 10:40, Moudy Ho ha scritto:
MT8195 WROT inherited from MT8183, add the corresponding
compatible name to it.
Signed-off-by: Moudy Ho
Reviewed-by: AngeloGioacchino Del Regno
Il 12/10/23 10:40, Moudy Ho ha scritto:
MT8195 RSZ inherited from MT8183, add the corresponding
compatible name to it.
Signed-off-by: Moudy Ho
Reviewed-by: AngeloGioacchino Del Regno
Il 12/10/23 10:40, Moudy Ho ha scritto:
Added the configuration for MT8195 RDMA. In comparison to MT8183, it
no longer shares SRAM with RSZ, and there are now preconfigured 5 mbox.
Signed-off-by: Moudy Ho
Reviewed-by: AngeloGioacchino Del Regno
Hi Dave, Daniel,
Here is the second pull request for 6.7.
I say second and not final because there is a very small chance we might
be doing another one next week, to bring Meteorlake out of force probe
status, which was quite close this week but apparently not quite there.
At the moment it looks
Il 12/10/23 10:40, Moudy Ho ha scritto:
To simplify maintenance and avoid branches, the identical component
should be merged and placed in the path belonging to the MDP
(from display/* to media/*).
In addition, currently only MDP utilizes RDMA through CMDQ, and the
necessary properties for "medi
On Wed, 11 Oct 2023 at 17:07, Christian König wrote:
>
> Am 10.10.23 um 22:23 schrieb Dave Airlie:
> >> I think we're then optimizing for different scenarios. Our compute
> >> driver will use mostly external objects only, and if shared, I don't
> >> forsee them bound to many VMs. What saves us cur
Il 12/10/23 10:40, Moudy Ho ha scritto:
The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names.
In addition, fix improper space indent in example.
Fixes: 4ad7b39623ab ("media: dt-binding: mediatek: add bindings for MediaTek MDP3
components")
Signed-off-by: Moudy Ho
Acked-by
On Thu, 12 Oct 2023 11:53:52 +0200
Daniel Vetter wrote:
> On Thu, Oct 12, 2023 at 11:55:48AM +0300, Pekka Paalanen wrote:
> > On Wed, 11 Oct 2023 11:42:24 +0200
> > Daniel Vetter wrote:
> >
> > > On Wed, Oct 11, 2023 at 11:48:16AM +0300, Pekka Paalanen wrote:
...
> > > > - all selections
On Thu, 2023-10-12 at 09:07 +0200, Krzysztof Kozlowski wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 12/10/2023 08:54, Yong Wu (吴勇) wrote:
> >
> > Thanks Jeffrey for the addition.
> >
> > Hi Rob, krzysz
Hi,
On 10/11/23 15:05, Jani Nikula wrote:
> On Sun, 08 Oct 2023, Hans de Goede wrote:
>> Hi All,
>>
>> Ping what is the status of this now? This v3 addresses all review
>> remarks from previous versions (specifically the request to file
>> + link gitlab issues).
>>
>> So AFAICT this is ready for
Hi Dave and Daniel,
here's the PR for drm-misc-fixes.
Best regards
Thomas
drm-misc-fixes-2023-10-12:
Short summary of fixes pull:
* atomic-helper: Relax checks for unregistered connectors
* dma-buf: Work around race condition when retrieving fence timestamp
* gem: Avoid OOB access in BO mem
On 09/10/23 13:20, Devarsh Thakkar wrote:
Some SoC's such as AM62P have dedicated power domains
for OLDI which need to be powered on separetely along
with display controller.
So during driver probe, power up all attached PM domains
enumerated in devicetree node for DSS.
This also prepares ba
On Thu, Oct 12, 2023 at 08:58:14AM +0200, Javier Martinez Canillas wrote:
> There are DT properties that can be shared across different Solomon OLED
> Display Controller families. Split them into a separate common schema to
> avoid these properties to be duplicated in different DT bindings schemas.
On Thu, Oct 12, 2023 at 08:58:15AM +0200, Javier Martinez Canillas wrote:
> Add a Device Tree binding schema for the OLED panels based on the Solomon
> SSD132x family of controllers.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
> Changes in v2:
> - Remove unnecessary 'oneOf' in the SSD132
Hi Thierry,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on drm-tip/drm-tip linus/master v6.6-rc5 next-20231012]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
Hi,
On Wed, Oct 11, 2023 at 3:11 AM Doug Anderson wrote:
>
> Hi,
>
> On Tue, Oct 10, 2023 at 4:36 AM cong yang
> wrote:
> >
> > Hi,
> >
> > On Tue, Oct 10, 2023 at 4:44 AM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Fri, Oct 6, 2023 at 11:07 PM Cong Yang
> > > wrote:
> > > >
> > > > At
Linus series proposed to break out ili9882t as separate driver,
but he didn't have time for that extensive rework of the driver.
As discussed by Linus and Doug [1], keep macro using the "struct panel_init_cmd"
until we get some resolution about the binary size issue.
[1]:
https://lore.kernel.org
The Starry ILI9882t-based panel should never have been part of the boe
tv101wum driver, it is clearly based on the Ilitek ILI9882t display
controller and if you look at the custom command sequences for the
panel these clearly contain the signature Ilitek page switch (0xff)
commands. The hardware ha
At present, we have found that there may be a problem of blurred
screen during fast sleep/resume. The direct cause of the blurred
screen is that the IC does not receive 0x28/0x10. Because of the
particularity of the IC, before the panel enters sleep hid must
stop scanning, as i2c_hid_core_suspend b
DRM_PANEL_ILITEK_ILI9882T is being split out from
DRM_PANEL_BOE_TV101WUM_NL6. Since the arm64 defconfig had the BOE
panel driver enabled, let's also enable the Ilitek driver.
Reviewed-by: Douglas Anderson
Signed-off-by: Cong Yang
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 inserti
Am 12.10.23 um 12:33 schrieb Dave Airlie:
On Wed, 11 Oct 2023 at 17:07, Christian König wrote:
Am 10.10.23 um 22:23 schrieb Dave Airlie:
I think we're then optimizing for different scenarios. Our compute
driver will use mostly external objects only, and if shared, I don't
forsee them bound to
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