-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi Helen,
On Wed, 2023-09-27 at 19:28 -0300, Helen Koike wrote:
> > > +def get_unit_test_name_and_results(unit_test):
> > > + if "Artifact results/failures.csv not found" in unit_test:
> > > + return None, None
> > > + unit_test_name, u
Hi Nirmoy,
your client is still missing my e-mails? :)
> +void intel_gt_mcr_lock_reset(struct intel_gt *gt)
> +{
> + unsigned long __flags;
> +
> + lockdep_assert_not_held(>->uncore->lock);
> +
> + spin_lock_irqsave(>->mcr_lock, __flags);
> +
> + if (GRAPHICS_VER_FULL(gt->i915) >=
Hi Nirmoy,
On Wed, Sep 27, 2023 at 11:03:56PM +0200, Nirmoy Das wrote:
> During resume, the steer semaphore on GT1 was observed to be held. The
> hardware team has confirmed the safety of clearing the steer semaphore
> during driver load/resume, as no lock acquisitions can occur in this
> process
Hi Nirmoy,
On Wed, Sep 27, 2023 at 11:03:55PM +0200, Nirmoy Das wrote:
> Move early resume functions of gt to a proper file.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 ++
> drivers/gpu/drm/i915/gt/intel_gt_pm.h | 1 +
> drivers/gpu/drm/i915/i915_driver.
On Wed, 27 Sep 2023 13:54:38 +0200
Christian König wrote:
> Am 26.09.23 um 09:11 schrieb Boris Brezillon:
> > On Mon, 25 Sep 2023 19:55:21 +0200
> > Christian König wrote:
> >
> >> Am 25.09.23 um 14:55 schrieb Boris Brezillon:
> >>> +The imagination team, who's probably interested too.
> >>>
On Wed, Sep 27, 2023 at 10:22 AM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> Two function stubs were removed in an earlier commit but are now needed
> again:
>
> drivers/accel/habanalabs/common/device.c: In function 'hl_device_init':
> drivers/accel/habanalabs/common/device.c:2231:14: error:
On Wed, 2023-09-27 at 16:42 +0200, Joakim Bech wrote:
External email : Please do not click links or open attachments until you have
verified the sender or the content.
On Mon, Sep 11, 2023 at 10:30:33AM +0800, Yong Wu wrote:
> Initialise a mtk_svp heap. Currently just add a null heap, Prepare fo
On 9/28/2023 12:35 AM, Matt Roper wrote:
On Wed, Sep 27, 2023 at 11:03:56PM +0200, Nirmoy Das wrote:
During resume, the steer semaphore on GT1 was observed to be held. The
hardware team has confirmed the safety of clearing the steer semaphore
during driver load/resume, as no lock acquisitions
Hi Dave and Daniel,
drm-misc-fixes, Intel VPU Edition. Only the ivpu driver received
fixes this week.
Best regards
Thomas
drm-misc-fixes-2023-09-28:
Short summary of fixes pull:
* ivpu:
* Add PCI ids for Arrow Lake
* Fix memory corruption during IPC
* Avoid dmesg flooding
* 40xx: W
On 9/28/2023 9:19 AM, Andi Shyti wrote:
Hi Nirmoy,
On Wed, Sep 27, 2023 at 11:03:56PM +0200, Nirmoy Das wrote:
During resume, the steer semaphore on GT1 was observed to be held. The
hardware team has confirmed the safety of clearing the steer semaphore
during driver load/resume, as no lock ac
Hi
Am 26.09.23 um 09:31 schrieb Jocelyn Falempe:
On 20/09/2023 16:24, Thomas Zimmermann wrote:
Store and instance of struct drm_xfrm_buf in struct simpledrm_device
and keep the allocated memory allocated across display updates. Avoid
possibly reallocating temporary memory on each display update
On 9/28/2023 12:23 AM, Matt Roper wrote:
On Wed, Sep 27, 2023 at 11:03:54PM +0200, Nirmoy Das wrote:
Implement intel_gt_mcr_lock_reset() to provide a mechanism
for resetting the steer semaphore when absolutely necessary.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c
On 9/28/2023 9:18 AM, Andi Shyti wrote:
Hi Nirmoy,
your client is still missing my e-mails? :)
I did reply with a question!
+void intel_gt_mcr_lock_reset(struct intel_gt *gt)
+{
+ unsigned long __flags;
+
+ lockdep_assert_not_held(>->uncore->lock);
+
+ spin_lock_irqsav
On Thu, 28 Sep 2023, Ramya SR wrote:
> Reminder. Please review the reply comment.
Maybe send a patch to review?
It's also not helping that your previous mail looks like it's just
quoting other messages [1].
BR,
Jani.
[1]
https://lore.kernel.org/all/bn0pr02mb79517b267d593dc484ba34df81...@bn0
Le 27/09/2023 à 20:56, Jeffrey Kardatzke a écrit :
On Wed, Sep 27, 2023 at 8:18 AM Benjamin Gaignard
wrote:
Le 27/09/2023 à 15:46, Joakim Bech a écrit :
On Mon, Sep 25, 2023 at 12:49:50PM +, Yong Wu (吴勇) wrote:
On Tue, 2023-09-12 at 11:32 +0200, AngeloGioacchino Del Regno wrote:
Il 12
Hi Andi,
On 9/28/2023 9:24 AM, Andi Shyti wrote:
Hi Nirmoy,
On Wed, Sep 27, 2023 at 11:03:55PM +0200, Nirmoy Das wrote:
Move early resume functions of gt to a proper file.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.h
Hi
Am 27.09.23 um 19:22 schrieb Jocelyn Falempe:
drm_panic will need the low-level drm_fb__line functions.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/drm_format_helper.c | 3 ++-
include/drm/drm_format_helper.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff -
Hi,
On Mon, Sep 25, 2023 at 03:49:29PM -0700, Douglas Anderson wrote:
> As per the discussion on the lists [1], changes to this driver
> generally flow through drm-misc. Add a tag in MAINTAINERS to document
> this
>
> [1]
> https://lore.kernel.org/r/20230925054710.r3guqn5jzdl4g...@fsr-ub1664-121
Hi,
On Thu, Sep 21, 2023 at 12:57:43PM +0200, Maxime Ripard wrote:
> We've had a number of times when a patch slipped through and we couldn't
> pick them up either because our MAINTAINERS entry only covers the
> framework and thus we weren't Cc'd.
>
> Let's take another approach where we match ev
From: farah kassabri
The decoder interrupts are handled in the interrupt context
same as all user interrupts.
In such case, the wait list should be protected by
spin_lock_irqsave in order to avoid deadlock that might happen
with the user submission flow.
Signed-off-by: farah kassabri
Reviewed-b
From: Tomer Tayar
Non-completed transactions from PCIe towards the device are handled by
the AXI drain mechanism. This handling is in the PCIe level, but the
transactions are still there in the device consuming some queues
entries, and therefore the device must be reset.
Modify to perform hard-re
From: Dafna Hirschfeld
The function does not pin the pages so remove that from the inline doc.
Signed-off-by: Dafna Hirschfeld
Reviewed-by: Oded Gabbay
Signed-off-by: Oded Gabbay
---
drivers/accel/habanalabs/common/memory.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/accel/hab
Il 27/09/23 17:38, Jason-JH.Lin ha scritto:
Add mtk_drm_crtc_path enum for each display path.
Instead of using array index of all_drm_priv in mtk_drm_kms_init(),
mtk_drm_crtc_path enum can make code more readable.
Signed-off-by: Jason-JH.Lin
Reviewed-by: Fei Shao
Reviewed-by: CK Hu
Tested-by
Il 27/09/23 17:38, Jason-JH.Lin ha scritto:
Move DDP_COMPONENT_DP_INTF0 from mt8188_mtk_ddp_main array to a
connector routes array called mt8188_mtk_ddp_main_routes to support
dynamic selection capability for mt8188.
Signed-off-by: Jason-JH.Lin
Reviewed-by: AngeloGioacchino Del Regno
Il 27/09/23 17:38, Jason-JH.Lin ha scritto:
Add implementation of mtk_dsi_encoder_index to mtk_ddp_comp_func
to make mtk_dsi support dynamic connector selection.
Signed-off-by: Jason-JH.Lin
Reviewed-by: CK Hu
Reviewed-by: Fei Shao
Tested-by: Fei Shao
Reviewed-by: AngeloGioacchino Del Regno
Il 27/09/23 17:38, Jason-JH.Lin ha scritto:
To support dynamic connector selection function, each ddp_comp need to
get their encoder_index to identify which connector should be selected.
Add encoder_index interface for mtk_ddp_comp_funcs to get the encoder
identifier by drm_encoder_index().
Then
Il 27/09/23 17:38, Jason-JH.Lin ha scritto:
Add implementation of mtk_dpi_encoder_index to mtk_ddp_comp_func
to make mtk_dpi support dynamic connector selection.
Signed-off-by: Jason-JH.Lin
Reviewed-by: AngeloGioacchino Del Regno
Il 27/09/23 17:38, Jason-JH.Lin ha scritto:
Add DDP_COMPONENT_DSI0 as a main display output selection on
MT8188 VDOSYS0.
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
Reviewed-by: Matthias Brugger
Reviewed-by: Fei Shao
Tested-by: Fei Shao
Reviewed-by: AngeloGioacchino Del Regno
Am 27.09.23 um 19:22 schrieb Jocelyn Falempe:
This module displays a user friendly message when a kernel panic
occurs. It currently doesn't contain any debug information,
but that can be added later.
v2
* Use get_scanout_buffer() instead of the drm client API.
(Thomas Zimmermann)
* Add
Hi
Am 27.09.23 um 19:22 schrieb Jocelyn Falempe:
Add support for the drm_panic module, which displays a user-friendly
message to the screen when a kernel panic occurs.
Signed-off-by: Jocelyn Falempe
---
drivers/gpu/drm/tiny/simpledrm.c | 17 +
1 file changed, 17 insertions(+
On 9/28/23 08:56, Christian König wrote:
> Am 27.09.23 um 22:25 schrieb Ray Strode:
>> On Wed, Sep 27, 2023 at 4:05 AM Christian König
>> wrote:
>
>>> When it's really not desirable to account the CPU overhead to the
>>> process initiating it then you probably rather want to use an non
>>> blocki
drivers/gpu/drm/radeon/atom.c:396 atom_skip_src_int() warn: ignoring
unreachable code.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6713
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/radeon/atom.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/
On older chips, the absolute doorbell offset within
the doorbell page is based on the queue ID.
KFD is using queue ID and doorbell size to get an
absolute doorbell offset in userspace.
This patch is to adjust the absolute doorbell offset
against the doorbell id considering the doorbell
size of 32/
This patch is to adjust the absolute doorbell offset
against the doorbell id considering the doorbell
size of 32/64 bit.
v2:
- Addressed the review comment from Felix.
Cc: Christian Koenig
Cc: Alex Deucher
Signed-off-by: Shashank Sharma
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amd
Il 27/09/23 17:38, Jason-JH.Lin ha scritto:
Add dynamic select available connector flow in mtk_drm_crtc_create()
and mtk_drm_crtc_atomic_enable().
In mtk_drm_crtc_create(), if there is a connector routes array in drm
driver data, all components definded in the connector routes array will
be chec
From: Tvrtko Ursulin
Simplify the implementation of perf/OA queries by re-ogranizing the way
querying of the OA config list is done, how temporary storage is used,
and also replace the multi-step manual retrieving of user data with the
existing copy_query_item helper.
Note that this could be fur
Il 28/09/23 05:39, Shawn Sung (宋孝謙) ha scritto:
Hi CK,
On Thu, 2023-09-28 at 03:05 +, CK Hu (胡俊光) wrote:
Hi, Hsiao-chien:
On Mon, 2023-09-11 at 15:42 +0800, Hsiao Chien Sung wrote:
Padding is a new display module on MT8188, it provides ability
to add pixels to width and height of a layer
On 07/09/2023 04:05, Sandor Yu wrote:
MHDP8546 mailbox access functions will be share to other mhdp driver
and Cadence HDP-TX HDMI/DP PHY drivers.
Move those functions to head file include/drm/bridge/cdns-mhdp-mailbox.h
and convert them to macro functions.
Signed-off-by: Sandor Yu
---
.../drm
Hi Tapani,
On 9/27/2023 6:13 AM, Tapani Pälli wrote:
Fixes all regressions we saw, I also run some extra vulkan and GL
workloads, no regressions observed.
Tested-by: Tapani Pälli
Thanks to testing it. The patch is now merged with"
# v5.8+" tag so it should trickle down to
v6.4.10. as n
From: Sandor Yu
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor
According to the vendor kernel [1] , the alt_iface clock should be
enabled together with the rest of HPD clocks, to make HPD to work
properly.
[1]
https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry
The MSM HDMI PHYs have been using the ad-hoc approach / API instead of
using the generic API framework. Move all the PHYs to
drivers/phy/qualcomm and rework them to use generic PHY framework. This
way all the QMP-related code is kept close. Also in future this will
allow us to use a common set of f
Add support for HDMI PHY on Qualcomm MSM8x60 / APQ8060 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-45nm.c | 184
drivers/phy/qualcomm/phy-qcom-hdmi-preqmp.c | 32 ++--
drivers/phy/q
In preparation to converting MSM HDMI driver to use PHY framework, which
requires phy_power_on() calls to be paired with phy_power_off(), add a
conditional call to msm_hdmi_phy_powerdown() before the call to
msm_hdmi_phy_powerup().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdm
Port Qualcomm QMP HDMI PHY to the generic PHY framework. Split the
generic part and the msm8996 part. When adding support for msm8992/4 and
msm8998 (which also employ QMP for HDMI PHY), one will have to provide
the PLL programming part only.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualco
The "uni" PLL is shared between several PHYS: APQ8064's SATA,
MSM8974/APQ8084 HDMI, MSM8916 DSI, MSM8974/APQ8084 DSI.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 23 +-
drivers/phy/qualcomm/phy-qcom-uniphy.h | 32
2 fi
Add the driver for pre-QMP Qualcomm HDMI PHYs. Currently it suppports
Qualcomm MSM8960 / APQ8064 platforms, other platforms will come later.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig| 14 +
drivers/phy/qualcomm/Makefile | 6 +
drivers/phy/q
In consequent modeset calls, the atomic_pre_enable() will be called
several times without calling atomic_post_disable() inbetween. Thus
iframes will not be updated for the next mode. Fix this by setting the
iframe outside of the !power_on check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/dr
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 62ce1455f974..fbcf4dd91cd9 100644
--- a/drivers/gpu/dr
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
Import register definitions from 28nm DSI and HDMI PHYs, adding more UNI
PHY registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-uniphy.h | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.h
b/drivers/phy
Add support for HDMI PHY on Qualcomm MSM8974 / APQ8074 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig| 2 +-
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c | 327
drivers/phy/qua
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 24 ---
drivers/gpu/drm/msm/hdmi/hdmi.h| 6 +
drivers/gpu/drm/msm/hdmi/hdmi_
Change the MSM HDMI driver to use generic PHY subsystem. Moving PHY
drivers allows better code sharing with the rest of the PHY system.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 6 ---
drivers/gpu/drm/msm/hdmi/hdmi.c| 60 +++--
drivers/
Drop source files used by old HDMI PHY and HDMI PLL drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 216 ---
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 51 --
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 765 ---
drivers/gpu/drm/msm/
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
BO's RSS is updated every time new pages are allocated on demand and mapped
for the object at GPU page fault's IRQ handler, but only for heap buffers.
The reason this is unnecessary for non-heap buffers is that they are mapped
onto the GPU's VA space
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
These GPU registers will be used when programming the cycle counter, which
we need for providing accurate fdinfo drm-cycles values to user space.
Signed-off-by: Adrián Larumbe
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: A
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
Some BO's might be mapped onto physical memory chunkwise and on demand,
like Panfrost's tiler heap. In this case, even though the
drm_gem_shmem_object page array might already be allocated, only a very
small fraction of the BO is currently backed by s
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
A new DRM GEM object function is added so that drm_show_memory_stats can
provide more accurate memory usage numbers.
Ideally, in panfrost_gem_status, the BO's purgeable flag would be checked
after locking the driver's shrinker mutex, but drm_show_mem
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
The drm-stats fdinfo tags made available to user space are drm-engine,
drm-cycles, drm-max-freq and drm-curfreq, one per job slot.
This deviates from standard practice in other DRM drivers, where a single
set of key:value pairs is provided for the wh
Per agreement with Konrad, picked up this patch series.
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.
Gating that path may have a variety of effect
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.
Gating that path may have a variety of effects, from none to otherwise
inexplicable DSI timeouts.
Pro
Stop using hand-written reset function for ICC release, use
devm_of_icc_get() instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm
From: Konrad Dybcio
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are
other connection paths:
- a path that connects rotator block to the DDR.
- a path that needs to be handled to ensure MDSS register access
functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG
From: Linus Torvalds
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index ceb23eed4dce..57698d048e2c 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
VERSION = 6
PATCHLEVEL = 6
SUBLEVEL = 0
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NA
From: Konrad Dybcio
The DPU1 driver needs to handle all MDPn<->DDR paths, as well as
CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are
calculated, but the latter one has static predefines spanning all SoCs.
In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename
There are just two places where we set the bandwidth: in the resume and
in the suspend paths. Drop the wrapping function
msm_mdss_icc_request_bw() and call icc_set_bw() directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 19 ---
1 file changed, 8 insert
The CTRLDESCL0_5 register also holds other bits that are not related to the
format, which should not be overwritten when the format is set up. Use a
proper RMW access in lcdif_set_formats().
Signed-off-by: Lucas Stach
---
v3: no changes
v2: new patch
---
drivers/gpu/drm/mxsfb/lcdif_kms.c | 40 ++
The comment regarding AXI bust size configuration is a bit hard
to read. Improve the wording somewhat.
Signed-off-by: Lucas Stach
Reviewed-by: Marco Felsch
Reviewed-by: Marek Vasut
---
v3: no changes
v2: Some more rewording.
---
drivers/gpu/drm/mxsfb/lcdif_kms.c | 8
1 file changed, 4
drm_atomic_helper_commit_tail_rpm makes it hard for drivers to follow
the documented encoder/bridge enable flow, as it commits all CRTC enables
before the planes are fully set up, so drivers that can't enable the
display link without valid plane setup either need to do the plane setup
in the CRTC e
Now that the plane state is fully programmed into the hardware before
the scanout is started there is no need to program the plane framebuffer
DMA address from the CRTC atomic_enable anymore.
Signed-off-by: Lucas Stach
Reviewed-by: Marek Vasut
---
v2/3: no changes
---
drivers/gpu/drm/mxsfb/lcdi
The display clock only required to be running when the CRTC
is enabled, so we have well defined points in the DRM atomic
sequence when this clock should be enabled or disabled.
Signed-off-by: Lucas Stach
---
v3: new patch
---
drivers/gpu/drm/mxsfb/lcdif_drv.c | 4
drivers/gpu/drm/mxsfb/lcdi
Otherwise the DMA enable races with the fetch start, which causes
wrong or no data to be scanned out on the first frame. Also there
is no point in waiting for the DMA disable when the controller is
going to shut down. Simply disable the display first so no further
fetches are triggered and then shu
The buffer pitch may change when switching the buffer on a
atomic update. As the register is double buffered it can be
safely changed while the display is active.
Signed-off-by: Lucas Stach
Reviewed-by: Marek Vasut
---
v2/3: no changes
---
drivers/gpu/drm/mxsfb/lcdif_kms.c | 26 +---
Force a modeset if the new FB has a different format than the
currently active one. While it might be possible to change between
compatible formats without a full modeset as the format control is
also supposed to be double buffered, the colorspace conversion is
not, so when the CSC changes we need
Hello dri maintainers/developers,
This is a 31-day syzbot report for the dri subsystem.
All related reports/information can be found at:
https://syzkaller.appspot.com/upstream/s/dri
During the period, 3 new issues were detected and 0 were fixed.
In total, 14 issues are still open and 30 have been
This series includes patches to update the V3D kernel module
that drives the VideoCore VI GPU in Raspberry Pi 4 to also support
the Video Core VII iteration present in Raspberry Pi 5.
The first patch in the series addresses the bulk of the work and
involves mostly updates to register addresses. Th
---
drivers/gpu/drm/v3d/v3d_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c
index ffbbe9d527d3..0ed2e7ba8b33 100644
--- a/drivers/gpu/drm/v3d/v3d_drv.c
+++ b/drivers/gpu/drm/v3d/v3d_drv.c
@@ -186,6 +186,7 @@ static const struc
---
drivers/gpu/drm/v3d/v3d_debugfs.c | 173 +-
drivers/gpu/drm/v3d/v3d_gem.c | 3 +
drivers/gpu/drm/v3d/v3d_irq.c | 47
drivers/gpu/drm/v3d/v3d_regs.h| 51 -
drivers/gpu/drm/v3d/v3d_sched.c | 41 ---
5 files changed, 200 insertio
V3D t.x takes a new parameter to configure TFU jobs that needs
to be provided by user space.
---
include/uapi/drm/v3d_drm.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/v3d_drm.h b/include/uapi/drm/v3d_drm.h
index 3dfc0af8756a..1a7d7a689de3 100644
--- a/include/uapi/dr
On Wed, 20 Sep 2023 16:42:33 +0200
Danilo Krummrich wrote:
> So far the DRM GPUVA manager offers common infrastructure to track GPU VA
> allocations and mappings, generically connect GPU VA mappings to their
> backing buffers and perform more complex mapping operations on the GPU VA
> space.
>
>
Fix misspellings of "hardware".
Signed-off-by: Geert Uytterhoeven
---
include/drm/drm_bridge.h | 2 +-
include/drm/drm_modeset_helper_vtables.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
index cfb7d
Hi all,
is the second largest header file in
the DRM subsystem, and declares helpers vtables for various DRM
components. Several vtables contain methods with the same name, and all
but one vtable do not fit on the screen, making it hard to navigate to
the actual method one is interested
is the second largest header file in
the DRM subsystem, and declares helpers vtables for various DRM
components. Several vtables contain methods with the same name, and all
but one vtable do not fit on the screen, making it hard to navigate to
the actual method one is interested in.
Make it easi
Fix misspellings of "preceding".
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/drm_atomic_helper.c | 4 ++--
include/drm/drm_modeset_helper_vtables.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_ato
On 28.09.2023 13:16, Dmitry Baryshkov wrote:
> From: Sandor Yu
>
> Allow HDMI PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
>
> The parameters added here are based on HDMI PHY
> implementation practices. The current set of parameter
On Wed, 27 Sep 2023 18:52:55 +0200
Danilo Krummrich wrote:
> On 9/22/23 13:58, Boris Brezillon wrote:
> > On Wed, 20 Sep 2023 16:42:39 +0200
> > Danilo Krummrich wrote:
> >
> >> +/**
> >> + * enum drm_gpuvm_flags - flags for struct drm_gpuvm
> >> + */
> >> +enum drm_gpuvm_flags {
> >> + /**
Hi Dave, Daniel,
Here goes the first pull request for 6.7.
Nothing major in this round - a bunch of fixes, mostly relating to various
GuC and PXP features/functionalities, and a few new mostly DG2
workarounds.
Tiny bit or Meteorlake enablement and a tiny bit of selftests fixes and
even less code
> > > During resume, the steer semaphore on GT1 was observed to be held. The
> > > hardware team has confirmed the safety of clearing the steer semaphore
> > > during driver load/resume, as no lock acquisitions can occur in this
> > > process by other agents.
> > >
> > > v2: reset on resume not in
On 27/09/2023 17:36, Teres Alexis, Alan Previn wrote:
Thanks for taking the time to review this Tvrtko, replies inline below.
On Wed, 2023-09-27 at 10:02 +0100, Tvrtko Ursulin wrote:
On 26/09/2023 20:05, Alan Previn wrote:
When suspending, add a timeout when calling
intel_gt_pm_wait_for_idle
Hi,
On Thu, Sep 28, 2023 at 2:56 AM Christian König
wrote:
> > To say the "whole point" is about CPU overhead accounting sounds
> > rather absurd to me. Is that really what you meant?
>
> Yes, absolutely. See the functionality you try to implement already exists.
You say lower in this same messa
On 27/09/2023 14:48, Steven Price wrote:
On 27/09/2023 14:38, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It is better not to lose precision and not revert to 1 MiB size
granularity for every size greater than 1 MiB.
Sizes in KiB should not be so troublesome to read (and in fact machine
pars
On 27/09/2023 20:34, Belgaumkar, Vinay wrote:
On 9/21/2023 3:41 AM, Tvrtko Ursulin wrote:
On 20/09/2023 22:56, Vinay Belgaumkar wrote:
Provide a bit to disable waitboost while waiting on a gem object.
Waitboost results in increased power consumption by requesting RP0
while waiting for the r
From: Martin Krastev
LGTM
Reviewed-by: Martin Krastev
Regards,
Martin
On 28.09.23 г. 7:13 ч., Zack Rusin wrote:
From: Zack Rusin
Surfaces can be backed (i.e. stored in) memory objects (mob's) which
are created and managed by the userspace as GEM buffers. Surfaces
grab only a ttm refe
Add binding for the i.MX8MP HDMI parallel video interface block.
Signed-off-by: Lucas Stach
Reviewed-by: Laurent Pinchart
---
.../display/imx/fsl,imx8mp-hdmi-pvi.yaml | 83 +++
1 file changed, 83 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/i
This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a
full timing generator and can switch between different video sources. On
the i.MX8MP however the only supported source is the LCDIF. The block
just needs to be powered up and told about the polarity of the video
sync signals
hi,
On Thu, Sep 28, 2023 at 5:43 AM Michel Dänzer
wrote:
> >>> When it's really not desirable to account the CPU overhead to the
> >>> process initiating it then you probably rather want to use an non
> >>> blocking commit plus a dma_fence to wait for the work to end from
> >>> userspace.
> >> W
Implement intel_gt_mcr_lock_sanitize() to provide a mechanism
for cleaning the steer semaphore when absolutely necessary.
v2: remove unnecessary lock(Andi, Matt)
improve the kernel doc(Matt)
s/intel_gt_mcr_lock_clear/intel_gt_mcr_lock_sanitize
Signed-off-by: Nirmoy Das
---
drivers/gpu/d
Move early resume functions of gt to a proper file.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 1 +
drivers/gpu/drm/i915/i915_driver.c| 6 ++
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/driver
1 - 100 of 188 matches
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