On 2023-05-02 18:19:14, Jessica Zhang wrote:
> Add data_compress feature to DPU HW catalog.
>
> In DPU 7.x and later, there is a DATA_COMPRESS register that must be set
> within the DPU INTF block for DSC to work.
>
> As core_rev (and related macros) was removed from the dpu_kms struct, the
> mos
Hi
Am 02.05.23 um 21:54 schrieb Sam Ravnborg:
Hi Thomas,
On Tue, May 02, 2023 at 03:02:21PM +0200, Thomas Zimmermann wrote:
Fbdev's main header file, , includes to get
declarations for I/O helper functions. From these declarations, it
later defines framebuffer I/O helpers, such as fb_{read,wr
On Tue, May 02, 2023 at 02:26:53PM -0700, Justin Chen wrote:
> On Tue, May 2, 2023 at 12:44 PM Simon Horman
> wrote:
> >
> > On Wed, Apr 26, 2023 at 11:54:29AM -0700, Justin Chen wrote:
...
> > > +static void bcmasp_update_mib_counters(struct bcmasp_intf *priv)
> > > +{
> > > + int i, j = 0
On Tue, May 02, 2023 at 05:38:57PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The MST DSC code has a myriad of issues:
> - Platform checks are wrong (MST+DSC is TGL+ only IIRC)
> - Return values of .mode_valid_ctx() are wrong
> - .mode_valid_ctx() assumes bigjoiner might be used, but t
Thomas Zimmermann writes:
Hello Thomas,
> Am 02.05.23 um 21:54 schrieb Sam Ravnborg:
>> On Tue, May 02, 2023 at 03:02:21PM +0200, Thomas Zimmermann wrote:
[...]
>>> #include /* Why should fb driver call console
>>> functions? because console_lock() */
>>> #include
>>>
>>> +#include
On 2023-05-02 18:19:15, Jessica Zhang wrote:
> Add a dpu_hw_intf op to enable data compression.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 +++
> drivers/gpu/drm/msm/disp/d
Hi Christian,
Christian König ezt írta (időpont: 2023. máj.
2., Ke 9:59):
> Am 02.05.23 um 03:26 schrieb André Almeida:
> > Em 01/05/2023 16:24, Alex Deucher escreveu:
> >> On Mon, May 1, 2023 at 2:58 PM André Almeida
> >> wrote:
> >>>
> >>> I know that devcoredump is also used for this kind of
On Tue, 2023-05-02 at 09:45 -0400, Alex Deucher wrote:
> On Tue, May 2, 2023 at 9:35 AM Timur Kristóf
> wrote:
> >
> > Hi,
> >
> > On Tue, 2023-05-02 at 13:14 +0200, Christian König wrote:
> > > >
> > > > Christian König ezt írta (időpont:
> > > > 2023.
> > > > máj. 2., Ke 9:59):
> > > >
> >
Hi Mike,
On 5/1/2023 12:29 PM, Mike Lothian wrote:
> Hi
>
> I've not had any issues since using this, but I imagine most people
> won't know how to set swiotlb=dynamic if they start seeing this (when
> it lands)
>
> Any clue as to why this broke last cycle?
IIRC the kernel messages indicate hig
Hi,
On Tue, 2023-05-02 at 13:14 +0200, Christian König wrote:
> >
> > Christian König ezt írta (időpont: 2023.
> > máj. 2., Ke 9:59):
> >
> > > Am 02.05.23 um 03:26 schrieb André Almeida:
> > > > Em 01/05/2023 16:24, Alex Deucher escreveu:
> > > >> On Mon, May 1, 2023 at 2:58 PM André Almeid
On 5/2/23 15:34, Linux regression tracking (Thorsten Leemhuis) wrote:
On 02.05.23 15:13, Alex Deucher wrote:
On Tue, May 2, 2023 at 7:45 AM Linux regression tracking (Thorsten
Leemhuis) wrote:
On 30.04.23 13:44, Felix Richter wrote:
Hi,
I am running into an issue with the integrated GPU of
On Tue, May 02, 2023 at 05:38:57PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The MST DSC code has a myriad of issues:
> - Platform checks are wrong (MST+DSC is TGL+ only IIRC)
> - Return values of .mode_valid_ctx() are wrong
> - .mode_valid_ctx() assumes bigjoiner might be used, but t
Zack Rusin writes:
> On Tue, 2023-05-02 at 11:32 +0200, Javier Martinez Canillas wrote:
>> !! External Email
>>
>> Daniel Vetter writes:
>>
>> > On Mon, Jul 11, 2022 at 11:32:39PM -0400, Zack Rusin wrote:
>> > > From: Zack Rusin
>> > >
>> > > Cursor planes on virtualized drivers have special
On 2023-05-02 14:02:57, Kuogee Hsieh wrote:
> Legacy DPU requires PP block to be involved during DSC setting up.
This patch should clarify that "legacy" means DPU < 7.0.0, as we found
out in [1] that PINGPONG has no more register remaining in 7.x. In
addition, it seems that the DCE enable registe
On Wed, 3 May 2023 03:35:29 +
Zack Rusin wrote:
> On Tue, 2023-05-02 at 11:32 +0200, Javier Martinez Canillas wrote:
> > !! External Email
> >
> > Daniel Vetter writes:
> >
> > > On Mon, Jul 11, 2022 at 11:32:39PM -0400, Zack Rusin wrote:
> > > > From: Zack Rusin
> > > >
> > > > Curs
Am 02.05.23 um 20:41 schrieb Alex Deucher:
On Tue, May 2, 2023 at 11:22 AM Timur Kristóf wrote:
[SNIP]
In my opinion, the correct solution to those problems would be
if
the kernel could give userspace the necessary information about
a
GPU hang before a GPU reset.
The fundamental problem he
On Tue, 12 Jul 2022 at 05:33, Zack Rusin wrote:
>
> From: Zack Rusin
>
> Atomic modesetting code lacked support for specifying mouse cursor
> hotspots. The legacy kms DRM_IOCTL_MODE_CURSOR2 had support for setting
> the hotspot but the functionality was not implemented in the new atomic
> paths.
On Wed, 03 May 2023 09:48:54 +0200
Javier Martinez Canillas wrote:
> Zack Rusin writes:
>
> > On Tue, 2023-05-02 at 11:32 +0200, Javier Martinez Canillas wrote:
> >> !! External Email
> >>
> >> Daniel Vetter writes:
> >>
> >> > On Mon, Jul 11, 2022 at 11:32:39PM -0400, Zack Rusin wrote:
On 2023-05-02 14:02:59, Kuogee Hsieh wrote:
> During DSC setup, the crossbar mux need to be programmed to engage
> DSC to specified PINGPONG. Hence during tear down, the crossbar mux
> need to be reset to disengage DSC from PINGPONG. This patch add
> PINGPONG_NONE to serve as disable to reset cross
On Wed, May 3, 2023 at 9:19 AM Javier Martinez Canillas
wrote:
> Thomas Zimmermann writes:
> > Am 02.05.23 um 21:54 schrieb Sam Ravnborg:
> >> On Tue, May 02, 2023 at 03:02:21PM +0200, Thomas Zimmermann wrote:
>
> [...]
>
> >>> #include /* Why should fb driver call console
> >>> functions? be
Hi
Am 03.05.23 um 09:19 schrieb Javier Martinez Canillas:
Thomas Zimmermann writes:
Hello Thomas,
Am 02.05.23 um 21:54 schrieb Sam Ravnborg:
On Tue, May 02, 2023 at 03:02:21PM +0200, Thomas Zimmermann wrote:
[...]
#include /* Why should fb driver call console functions?
because con
Hi
Am 02.05.23 um 22:08 schrieb Sam Ravnborg:
Hi Thomas.
On Tue, May 02, 2023 at 03:02:23PM +0200, Thomas Zimmermann wrote:
Update the names of the fb_mem*() helpers to be consistent with their
regular counterparts. Hence, fb_memset() now becomes fb_memset_io(),
fb_memcpy_fromfb() now becomes
Hi Christian,
On Tue, 2 May 2023 14:41:32 +0200
Boris Brezillon wrote:
> Hi Christian,
>
> Thanks for your quick reply.
>
> On Tue, 2 May 2023 13:36:07 +0200
> Christian König wrote:
>
> > Hi Boris,
> >
> > Am 02.05.23 um 13:19 schrieb Boris Brezillon:
> > > Hello Christian, Alex,
> > >
>
Hi Thomas,
On Tue, May 2, 2023 at 3:02 PM Thomas Zimmermann wrote:
> (was: fbdev: Use regular I/O function for framebuffers)
>
> Fbdev provides helpers for framebuffer I/O, such as fb_readl(),
> fb_writel() or fb_memcpy_to_fb(). The implementation of each helper
> depends on the architecture, but
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count is calculated using slice_count. This is incorrect
as downstream uses slice per packet, which is different from
slice_count.
Slice count represents the number of soft slices per interface, and its
value will not always match that of
On 03/05/2023 04:19, Jessica Zhang wrote:
Divide the pclk rate by the compression ratio when DSC is enabled
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host
Nit: drop leading space, use singular support*.
On 2023-05-02 14:02:55, Kuogee Hsieh wrote:
> This series adds the DPU side changes to support DSC 1.2 encoder. This
> was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
> The DSI and DP parts will be pushed later on top of this change
RFC as I'm looking for comments.
For long running compute, it can be beneficial to partition the GPU memory
between cgroups, so each cgroup can use its maximum amount of memory without
interfering with other scheduled jobs. Done properly, this can alleviate the
need for eviction, which might resul
From: Tvrtko Ursulin
Skeleton controller without any functionality.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Maarten Lankhorst
---
include/linux/cgroup_drm.h| 9 ++
include/linux/cgroup_subsys.h | 4 +++
init/Kconfig | 7
kernel/cgroup/Makefile| 1
This allows the drm cgroup controller to return no space is available..
XXX: This is a hopeless simplification that changes behavior, and
returns -ENOSPC even if we could evict ourselves from the current
cgroup.
Ideally, the eviction code becomes cgroup aware, and will force eviction
from the cur
Based roughly on the rdma and misc cgroup controllers, with a lot of
the accounting code borrowed from rdma.
The interface is simple:
- populate drmcgroup_device->regions[..] name and size for each active
region.
- Call drm(m)cg_register_device()
- Use drmcg_try_charge to check if you can alloca
Add some code to implement basic support for the vram0, vram1 and stolen
memory regions.
I fear the try_charge code should probably be done inside TTM. This
code should interact with the shrinker, but for a simple RFC it's good
enough.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/xe/xe_
Adding Luben as well.
Am 03.05.23 um 10:16 schrieb Boris Brezillon:
[SNIP]
To sum-up, we shouldn't call drm_sched_{start,stop,resubmit_jobs}().
After the discussion I had with Matthew yesterday on IRC, I
realized there was no clear agreement on this. Matthew uses those 3
helpers in the Xe driv
On Sat, Apr 15, 2023 at 11:51:28PM +0200, Javier Martinez Canillas wrote:
> Uwe Kleine-König writes:
>
> > On Wed, Mar 22, 2023 at 12:06:55PM +0300, Dan Carpenter wrote:
> >> The devm_drm_dev_alloc() function returns error pointers. It never
> >> returns NULL. Fix the check.
> >>
> >> Fixes: c
On Wed, May 3, 2023, at 10:12, Thomas Zimmermann wrote:
> Am 03.05.23 um 09:19 schrieb Javier Martinez Canillas:
>> Thomas Zimmermann writes:
There are countless examples where the above are not followed,
but to my best understanding the above it the preferred way to do it.
>>>
>>>
Hi, Maarten
On 5/3/23 10:34, Maarten Lankhorst wrote:
This allows the drm cgroup controller to return no space is available..
XXX: This is a hopeless simplification that changes behavior, and
returns -ENOSPC even if we could evict ourselves from the current
cgroup.
Ideally, the eviction code b
On 2023-05-03 11:11, Thomas Hellström wrote:
Hi, Maarten
On 5/3/23 10:34, Maarten Lankhorst wrote:
This allows the drm cgroup controller to return no space is available..
XXX: This is a hopeless simplification that changes behavior, and
returns -ENOSPC even if we could evict ourselves from th
On Wed, 3 May 2023 10:47:43 +0200
Christian König wrote:
> Adding Luben as well.
>
> Am 03.05.23 um 10:16 schrieb Boris Brezillon:
> > [SNIP]
> >> To sum-up, we shouldn't call drm_sched_{start,stop,resubmit_jobs}().
> > After the discussion I had with Matthew yesterday on IRC, I
> > realized
On Fri, Apr 28, 2023 at 2:26 PM Thomas Zimmermann wrote:
> Push the test for info->screen_base from fb_read() and fb_write() into
> the implementations of struct fb_ops.{fb_read,fb_write}. In cases where
> the driver operates on info->screen_buffer, test this field instead.
>
> While bothi fields,
On Sun, 16 Apr 2023, Daniel Vetter wrote:
> On Fri, Apr 14, 2023 at 07:52:12PM +0900, Tetsuo Handa wrote:
>> On 2023/04/14 19:13, Jani Nikula wrote:
>> > On Fri, 14 Apr 2023, Tetsuo Handa
>> > wrote:
>> >> On 2023/03/15 19:47, Luca Coelho wrote:
>> >>> On Tue, 2023-03-14 at 20:21 +0900, Tetsuo H
Hi Christian,
Am Mittwoch, dem 03.05.2023 um 10:47 +0200 schrieb Christian König:
> Adding Luben as well.
>
> Am 03.05.23 um 10:16 schrieb Boris Brezillon:
> > [SNIP]
> > > To sum-up, we shouldn't call drm_sched_{start,stop,resubmit_jobs}().
> > After the discussion I had with Matthew yesterday o
Smatch complains that these are not initialized if get_cntl_version()
fails but we still print them in the debug message. Not the end of
the world, but true enough. Let's just initialize them to a dummy value
to make the checker happy.
Signed-off-by: Dan Carpenter
---
drivers/accel/qaic/qaic_d
On Wed, May 03, 2023 at 10:36:42AM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 02, 2023 at 05:38:57PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The MST DSC code has a myriad of issues:
> > - Platform checks are wrong (MST+DSC is TGL+ only IIRC)
> > - Return values of .mode_
When hactive is not aligned to 8 pixels, it is aligned accordingly and
hfront porch needs to be reduced the same amount. Unfortunately the front
porch is set to the difference rather than reducing it. There are some
Samsung TVs which can't cope with a front porch of instead of 70.
Fixes: 94dfec48f
On Mon, Apr 17, 2023 at 11:02:13PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The corgi_lcd_limit_intensity() function is called from platform
> and defined in a driver, but the driver does not see the declaration:
>
> drivers/video/backlight/corgi_lcd.c:434:6: error: no previous protot
From: Ville Syrjälä
Track DP enhanced framing properly in the crtc state instead
of relying just on the cached DPCD everywhere, and hook it
up into the state check and dump.
v2: Actually set enhanced_framing in .compute_config()
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4
Hi Lucas,
Am 03.05.23 um 12:28 schrieb Lucas Stach:
Hi Christian,
Am Mittwoch, dem 03.05.2023 um 10:47 +0200 schrieb Christian König:
Adding Luben as well.
Am 03.05.23 um 10:16 schrieb Boris Brezillon:
[SNIP]
To sum-up, we shouldn't call drm_sched_{start,stop,resubmit_jobs}().
After the di
Changes in v2:
- Added explicit inclusion of linux/bitfield.h in patch [06/11]
This series adds support for GAMMA IP requiring and/or supporting
a 12-bits LUT using a slightly different register layout and programming
sequence for multiple LUT banks: this IP version is currently found
on a number
Invert the check for state->gamma_lut and move it at the beginning
of the function to reduce indentation: this prepares the code for
keeping readability on later additions.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp
Newer SoCs support a bigger Gamma LUT table: wire up a callback
to retrieve the correct LUT size for each different Gamma IP.
Co-developed-by: Jason-JH.Lin
Signed-off-by: Jason-JH.Lin
[Angelo: Rewritten commit message/description + porting]
Signed-off-by: AngeloGioacchino Del Regno
---
driver
From: "Jason-JH.Lin"
Adjust the parameters in mtk_drm_gamma_set_common()
- add (struct device *dev) to get lut_diff from gamma's driver data
- remove (bool lut_diff) and use false as default value in the function
Signed-off-by: Jason-JH.Lin
Signed-off-by: AngeloGioacchino Del Regno
---
d
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after
programming the actual table to avoid potential visual glitches during
table modification.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 -
1 file changed, 8 insertions(+
Use drm_color_lut_extract() to avoid open-coding the bits reduction
calculations for each color channel and use a struct drm_color_lut
to temporarily store the information instead of an array of u32.
Also, slightly improve the precision of the HW LUT calculation in the
LUT DIFF case by performing
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
While at it, also add a definition for LUT_BITS_DEFAULT.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++-
1 file
New SoCs, like MT8195, not only may support bigger lookup tables, but
have got a different register layout to support bigger precision:
support specifying the number of `lut_bits` for each SoC and use it
in mtk_gamma_set_common() to perform the right calculation.
Signed-off-by: AngeloGioacchino De
Disable relay mode at the end of LUT programming to make sure that the
processed image goes through.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
b/drive
Newer Gamma IP have got multiple LUT banks: support specifying the
size of the LUT banks and handle bank-switching before programming
the LUT in mtk_gamma_set_common() in preparation for adding support
for MT8195 and newer SoCs.
Suggested-by: Jason-JH.Lin
[Angelo: Refactored original commit]
Sign
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu
Add support for 12-bit gamma lookup tables and introduce the first
user for it: MT8195.
While at it, also reorder the variables in mtk_gamma_set_common()
and rename `lut_base` to `lut0_base` to improve readability.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_
On Wed, May 03, 2023 at 02:07:04PM +0300, Ville Syrjälä wrote:
> On Wed, May 03, 2023 at 10:36:42AM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 02, 2023 at 05:38:57PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > The MST DSC code has a myriad of issues:
> > > - Platform
On Tue, May 2, 2023 at 4:26 PM Ulf Hansson wrote:
> On Sun, 30 Apr 2023 at 11:22, Linus Walleij wrote:
> > Fixes: 92bf78b33b0b ("gpio: omap: use dynamic allocation of base")
> > Signed-off-by: Linus Walleij
>
> This looks like it's best funneled through the soc maintainer's tree(s),
> right?
>
Am Mittwoch, dem 03.05.2023 um 13:40 +0200 schrieb Christian König:
> Hi Lucas,
>
> Am 03.05.23 um 12:28 schrieb Lucas Stach:
> > Hi Christian,
> >
> > Am Mittwoch, dem 03.05.2023 um 10:47 +0200 schrieb Christian König:
> > > Adding Luben as well.
> > >
> > > Am 03.05.23 um 10:16 schrieb Boris B
On 02/05/2023 05:11, fei.y...@intel.com wrote:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. I
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a
macro") says, flush_scheduled_work() is dangerous and will be forbidden.
i915 became the last flush_scheduled_work() user, but developers cannot
find time for auditing which work items does this flush_scheduled_work()
need to
Hi
Am 03.05.23 um 11:51 schrieb Geert Uytterhoeven:
On Fri, Apr 28, 2023 at 2:26 PM Thomas Zimmermann wrote:
Push the test for info->screen_base from fb_read() and fb_write() into
the implementations of struct fb_ops.{fb_read,fb_write}. In cases where
the driver operates on info->screen_buffer
Merged, thanks!
Am 02.05.23 um 14:59 schrieb Dan Carpenter:
The "unode" pointer cannot be NULL here and checking for it causes
Smatch warnings:
drivers/gpu/drm/udl/udl_main.c:259 udl_get_urb_locked()
warn: can 'unode' even be NULL?
Fortunately, it's just harmless dead code which can be
Hi
Am 02.05.23 um 22:06 schrieb Arnd Bergmann:
On Tue, May 2, 2023, at 15:02, Thomas Zimmermann wrote:
Implement framebuffer I/O helpers, such as fb_read*() and fb_write*(),
in the architecture's header file or the generic one.
The common case has been the use of regular I/O functions, such a
Am 03.05.23 um 15:10 schrieb Lucas Stach:
Am Mittwoch, dem 03.05.2023 um 13:40 +0200 schrieb Christian König:
Hi Lucas,
Am 03.05.23 um 12:28 schrieb Lucas Stach:
Hi Christian,
Am Mittwoch, dem 03.05.2023 um 10:47 +0200 schrieb Christian König:
Adding Luben as well.
Am 03.05.23 um 10:16 schr
Hi Thomas,
On Wed, May 3, 2023 at 4:30 PM Thomas Zimmermann wrote:
> Am 03.05.23 um 11:51 schrieb Geert Uytterhoeven:
> > On Fri, Apr 28, 2023 at 2:26 PM Thomas Zimmermann
> > wrote:
> >> Push the test for info->screen_base from fb_read() and fb_write() into
> >> the implementations of struct f
On Wed, May 3, 2023, at 16:55, Thomas Zimmermann wrote:
> Am 02.05.23 um 22:06 schrieb Arnd Bergmann:
>> It's probably safe to deal with all the above by either adding
>> architecture specific overrides to the current version, or
>> by doing the semantic changes before the move to asm/fb.h, but
>>
Am 2023-05-03 um 03:59 schrieb Christian König:
Am 02.05.23 um 20:41 schrieb Alex Deucher:
On Tue, May 2, 2023 at 11:22 AM Timur Kristóf
wrote:
[SNIP]
In my opinion, the correct solution to those problems would be
if
the kernel could give userspace the necessary information about
a
GPU hang b
On 02.05.23 03:07, Adam Ford wrote:
> From: Lucas Stach
>
> Scale the blanking packet sizes to match the ratio between HS clock
> and DPI interface clock. The controller seems to do internal scaling
> to the number of active lanes, so we don't take those into account.
>
> Signed-off-by: Lucas St
On 02.05.23 03:07, Adam Ford wrote:
> According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
> and max values for M and the frequency range for the VCO_out
> calculator were incorrect. This information was contradicted in other
> parts of the mini, nano and plus manuals. After reac
On 02.05.23 03:07, Adam Ford wrote:
> Make the pll-clock-frequency optional. If it's present, use it
> to maintain backwards compatibility with existing hardware. If it
> is absent, read clock rate of "sclk_mipi" to determine the rate.
>
> Signed-off-by: Adam Ford
> Tested-by: Chen-Yu Tsai
Te
On 02.05.23 03:07, Adam Ford wrote:
> In order to support variable DPHY timings, it's necessary
> to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config
> can be used to determine the nominal values for a given resolution
> and refresh rate.
>
> Signed-off-by: Adam Ford
This fixes t
Am 03.05.23 um 17:08 schrieb Felix Kuehling:
Am 2023-05-03 um 03:59 schrieb Christian König:
Am 02.05.23 um 20:41 schrieb Alex Deucher:
On Tue, May 2, 2023 at 11:22 AM Timur Kristóf
wrote:
[SNIP]
In my opinion, the correct solution to those problems would be
if
the kernel could give userspac
On 03/05/2023 09:34, Maarten Lankhorst wrote:
Based roughly on the rdma and misc cgroup controllers, with a lot of
the accounting code borrowed from rdma.
The interface is simple:
- populate drmcgroup_device->regions[..] name and size for each active
region.
- Call drm(m)cg_register_device(
On 2023-05-03 17:31, Tvrtko Ursulin wrote:
On 03/05/2023 09:34, Maarten Lankhorst wrote:
Based roughly on the rdma and misc cgroup controllers, with a lot of
the accounting code borrowed from rdma.
The interface is simple:
- populate drmcgroup_device->regions[..] name and size for each activ
On 02.05.23 03:07, Adam Ford wrote:
> The DPHY timings are currently hard coded. Since the input
> clock can be variable, the phy timings need to be variable
> too. Add an additional variable to the driver data to enable
> this feature to prevent breaking boards that don't support it.
>
> The phy
On 02.05.23 03:07, Adam Ford wrote:
> The high-speed clock is hard-coded to the burst-clock
> frequency specified in the device tree. However, when
> using devices like certain bridge chips without burst mode
> and varying resolutions and refresh rates, it may be
> necessary to set the high-speed
On 02.05.23 03:07, Adam Ford wrote:
> The blanking calculation currently uses burst_clk_rate for calculating
> the settings. Since it's possible to use this in non-burst mode, it's
> possible that where won't be burst_clk_rate. Instead, cache the
"possible that burst_clk_rate is 0"
> clock rate
On Wed, May 3, 2023 at 10:52 AM Frieder Schrempf
wrote:
>
> On 02.05.23 03:07, Adam Ford wrote:
> > The blanking calculation currently uses burst_clk_rate for calculating
> > the settings. Since it's possible to use this in non-burst mode, it's
> > possible that where won't be burst_clk_rate. Ins
From: Frieder Schrempf
This patchset contains a proposal to fix the initialization flow for
the display pipeline used on our i.MX8MM Kontron boards:
i.MX8MM LCDIF -> i.MX8MM DSIM -> TI SN65DSI84 -> 7" LVDS Panel
Without these changes the display works most of the time, but fails
to come up oc
From: Frieder Schrempf
According to the documentation [1] the proper enable flow is:
1. Enable DSI link and keep data lanes in LP-11 (stop state)
2. Disable stop state to bring data lanes into HS mode
Currently we do this all at once within enable(), which doesn't
allow to meet the requirements
From: Frieder Schrempf
The datasheet describes the following initialization flow including
minimum delay times between each step:
1. DSI data lanes need to be in LP-11 and the clock lane in HS mode
2. toggle EN signal
3. initialize registers
4. enable PLL
5. soft reset
6. enable DSI stream
7. ch
On Mon, Apr 24, 2023 at 3:17 PM Adam Ford wrote:
>
> On Mon, Apr 24, 2023 at 4:03 AM Jagan Teki wrote:
> >
> > On Sun, Apr 23, 2023 at 5:42 PM Adam Ford wrote:
> > >
> > > From: Lucas Stach
> > >
> > > Scale the blanking packet sizes to match the ratio between HS clock
> > > and DPI interface c
On Mon, May 1, 2023 at 8:38 AM Dmitry Osipenko <
dmitry.osipe...@collabora.com> wrote:
> On 4/16/23 14:52, Dmitry Osipenko wrote:
> > We have multiple Vulkan context types that are awaiting for the addition
> > of the sync object DRM UAPI support to the VirtIO-GPU kernel driver:
> >
> > 1. Venus
GPU hangs are pretty common post-bringup. They are not common per user, but
if we gather all hangs from all users, we can have lots and lots of them.
GPU hangs are indeed not very debuggable. There are however some things we
can do:
- Identify the hanging IB by its VA (the kernel should know it)
-
On 5/3/2023 1:33 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Divide the pclk rate by the compression ratio when DSC is enabled
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(
WRITE_DATA with ENGINE=PFP will execute the packet on the frontend engine,
while ENGINE=ME will execute the packet on the backend engine.
Marek
On Wed, May 3, 2023 at 1:08 PM Marek Olšák wrote:
> GPU hangs are pretty common post-bringup. They are not common per user,
> but if we gather all hang
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count is calculated using slice_count. This is incorrect
as downstream uses slice per packet, which is different from
slice_count.
Slice count represents the number of soft slices per inter
On 5/2/2023 3:42 PM, Dmitry Baryshkov wrote:
On 03/05/2023 00:02, Kuogee Hsieh wrote:
At legacy chipsets, it required DPU_PINGPONG_DSC bit be set to indicate
pingpong ops functions are required to complete DSC data path setup if
this chipset has DSC hardware block presented. This patch add
DPU
On 5/3/2023 1:03 AM, Marijn Suijten wrote:
On 2023-05-02 14:02:59, Kuogee Hsieh wrote:
During DSC setup, the crossbar mux need to be programmed to engage
DSC to specified PINGPONG. Hence during tear down, the crossbar mux
need to be reset to disengage DSC from PINGPONG. This patch add
PINGPONG
LGTM:
Reviewed-by: Alan Previn
On Fri, 2023-04-28 at 11:56 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Don't use 'xe_lp*' prefixes for register lists that are common with
> Gen8.
>
> Don't add Xe only GSC registers to pre-Xe devices that don't
> even have a GSC engine.
>
Hi
Am 03.05.23 um 17:02 schrieb Geert Uytterhoeven:
Hi Thomas,
On Wed, May 3, 2023 at 4:30 PM Thomas Zimmermann wrote:
Am 03.05.23 um 11:51 schrieb Geert Uytterhoeven:
On Fri, Apr 28, 2023 at 2:26 PM Thomas Zimmermann wrote:
Push the test for info->screen_base from fb_read() and fb_write()
On 5/2/2023 11:51 AM, Hamza Mahfooz wrote:
As made mention of, in commit 9128e6babf10 ("drm/amdgpu: fix
amdgpu_irq_put call trace in gmc_v10_0_hw_fini") and commit c094b8923bdd
("drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini"). It
is meaningless to call amdgpu_irq_put() for gmc
On Sun, Apr 30, 2023 at 11:22:16AM +0200, Linus Walleij wrote:
> The ADS7846 has some limited support for using GPIO descriptors,
> let's convert it over completely and fix all users to provide
> GPIOs in descriptor tables.
>
> The Nokia 770 now has dynamic allocation of IRQ numbers, so this
> nee
Em 03/05/2023 14:08, Marek Olšák escreveu:
GPU hangs are pretty common post-bringup. They are not common per user,
but if we gather all hangs from all users, we can have lots and lots of
them.
GPU hangs are indeed not very debuggable. There are however some things
we can do:
- Identify the h
On 5/2/2023 2:42 PM, Dmitry Baryshkov wrote:
On 03/05/2023 00:03, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both sh
On 03/05/2023 20:45, Kuogee Hsieh wrote:
On 5/2/2023 3:42 PM, Dmitry Baryshkov wrote:
On 03/05/2023 00:02, Kuogee Hsieh wrote:
At legacy chipsets, it required DPU_PINGPONG_DSC bit be set to indicate
pingpong ops functions are required to complete DSC data path setup if
this chipset has DSC har
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