On Tue, Sep 13, 2022 at 07:35:15AM +0100, Doug Anderson wrote:
> Hi,
>
> On Mon, Sep 12, 2022 at 7:10 PM Dmitry Baryshkov
> wrote:
> >
> > On 12/09/2022 18:40, Johan Hovold wrote:
> > > Device-managed resources allocated post component bind must be tied to
> > > the lifetime of the aggregate DRM
On Mon, Sep 12, 2022 at 04:55:58PM -0500, Steev Klimaszewski wrote:
>
> On 9/12/22 1:10 PM, Dmitry Baryshkov wrote:
> > On 12/09/2022 18:40, Johan Hovold wrote:
> >> Device-managed resources allocated post component bind must be tied to
> >> the lifetime of the aggregate DRM device or they will no
On Mon, Sep 12, 2022 at 08:52:44PM +0300, Dmitry Baryshkov wrote:
> On 12/09/2022 18:40, Johan Hovold wrote:
> > The bridge counter was never reset when tearing down the DRM device so
> > that stale pointers to deallocated structures would be accessed on the
> > next tear down (e.g. after a second
Hi
Am 12.09.22 um 19:16 schrieb Ville Syrjälä:
On Mon, Sep 12, 2022 at 04:22:49PM +0200, Thomas Zimmermann wrote:
Hi
Am 12.09.22 um 14:34 schrieb Ville Syrjälä:
On Mon, Sep 12, 2022 at 02:05:36PM +0200, Thomas Zimmermann wrote:
Hi
Am 12.09.22 um 13:18 schrieb Ville Syrjälä:
On Mon, Sep 12,
On Mon, Sep 12, 2022 at 08:55:55PM +0300, Dmitry Baryshkov wrote:
> On 12/09/2022 18:40, Johan Hovold wrote:
> > Add the missing sanity checks on the bridge counter to avoid corrupting
> > data beyond the fixed-sized bridge array in case there are ever more
> > than eight bridges.
> >
> > a3376e3e
On Mon, Sep 12, 2022 at 09:06:28PM +0300, Dmitry Baryshkov wrote:
> On 12/09/2022 18:40, Johan Hovold wrote:
> > Drop the overly defensive modeset sanity checks of function parameters
> > which have already been checked or used by the callers.
> >
> > Signed-off-by: Johan Hovold
>
> Again, pleas
On Tue, Sep 13, 2022 at 01:49:40AM +0800, butt3rflyh4ck wrote:
> Hi, there is a divide error bug in framebuffer_check in
> drivers/gpu/drm/drm_framebuffer.c in the latest kernel.
> we can trigger it via drm_mode_addfb2 IOCTL.
> The call trace is drm_mode_addfb2 -> drm_internal_framebuffer_create
>
Hi
Am 07.09.22 um 06:16 schrieb Wang Yugui:
Hi,
Am 02.09.22 um 07:52 schrieb Wang Yugui:
Hi,
mgag200 broken on kernel-6.0-rc3 on DELL/T620.
See the attachementment file for the graph output.
Thanks for reporting the bug. We recently refactored some code of the driver.
Can you bisect to t
This symbol is not used outside of dcn32_dio_stream_encoder.c, so marks
it static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dio_stream_encoder.c:63:6:
warning: no previous prototype for
‘enc32_stream_encoder_dvi_set_stream_attribute’.
Link:https://bugzilla.openanolis.cn/show_bug.cgi
These two functions are not used outside the function dcn32_mpc.c, so the
modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:704:6: warning: no
previous prototype for ‘mpc32_program_shaper’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_mpc.c:900:
This symbol is not used outside of dcn32_dpp.c, so marks it static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dpp.c:34:6: warning: no
previous prototype for ‘dscl32_calc_lb_num_partitions’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2118
Reported-by: Abaci Robot
Signed-off-
The function copy_stream_update_to_stream() is defined in the notif.c
file, but not called elsewhere, so delete this unused function.
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2852:6: warning: no previous
prototype for ‘dc_reset_state’.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?
These two functions are not used outside the function
dcn32_dio_link_encoder.c, so the modification is defined as static.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_dio_link_encoder.c:121:6:
warning: no previous prototype for ‘dcn32_link_encoder_is_in_alt_mode’.
drivers/gpu/drm/amd/amdg
On 12/09/2022 17:44, Adrián Larumbe wrote:
> Building Mesa's Perfetto requires including the panfrost drm uAPI header in
> C++ code, but the C++ compiler requires anonymous unions to have only
> public non-static data members.
>
> Commit 730c2bf4ad39 ("drm/panfrost: Add support for devcoredump")
>
From: allen chen
This series let driver can read properties from dt to restrict dp output
bandwidth.
allen chen (2):
dt-bindings: it6505: add properties to restrict output bandwidth
drm/bridge: add it6505 driver to read data-lanes and
max-pixel-clock-khz from dt
.../bindings/display/br
From: allen chen
Add properties to restrict dp output data-lanes and clock.
Signed-off-by: Pin-Yen Lin
Signed-off-by: Allen Chen
---
.../devicetree/bindings/display/bridge/ite,it6505.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
From: allen chen
Add driver to read data-lanes and max-pixel-clock-khz from dt property
to restrict output bandwidth.
Signed-off-by: Allen chen
Signed-off-by: Pin-yen Lin
---
drivers/gpu/drm/bridge/ite-it6505.c | 35 ++---
1 file changed, 32 insertions(+), 3 deletions(
The bridge counter was never reset when tearing down the DRM device so
that stale pointers to deallocated structures would be accessed on the
next tear down (e.g. after a second late bind deferral).
Given enough bridges and a few probe deferrals this could currently also
lead to data beyond the br
Add the missing sanity check on the bridge counter to avoid corrupting
data beyond the fixed-sized bridge array in case there are ever more
than eight bridges.
Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable
and disable")
Cc: sta...@vger.kernel.org # 5.17
Signed-
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This is specifically true for the DP IRQ, which will otherwise remain
requested so that the nex
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This is specifically true for the HDMI IRQ, which will otherwise remain
requested so that the n
Add the missing sanity check on the bridge counter to avoid corrupting
data beyond the fixed-sized bridge array in case there are ever more
than eight bridges.
Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
Cc: sta...@vger.kernel.org # 4.1
Signed-off-by: Johan Hovold
---
Add the missing sanity check on the bridge counter to avoid corrupting
data beyond the fixed-sized bridge array in case there are ever more
than eight bridges.
Fixes: a3376e3ec81c ("drm/msm: convert to drm_bridge")
Cc: sta...@vger.kernel.org # 3.12
Signed-off-by: Johan Hovold
---
drivers/gp
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This can lead resource leaks or failure to bind the aggregate device
when binding is later retr
The MSM DRM driver is currently broken in multiple ways with respect to
probe deferral. Not only does the driver currently fail to probe again
after a late deferral, but due to a related use-after-free bug this also
triggers NULL-pointer dereferences.
These bugs are not new but have become critica
Drop the overly defensive modeset sanity checks of function parameters
which have already been checked or used by the callers.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Johan Hovold
---
drivers/gpu/drm/msm/dsi/dsi.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/dr
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This can lead resource leaks or failure to bind the aggregate device
when binding is later retr
Drop the overly defensive modeset sanity checks of function parameters
which have already been checked or used by the callers.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Johan Hovold
---
drivers/gpu/drm/msm/dp/dp_display.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --gi
On Mon, Sep 12, 2022 at 09:50:26PM +0200, Danilo Krummrich wrote:
> Hi Liviu,
Hi Danilo,
>
> Thanks for having a look!
>
> This is not about this patch, it's about patch 3/7 "drm/arm/hdlcd: crtc: use
> drmm_crtc_init_with_planes()".
Agree! However, this is the patch that removes the .destroy h
On 13/09/2022 10:48, allen wrote:
> From: allen chen
>
> Add properties to restrict dp output data-lanes and clock.
>
> Signed-off-by: Pin-Yen Lin
> Signed-off-by: Allen Chen
> ---
> .../devicetree/bindings/display/bridge/ite,it6505.yaml | 10 ++
> 1 file changed, 10 insertions(+)
Th
On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
> Currently damage clips handling is broken for planes when using big
> framebuffer + offset in case kms driver adjusts drm_plane_state.src
> coords. This is because damage clips are using coords relative to
> original coords from user
> Wiadomość napisana przez Michael Riesch w
> dniu 13.09.2022, o godz. 08:55:
>
> Hi,
>
> On 9/12/22 20:02, Chris Morgan wrote:
>> From: Chris Morgan
>
> Cc: Sascha -> any thoughts on this one?
>
> Best regards,
> Michael
>
>> If I use more than one VP to output on an RK3566 based device
Provides a default plane state check handler for primary planes that are a
fullscreen scanout buffer and whose state scale and position can't change.
There are some drivers that duplicate this logic in their helpers, such as
simpledrm and ssd130x. Factor out this common code into a plane helper an
On Thu, Sep 01, 2022 at 12:15:24PM +0300, Dmitry Baryshkov wrote:
> Johan Hovold has reported that returning a probe deferral from the
> msm_dp_modeset_init() can cause issues because the IRQ is not freed
> properly. This (compile-tested only) series tries to fix the issue by
> moving devm_request_
September 9, 2022 at 1:59 PM, "Thomas Zimmermann" mailto:tzimmerm...@suse.de?to=%22Thomas%20Zimmermann%22%20%3Ctzimmermann%40suse.de%3E
> wrote:
>
> Open-code drm_plane_init() and remove the function from DRM. The
> implementation of drm_plane_init() is a simple wrapper around a call
> to drm_un
Hi,
[+Cc Lee Jones, DRI devel]
On Tue, Aug 09, 2022 at 10:05:00PM -0500, Bjorn Andersson wrote:
> The Qualcomm Snapdragon-based Lenovo Yoga C630 has some sort of EC
> providing AC-adapter and battery status, as well as USB Type-C altmode
> notifications for Displayport operation.
>
> The Yoga C6
On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
> On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
> > Currently damage clips handling is broken for planes when using big
> > framebuffer + offset in case kms driver adjusts drm_plane_state.src
> > coords. This is because damag
Hi
Am 13.09.22 um 12:47 schrieb Hogander, Jouni:
On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
Currently damage clips handling is broken for planes when using big
framebuffer + offset in case kms driver adjusts drm_plane
Am 13.09.22 um 12:54 schrieb Thomas Zimmermann:
Hi
Am 13.09.22 um 12:47 schrieb Hogander, Jouni:
On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
Currently damage clips handling is broken for planes when using big
frameb
On Fri, Sep 09, 2022 at 07:59:06PM +0900, Gwan-gyeong Mun wrote:
> It moves overflows_type utility macro into overflow header from i915_utils
> header. The overflows_type can be used to catch the truncaion (overflow)
> between different data types. And it adds check_assign() macro which
> performs
On Fri, Sep 09, 2022 at 07:59:07PM +0900, Gwan-gyeong Mun wrote:
> It adds assert_type and assert_typable macros to catch type mis-match while
> compiling. The existing typecheck() macro outputs build warnings, but the
> newly added assert_type() macro uses the _Static_assert() keyword (which is
>
Hi,
This patchset contains a new Linux* Kernel Driver for Intel® VPUs.
VPU stands for Versatile Processing Unit and it is an AI inference accelerator
integrated with Intel non-server CPUs starting from 14th generation.
VPU enables efficient execution of Deep Learning applications
like object dete
ver);
+}
+
+module_init(ivpu_init);
+module_exit(ivpu_fini);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL and additional rights");
+MODULE_VERSION(DRIVER_VERSION_STR);
diff --git a/drivers/gpu/drm/ivpu/ivpu_drv.h b/drivers/g
Adds four types of GEM-based BOs for the VPU:
- shmem
- userptr
- internal
- prime
All types are implemented as struct ivpu_bo, based on
struct drm_gem_object. VPU address is allocated when buffer is created
except for imported prime buffers that allocate it in BO_INFO IOCTL due
to missing
The IPC driver is used to send and receive messages to/from firmware
running on the VPU.
The only supported IPC message format is Job Submission Model (JSM)
defined in vpu_jsm_api.h header.
Signed-off-by: Andrzej Kacprowski
Signed-off-by: Krystian Pradzynski
Signed-off-by: Jacek Lawrynowicz
--
drivers/gpu/drm/ivpu/ivpu_drv.h
+++ b/drivers/gpu/drm/ivpu/ivpu_drv.h
@@ -14,6 +14,8 @@
#include
#include
+#include "ivpu_mmu_context.h"
+
#define DRIVER_NAME "intel_vpu"
#define DRIVER_DESC "Driver for Intel Versatile Processing Unit (VPU)"
#define DRIVER
Read, parse and boot VPU firmware image.
Signed-off-by: Andrzej Kacprowski
Signed-off-by: Krystian Pradzynski
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 1 +
drivers/gpu/drm/ivpu/ivpu_drv.c | 122 +++-
drivers/gpu/drm/ivpu/ivpu_drv.h | 10 +
drive
Each of the user contexts has two command queues, one for compute engine
and one for the copy engine. Command queues are allocated and registered
in the device when the first job (command buffer) is submitted from
the user space to the VPU device. The userspace provides a list of
GEM buffer object
- Implement cold and warm firmware boot flows
- Add hang recovery support
- Add runtime power management support
Signed-off-by: Krystian Pradzynski
Signed-off-by: Jacek Lawrynowicz
---
drivers/gpu/drm/ivpu/Makefile | 3 +-
drivers/gpu/drm/ivpu/ivpu_drv.c| 34 ++-
drivers/gpu/d
On Tue, Sep 13, 2022 at 12:56:49PM +0200, Thomas Zimmermann wrote:
>
>
> Am 13.09.22 um 12:54 schrieb Thomas Zimmermann:
> > Hi
> >
> > Am 13.09.22 um 12:47 schrieb Hogander, Jouni:
> >> On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
> >>> On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni
Hi,
On Tue, Sep 13, 2022 at 9:58 AM Johan Hovold wrote:
>
> Device-managed resources allocated post component bind must be tied to
> the lifetime of the aggregate DRM device or they will not necessarily be
> released when binding of the aggregate device is deferred.
>
> This can lead resource lea
Applied. Thanks!
On Mon, Sep 12, 2022 at 10:12 PM Rafael Mendonca wrote:
>
> If construction of the array of work queues to handle hpd_rx_irq offload
> work fails, we need to unwind. Destroy all the created workqueues and
> the allocated memory for the hpd_rx_irq_offload_work_queue struct array.
Applied the series. Thanks!
Alex
On Tue, Sep 13, 2022 at 4:39 AM Jiapeng Chong
wrote:
>
> The function copy_stream_update_to_stream() is defined in the notif.c
> file, but not called elsewhere, so delete this unused function.
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2852:6: warnin
Applied. Thanks!
On Sun, Sep 11, 2022 at 11:23 PM wrote:
>
> From: Xu Panda
>
> soc15_common.h is included more than once.
>
> Reported-by: Zeal Robot
> Signed-off-by: Xu Panda
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a
From: Mikko Perttunen
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not a
From: Mikko Perttunen
Add support for the Tegra234 version of NVDEC to the NVDEC driver.
This version sports a RISC-V controller and requires a few additional
clocks. After firmware has been loaded, the behavior is, however,
backwards compatible.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/
From: Mikko Perttunen
Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.
Signed-off-by: Mikko Perttunen
Acked-by: Krzysztof Kozlowski
---
include/dt-bindings/clock/tegra234-clock.h | 4
include/dt-bindings/memory/tegra234-mc.h | 3 +++
inc
From: Mikko Perttunen
Add entries for NVDEC to the Tegra234 SID table.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 0cd3f97e7e49..d6b4614f968f 100644
--- a
From: Mikko Perttunen
NVDEC on Tegra234 requires multiple clocks. Add support for that.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/nvdec.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers
From: Mikko Perttunen
v2:
* Updated patches 1,3 based on comments
* Added Acked-by to patch 2
Original message:
Hi all,
this series adds support for the HW video decoder, NVDEC,
on Tegra234 (Orin). The main change is a switch from Falcon
to RISC-V for the internal microcontroller, which brings
From: Mikko Perttunen
On Tegra234 NVDEC firmware is loaded from a secure carveout, where it
has been loaded by a bootloader. When booting NVDEC, we need to tell it
the address of this firmware, which we can determine by checking the
starting address of the carveout. As such, add an MC API to quer
From: Mikko Perttunen
Add helper code for booting RISC-V based engines where firmware is
located in a carveout.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/Makefile | 3 +-
drivers/gpu/drm/tegra/riscv.c | 106 +
drivers/gpu/drm/tegra/riscv.h |
From: Mikko Perttunen
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the memo
On Thu, Sep 8, 2022 at 4:00 PM Jagan Teki wrote:
> Jadard JD9365DA-H3 is WUXGA MIPI DSI panel and it support TFT
> dot matrix LCD with 800RGBx1280 dots at maximum.
>
> Add support for it.
>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Jagan Teki
I wrote to Jadard and asked for a datas
On 2022-09-13 05:33, Javier Martinez Canillas wrote:
> Provides a default plane state check handler for primary planes that are a
> fullscreen scanout buffer and whose state scale and position can't change.
>
Even though this might be how some drivers are handling the primary
plane this assump
The title needs a spelling fix: /sched:
I'd also spell out "rq" as it is in a title.
The patch has a number of warnings from scripts/checkpatch.pl.
I suggest it be run through checkpatch.pl before submitting.
Inlined:
On 2022-09-02 22:48, Andrey Grodzovsky wrote:
> Poblem: Given many entities co
On Thu, 11 Aug 2022, Ankit Nautiyal wrote:
> Replace multiple log lines with a single log line at the end of
> parsing HF-VSDB. Also use drm_dbg_kms instead of DRM_DBG_KMS, and
> add log for DSC1.2 support.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/drm_edid.c | 21 +--
On Thu, 11 Aug 2022, Ankit Nautiyal wrote:
> Move the DSC parsing logic into separate function.
>
> Signed-off-by: Ankit Nautiyal
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_edid.c | 128 -
> 1 file changed, 69 insertions(+), 59 deletions(-)
>
> di
On Thu, 11 Aug 2022, Ankit Nautiyal wrote:
> DSC capabilities are given in bytes 11-13 of VSDB (i.e. bytes 8-10 of
> SCDS). Since minimum length of Data block is 7, all bytes greater than 7
> must be read only after checking the length of the data block.
>
> This patch adds check for data block le
Hi Linus,
On Tue, 13 Sept 2022 at 19:12, Linus Walleij wrote:
>
> On Thu, Sep 8, 2022 at 4:00 PM Jagan Teki wrote:
>
> > Jadard JD9365DA-H3 is WUXGA MIPI DSI panel and it support TFT
> > dot matrix LCD with 800RGBx1280 dots at maximum.
> >
> > Add support for it.
> >
> > Cc: dri-devel@lists.free
From: Greg Kroah-Hartman
commit cbfac7fa491651c57926c99edeb7495c6c1aeac2 upstream.
When calling debugfs_lookup() the result must have dput() called on it,
otherwise the memory will leak over time. Fix this up by properly
calling dput().
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc:
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (4):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Fix intel_dp_mst_compute_link_config
drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate
function
drm/i915: Add DSC support to MST pa
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
We currently always exit that bpp loop because
drm_dp_atomic_find_vcpi_slots doesn't care if we actually
can fit those or not.
I think that wasn't the initial intention here, especially when
we keep trying with lower bpps, we are supposed to keep trying
until we actually find some _working_ configu
We would be using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
v2: Fix pbn_div calculation - shouldn't matter if its DSC or not.
v3: FIx rebase conflict, constant_
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
From: Greg Kroah-Hartman
commit cbfac7fa491651c57926c99edeb7495c6c1aeac2 upstream.
When calling debugfs_lookup() the result must have dput() called on it,
otherwise the memory will leak over time. Fix this up by properly
calling dput().
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc:
Hi,
> Hi
>
> Am 07.09.22 um 06:16 schrieb Wang Yugui:
> > Hi,
> >
> >> Am 02.09.22 um 07:52 schrieb Wang Yugui:
> >>> Hi,
> >>>
> >>> mgag200 broken on kernel-6.0-rc3 on DELL/T620.
> >>>
> >>> See the attachementment file for the graph output.
> >>
> >> Thanks for reporting the bug. We recently r
These formats are not subsampled, but that means hsub and vsub should be
1, not 0.
Fixes: 94b292b27734 ("drm: drm_fourcc: add NV15, Q410, Q401 YUV formats")
Reported-by: George Kennedy
Reported-by: butt3rflyh4ck
Signed-off-by: Brian Starkey
---
drivers/gpu/drm/drm_fourcc.c | 8
1 file
Hi
Am 13.09.22 um 16:25 schrieb Wang Yugui:
Hi,
Hi
Am 07.09.22 um 06:16 schrieb Wang Yugui:
Hi,
Am 02.09.22 um 07:52 schrieb Wang Yugui:
Hi,
mgag200 broken on kernel-6.0-rc3 on DELL/T620.
See the attachementment file for the graph output.
Thanks for reporting the bug. We recently refa
On 9/13/22 15:49, Harry Wentland wrote:
>
>
> On 2022-09-13 05:33, Javier Martinez Canillas wrote:
>> Provides a default plane state check handler for primary planes that are a
>> fullscreen scanout buffer and whose state scale and position can't change.
>>
>
> Even though this might be how some
> -Original Message-
> From: Doug Anderson
> Sent: Friday, July 29, 2022 5:48 AM
> To: Vinod Polimera (QUIC)
> Cc: dri-devel ; linux-arm-msm m...@vger.kernel.org>; freedreno ;
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; LKML ; Rob
> Clark ; Stephen Boyd ;
> Kalyan
The eDP and DP interfaces shared the bridge operations and
the eDP specific changes were implemented under is_edp check.
To add psr support for eDP, we started using a new set of eDP
bridge ops. We are moving the eDP specific code in the
dp_bridge_mode_valid function to a new eDP function,
edp_brid
Update crtc retrieval from dpu_enc to dpu_enc connector state,
since new links get set as part of the dpu enc virt mode set.
The dpu_enc->crtc cache is no more needed, hence cleaning it as
part of this change.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4 ---
Reset the datapath after disabling the timing gen, such that
it can start on a clean slate when the intf is enabled back.
This was a recommended sequence from the DPU HW programming guide.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 +
1 file change
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Ba
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/drm_atomic.c | 60 ++
Changes in v2:
- Use dp bridge to set psr entry/exit instead of dpu_enocder.
- Don't modify whitespaces.
- Set self refresh aware from atomic_check.
- Set self refresh aware only if psr is supported.
- Provide a stub for msm_dp_display_set_psr.
- Move dp functions to bridge code.
Chang
Clear interface active register from the datapath for a clean shutdown of
the datapath.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
---
.../gpu/drm/msm/disp/dpu1/dpu_e
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/panel.c | 20 +++
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dis
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/bridge/panel.c | 48 ++
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++-
From: Sankeerth Billakanti
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
Timing gen status can be read reliablly from intf status
register rather than from the timing gen control register,
which will readback as "0" after disable though the timing
gen is still under going disable path. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
---
d
https://bugzilla.kernel.org/show_bug.cgi?id=216455
--- Comment #8 from Alex Deucher (alexdeuc...@gmail.com) ---
Patch:
https://patchwork.freedesktop.org/patch/501912/
--
You may reply to this email to add a comment.
You are receiving this mail because:
You are watching the assignee of the bug.
On 2022-09-13 10:46, Javier Martinez Canillas wrote:
> On 9/13/22 15:49, Harry Wentland wrote:
>>
>>
>> On 2022-09-13 05:33, Javier Martinez Canillas wrote:
>>> Provides a default plane state check handler for primary planes that are a
>>> fullscreen scanout buffer and whose state scale and posi
1 - 100 of 188 matches
Mail list logo
