I tested it on Loongarch and MIPS, and the results were fine。
-- Original --
From: "Neil Armstrong"
The property length which returns from "of_get_property", divided by
sizeof(int) to get the total property counts.
Fixes: fd0310b6fe7d ("drm/bridge: anx7625: add MIPI DPI input feature")
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 2 ++
1 file changed, 2 insertions(+)
On 09/03/2022 21:16, John Harrison wrote:
On 3/8/2022 01:41, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland about a GPU reset, and can also provide
some information like:
- process ID of the process involved with
Hi Dave, Daniel,
One PSR2 fix for the next release candidate, if there will be one.
Regards,
Tvrtko
drm-intel-fixes-2022-03-10:
- Fix PSR2 when selective fetch is enabled and cursor at (-1, -1) (Jouni
Högander)
The following changes since commit ffb217a13a2eaf6d5bd974fc83036a53ca69f1e2:
Li
On Wed, Mar 09, 2022 at 06:45:10PM -0600, Adam Ford wrote:
> On Wed, Mar 9, 2022 at 1:11 PM Jagan Teki wrote:
> >
> > or a Hi All,
> >
> > On Thu, Oct 14, 2021 at 6:45 PM Jagan Teki
> > wrote:
> > >
> > > Hi Laurent,
> > >
> > > On Fri, Oct 8, 2021 at 7:07 PM Laurent Pinchart
> > > wrote:
> >
Hi Maxime,
On Tue, Mar 08, 2022 at 01:51:40PM +0100, Maxime Ripard wrote:
> On Tue, Mar 08, 2022 at 11:29:59AM +0100, Marek Vasut wrote:
> > On 3/8/22 11:07, Jagan Teki wrote:
> > > On Tue, Mar 8, 2022 at 3:19 PM Marek Vasut wrote:
> > > >
> > > > On 3/8/22 09:03, Jagan Teki wrote:
> > > >
> >
On Wed, Mar 02, 2022 at 05:35:08PM +0800, Lee Shawn C wrote:
> Try to find and parse more CEA ext blocks if edid->extensions
> is greater than one.
>
> v2: split prvious patch to two. And do CEA block parsing
> in this one.
> v3: simplify this patch based on previous change.
>
> Cc: Jani Niku
On Wed, Mar 02, 2022 at 05:35:11PM +0800, Lee Shawn C wrote:
> Find HF-SCDB information in CEA extensions block. And retrieve
> Max_TMDS_Character_Rate that support by sink device.
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Ankit Nautiyal
> Signed-off-by: Lee Shawn C
> ---
> drivers/gpu/dr
Il 10/03/22 04:54, Nancy.Lin ha scritto:
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin
Reviewed-by: Chun-Kuang Hu
Reviewed-by: AngeloGioacchino Del Regno
---
.../display/mediatek/mediatek,ethdr.yaml | 158 ++
1 file changed, 158 insertions(+)
create mod
Il 10/03/22 04:55, Nancy.Lin ha scritto:
This is a preparation for adding support for mt8195 vdosys1 mutex.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin
Reviewed-by: Chun-Kuang Hu
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/g
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension. This is
the preparation for ovl_adaptor merge control.
Signed-off-by
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add merge start/stop API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq making sure all the settings taken effect in the
same vblank.
Signed-off-by: Nancy.Lin
Reviewed-by: Chun-K
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add merge mute/unmute setting for MT8195.
MT8195 Vdosys1 merge1~merge4 support HW mute function.
Signed-off-by: Nancy.Lin
Reviewed-by: Chun-Kuang Hu
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 13 +
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add merge async reset control in mtk_merge_stop. Async hw doesn't do self
reset on each sof signal(start of frame), so need to reset the async to
clear the hw status for the next merge start.
Signed-off-by: Nancy.Lin
Reviewed-by: CK Hu
Reviewed-by: An
Il 10/03/22 04:55, Nancy.Lin ha scritto:
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, out
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add plane color encoding information for color space conversion.
It's a preparation for adding support for mt8195 ovl_adaptor mdp_rdma
csc control.
Signed-off-by: Nancy.Lin
Reviewed-by: Chun-Kuang Hu
Reviewed-by: AngeloGioacchino Del Regno
---
d
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-b
Il 10/03/22 04:55, Nancy.Lin ha scritto:
Add display node for vdosys1.
Signed-off-by: Nancy.Lin
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 223 +++
1 file changed, 223 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek
On Tue, Mar 08, 2022 at 10:41:05PM +0100, Marek Vasut wrote:
> On 3/8/22 17:21, Maxime Ripard wrote:
> > On Tue, Mar 08, 2022 at 03:47:22PM +0100, Marek Vasut wrote:
> > > On 3/8/22 14:49, Maxime Ripard wrote:
> > > > On Tue, Mar 08, 2022 at 02:27:40PM +0100, Marek Vasut wrote:
> > > > > On 3/8/22
On Thu, Mar 10, 2022 at 12:42:12PM +0200, Laurent Pinchart wrote:
> Hi Maxime,
>
> On Tue, Mar 08, 2022 at 01:51:40PM +0100, Maxime Ripard wrote:
> > On Tue, Mar 08, 2022 at 11:29:59AM +0100, Marek Vasut wrote:
> > > On 3/8/22 11:07, Jagan Teki wrote:
> > > > On Tue, Mar 8, 2022 at 3:19 PM Marek V
On Thu, Mar 10, 2022 at 6:15 AM Adam Ford wrote:
>
> On Wed, Mar 9, 2022 at 1:11 PM Jagan Teki wrote:
> >
> > or a Hi All,
> >
> > On Thu, Oct 14, 2021 at 6:45 PM Jagan Teki
> > wrote:
> > >
> > > Hi Laurent,
> > >
> > > On Fri, Oct 8, 2021 at 7:07 PM Laurent Pinchart
> > > wrote:
> > > >
> >
On Tue, Mar 01, 2022 at 01:58:26PM -0100, Melissa Wen wrote:
> On 02/25, Maxime Ripard wrote:
> > Hi Melissa,
> >
> > On Tue, Feb 01, 2022 at 08:26:51PM -0100, Melissa Wen wrote:
> > > Trace submit_cl_ioctl and related IRQs for CL submission and bin/render
> > > jobs execution. It might be helpful
Hi Maxime,
On Thu, Mar 10, 2022 at 11:57:38AM +0100, Maxime Ripard wrote:
> On Thu, Mar 10, 2022 at 12:42:12PM +0200, Laurent Pinchart wrote:
> > On Tue, Mar 08, 2022 at 01:51:40PM +0100, Maxime Ripard wrote:
> > > On Tue, Mar 08, 2022 at 11:29:59AM +0100, Marek Vasut wrote:
> > > > On 3/8/22 11:0
https://bugzilla.kernel.org/show_bug.cgi?id=215669
--- Comment #2 from Andreas Polnas (andreas.polna...@hotmail.com) ---
Thanks Alex,
I have posted it on the mesa gitlab as an issue shown below:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/6113
--
You may reply to this email to add a comme
Hi Doug,
Quoting Doug Anderson (2022-03-07 19:52:08)
> Hi,
>
> On Mon, Mar 7, 2022 at 10:00 AM Kieran Bingham
> wrote:
> >
> > From: Laurent Pinchart
> >
> > Implement the bridge connector-related .get_edid() operation, and report
> > the related bridge capabilities and type.
> >
> > Signed-off
El 10/3/22 a las 12:12, Maxime Ripard escribió:
On Tue, Mar 01, 2022 at 01:58:26PM -0100, Melissa Wen wrote:
On 02/25, Maxime Ripard wrote:
Hi Melissa,
On Tue, Feb 01, 2022 at 08:26:51PM -0100, Melissa Wen wrote:
Trace submit_cl_ioctl and related IRQs for CL submission and bin/render
jobs exe
On 10/03/2022 05:18, Matt Atwood wrote:
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first, when passing a valid engine class and engine instance in the
flags returns a topology describing geometry.
The leftover bits around dealing with stolen-local memory + small BAR, plus
some related fixes.
v2: some tweaks based on feedback from Ville
--
2.34.1
From: Akeem G Abodunrin
On client platforms with reduced LMEM BAR, we should be able to continue
with driver load with reduced io_size. Instead of using the BAR size to
determine the how large stolen should be, we should instead use the
ADDR_RANGE register to figure this out(at least on platforms
Just pass along the probed io_size. The backend should be able to
utilize the entire range here, even if some of it is non-mappable.
It does leave open with what to do with stolen local-memory.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/
Keep the behaviour consistent with normal lmem, where we assume CPU
access if by default required.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen
For the ttm backend we can use existing placements fpfn and lpfn to
force the allocator to place the object at the requested offset,
potentially evicting stuff if the spot is currently occupied.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types.h
Add a generic interface for allocating an object at some specific
offset, and convert stolen over. Later we will want to hook this up to
different backends.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
.../drm/i915/display/intel_plane_initial.c| 4 +-
drivers/gpu/drm/i915/gem/i915_
From: CQ Tang
When system does not have mappable aperture, ggtt->mappable_end=0. In
this case if we pass PIN_MAPPABLE when pinning vma, the pinning code
will return -ENOSPC. So conditionally set PIN_MAPPABLE if HAS_GMCH().
Suggested-by: Chris P Wilson
Signed-off-by: CQ Tang
Cc: Radhakrishna Sr
The offset we get looks to be the exact start of DSM, but the
inital_plane_vma expects the address to be relative.
v2(Ville):
- The base is actually the pre-programmed GGTT address, which is then
meant to 1:1 map to somewhere inside dsm. In the case of dgpu the
base looks to just be some
On DG2+ the initial fb shouldn't be placed anywhere close to DSM, and so
should just be allocated directly from LMEM.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
.../drm/i915/display/intel_plane_initial.c| 46 +++
1 file changed, 27 insertions(+), 19 deletions(-)
d
On 3/10/22 11:53, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 10:41:05PM +0100, Marek Vasut wrote:
On 3/8/22 17:21, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 03:47:22PM +0100, Marek Vasut wrote:
On 3/8/22 14:49, Maxime Ripard wrote:
On Tue, Mar 08, 2022 at 02:27:40PM +0100, Marek Vasut wr
On 05/03/2022 23:36, Vivek Kasireddy wrote:
This iterator relies on drm_mm_first_hole() and drm_mm_next_hole()
functions to identify suitable holes for an allocation of a given
size by efficiently traversing the rbtree associated with the given
allocator.
It replaces the for loop in drm_mm_ins
Hi Jagan,
Am 09.03.22 um 15:01 schrieb Jagan Teki:
> Hi Frieder,
>
> On Wed, Mar 9, 2022 at 6:54 PM Frieder Schrempf
> wrote:
>>
>> Hi Jagan,
>>
>> Am 03.03.22 um 17:36 schrieb Jagan Teki:
>>> Updated series about drm bridge conversion of exynos dsi.
>>>
>>> Previous version can be accessible, h
On 09/03/2022 16:11, Biju Das wrote:
> On Renesas RZ/{G2L,V2L} platforms changing the lanes from 4 to 3 at
> lower frequencies causes display instability. On such platforms, it
> is better to avoid switching lanes from 4 to 3 as it needs different
> set of PLL parameter constraints to make the disp
Am 10.03.22 um 14:03 schrieb Frieder Schrempf:
> Hi Jagan,
>
> Am 09.03.22 um 15:01 schrieb Jagan Teki:
>> Hi Frieder,
>>
>> On Wed, Mar 9, 2022 at 6:54 PM Frieder Schrempf
>> wrote:
>>>
>>> Hi Jagan,
>>>
>>> Am 03.03.22 um 17:36 schrieb Jagan Teki:
Updated series about drm bridge conversion
https://bugzilla.kernel.org/show_bug.cgi?id=215652
--- Comment #8 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 300550
--> https://bugzilla.kernel.org/attachment.cgi?id=300550&action=edit
kernel dmesg (kernel 5.17-rc7, CONFIG_DRM_RADEON=m, Talos II)
Seems this is issue already fi
Quoting Kieran Bingham (2022-03-07 17:59:54)
> From: Laurent Pinchart
>
> Despite the SN65DSI86 being an eDP bridge, on some systems its output is
> routed to a DisplayPort connector. Enable DisplayPort mode when the next
> component in the display pipeline is detected as a DisplayPort
> connecto
On Thu, Mar 10, 2022 at 01:47:13PM +0100, Marek Vasut wrote:
> On 3/10/22 11:53, Maxime Ripard wrote:
> > On Tue, Mar 08, 2022 at 10:41:05PM +0100, Marek Vasut wrote:
> > > On 3/8/22 17:21, Maxime Ripard wrote:
> > > > On Tue, Mar 08, 2022 at 03:47:22PM +0100, Marek Vasut wrote:
> > > > > On 3/8/22
On Thu, Mar 10, 2022 at 01:16:57PM +0200, Laurent Pinchart wrote:
> On Thu, Mar 10, 2022 at 11:57:38AM +0100, Maxime Ripard wrote:
> > On Thu, Mar 10, 2022 at 12:42:12PM +0200, Laurent Pinchart wrote:
> > > On Tue, Mar 08, 2022 at 01:51:40PM +0100, Maxime Ripard wrote:
> > > > On Tue, Mar 08, 2022
On Thursday, March 10, 2022 6:50 PM, Ville Syrjälä
wrote:
>On Wed, Mar 02, 2022 at 05:35:11PM +0800, Lee Shawn C wrote:
>> Find HF-SCDB information in CEA extensions block. And retrieve
>> Max_TMDS_Character_Rate that support by sink device.
>>
>> Cc: Jani Nikula
>> Cc: Ville Syrjala
>> Cc: A
Quoting Kieran Bingham (2022-03-10 14:04:09)
> Quoting Kieran Bingham (2022-03-07 17:59:54)
> > From: Laurent Pinchart
> >
> > Despite the SN65DSI86 being an eDP bridge, on some systems its output is
> > routed to a DisplayPort connector. Enable DisplayPort mode when the next
> > component in the
https://bugzilla.kernel.org/show_bug.cgi?id=215652
--- Comment #9 from Alex Deucher (alexdeuc...@gmail.com) ---
Only the person that filed the bug can close it. If it's fixed for you, please
close it. Thanks!
--
You may reply to this email to add a comment.
You are receiving this mail because
On 08/03/22 10:31 pm, Matthew Auld wrote:
> On 08/03/2022 13:59, Arunpravin wrote:
>>
>>
>> On 07/03/22 10:11 pm, Matthew Auld wrote:
>>> On 07/03/2022 14:37, Arunpravin wrote:
place BUG_ON(order < min_order) outside do..while
loop as it fails Unigine Heaven benchmark.
Unigin
Support to parse multiple CEA extension blocks and HF-EEODB to
extend drm edid driver's capability.
v4: add one more patch to support HF-SCDB
v5: HF-SCDB and HF-VSDBS carry the same SCDS data. Reuse
drm_parse_hdmi_forum_vsdb() to parse this packet.
Lee Shawn C (5):
drm/edid: seek for availa
Try to find and parse more CEA ext blocks if edid->extensions
is greater than one.
v2: split prvious patch to two. And do CEA block parsing
in this one.
v3: simplify this patch based on previous change.
v4: refine patch v3.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Ankit Nautiyal
Cc: intel-gfx
drm_find_cea_extension() always look for a top level CEA block. Pass
ext_index from caller then this function to search next available
CEA ext block from a specific EDID block pointer.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Ankit Nautiyal
Cc: intel-gfx
Signed-off-by: Lee Shawn C
---
drivers/g
According to HDMI 2.1 spec.
"The HDMI Forum EDID Extension Override Data Block (HF-EEODB)
is utilized by Sink Devices to provide an alternate method to
indicate an EDID Extension Block count larger than 1, while
avoiding the need to present a VESA Block Map in the first
E-EDID Extension Block."
I
Find HF-SCDB information in CEA extensions block. And retrieve
Max_TMDS_Character_Rate that support by sink device.
v2: HF-SCDB and HF-VSDBS carry the same SCDS data. Reuse
drm_parse_hdmi_forum_vsdb() to parse this packet.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Ankit Nautiyal
Cc: intel-gfx
While adding CEA modes, try to get available EEODB block
number. Then based on it to parse numbers of ext blocks,
retrieve CEA information and add more CEA modes.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Ankit Nautiyal
Cc: intel-gfx
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/drm_displayid.c
Hi,
On Thu, Mar 10, 2022 at 3:43 AM Kieran Bingham
wrote:
>
> Hi Doug,
>
> Quoting Doug Anderson (2022-03-07 19:52:08)
> > Hi,
> >
> > On Mon, Mar 7, 2022 at 10:00 AM Kieran Bingham
> > wrote:
> > >
> > > From: Laurent Pinchart
> > >
> > > Implement the bridge connector-related .get_edid() oper
Hi,
looks like I wasn't in the original recipient list, so only got Nick's
answer.
Am Mittwoch, 9. März 2022, 00:10:31 CET schrieb Nick Desaulniers:
> On Mon, Mar 7, 2022 at 10:17 AM Colin Ian King wrote:
> >
> > The pointer connector is being assigned a value that is never read,
> > it is being
Hi Paul,
On Wed, Mar 09, 2022 at 03:32:00PM +0100, Paul Kocialkowski wrote:
> While bridge/panel detection was initially relying on the usual
> port/ports-based of graph detection, it was recently changed to
> perform the lookup on any child node that is not port/ports
> instead when such a node i
Implement support for non eDP connectors on the TI-SN65DSI86 bridge, and
provide IRQ based hotplug detect to identify when the connector is
present.
no-hpd is extended to be the default behaviour for non DisplayPort
connectors.
This series is based upon Sam Ravnborgs and Rob Clarks series [0] to
From: Laurent Pinchart
Despite the SN65DSI86 being an eDP bridge, on some systems its output is
routed to a DisplayPort connector. Enable DisplayPort mode when the next
component in the display pipeline is detected as a DisplayPort
connector, and disable eDP features in that case.
Signed-off-by:
When the SN65DSI86 is used in DisplayPort mode, its output is likely
routed to a DisplayPort connector, which can benefit from hotplug
detection. Support it in such cases, with polling mode only for now.
The implementation is limited to the bridge operations, as the connector
operations are legacy
From: Laurent Pinchart
Implement the bridge connector-related .get_edid() operation, and report
the related bridge capabilities and type.
Signed-off-by: Laurent Pinchart
Signed-off-by: Kieran Bingham
---
Changes since v1:
- The connector .get_modes() operation doesn't rely on EDID anymore,
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
>
>
>
> Am 09.03.22 um 19:12 schrieb Rob Clark:
> > On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
> > wrote:
> >> From: Shashank Sharma
> >>
> >> This patch adds a new sysfs event, which will indicate
> >> the userland about a GPU reset, a
Quoting Kieran Bingham (2022-03-10 15:22:27)
> When the SN65DSI86 is used in DisplayPort mode, its output is likely
> routed to a DisplayPort connector, which can benefit from hotplug
> detection. Support it in such cases, with polling mode only for now.
>
> The implementation is limited to the br
On 10/03/2022 14:47, Arunpravin wrote:
On 08/03/22 10:31 pm, Matthew Auld wrote:
On 08/03/2022 13:59, Arunpravin wrote:
On 07/03/22 10:11 pm, Matthew Auld wrote:
On 07/03/2022 14:37, Arunpravin wrote:
place BUG_ON(order < min_order) outside do..while
loop as it fails Unigine Heaven benchm
Hi Kieran,
Thank you for the patch.
On Thu, Mar 10, 2022 at 03:22:25PM +, Kieran Bingham wrote:
> From: Laurent Pinchart
>
> Despite the SN65DSI86 being an eDP bridge, on some systems its output is
> routed to a DisplayPort connector. Enable DisplayPort mode when the next
> component in the
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new sysfs event, which will indicate
the userland about
Hi Kieran,
Thank you for the patch.
On Thu, Mar 10, 2022 at 03:22:26PM +, Kieran Bingham wrote:
> From: Laurent Pinchart
>
> Implement the bridge connector-related .get_edid() operation, and report
> the related bridge capabilities and type.
>
> Signed-off-by: Laurent Pinchart
> Signed-of
On 2022-03-10 11:21, Sharma, Shashank wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrote:
From: Shashank Sharma
This patch adds a new sysf
Hi Biju,
Thank you for the patch.
On Wed, Mar 09, 2022 at 03:11:08PM +, Biju Das wrote:
> On Renesas RZ/{G2L,V2L} platforms changing the lanes from 4 to 3 at
> lower frequencies causes display instability. On such platforms, it
> is better to avoid switching lanes from 4 to 3 as it needs diff
Hi Kieran,
Thank you for the patch.
On Thu, Mar 10, 2022 at 03:22:27PM +, Kieran Bingham wrote:
> When the SN65DSI86 is used in DisplayPort mode, its output is likely
> routed to a DisplayPort connector, which can benefit from hotplug
> detection. Support it in such cases, with polling mode o
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH 1/2] dt-bindings: drm: bridge: adi,adv7533: Document
> adi,disable-lanes-override property
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Wed, Mar 09, 2022 at 03:11:08PM +, Biju Das wrote:
> > On Renesas RZ/{G2L,V2L} platforms ch
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 4:24 PM, Rob Clark wrote:
> > On Thu, Mar 10, 2022 at 1:55 AM Christian König
> > wrote:
> >>
> >>
> >>
> >> Am 09.03.22 um 19:12 schrieb Rob Clark:
> >>> On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
> >>> wrote:
> >
On Thu, Mar 10, 2022 at 8:27 AM Andrey Grodzovsky
wrote:
>
>
> On 2022-03-10 11:21, Sharma, Shashank wrote:
> >
> >
> > On 3/10/2022 4:24 PM, Rob Clark wrote:
> >> On Thu, Mar 10, 2022 at 1:55 AM Christian König
> >> wrote:
> >>>
> >>>
> >>>
> >>> Am 09.03.22 um 19:12 schrieb Rob Clark:
> On
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrote:
Am 09.03.22 um 19:12 schrieb Rob Clark:
On Tue, Mar 8, 2022 at 11:40 PM Shashank Sharma
wrot
DEVICE_COHERENT pages introduce a subtle distinction in the way
"normal" pages can be used by various callers throughout the kernel.
They behave like normal pages for purposes of mapping in CPU page
tables, and for COW. But they do not support LRU lists, NUMA
migration or THP. Therefore we split vm
Test device pages with get_user_pages and get_user_pages_fast.
The motivation is to test device coherent type pages in the gup and
gup fast paths, after vm_normal_pages was split into LRU and non-LRU
handled.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
---
tools/testing/selftests/vm/hmm
The objective is to test device migration mechanism in pages marked
as COW, for private and coherent device type. In case of writing to
COW private page(s), a page fault will migrate pages back to system
memory first. Then, these pages will be duplicated. In case of COW
device coherent type, pages
DEVICE_COHERENT pages introduce a subtle distinction in the way
"normal" pages can be used by various callers throughout the kernel.
They behave like normal pages for purposes of mapping in CPU page
tables, and for COW. But they do not support LRU lists, NUMA
migration or THP. Therefore we split vm
Hi Laurent
Quoting Laurent Pinchart (2022-03-10 16:42:48)
> Hi Kieran,
>
> Thank you for the patch.
>
> On Thu, Mar 10, 2022 at 03:22:27PM +, Kieran Bingham wrote:
> > When the SN65DSI86 is used in DisplayPort mode, its output is likely
> > routed to a DisplayPort connector, which can benefi
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 6:10 PM, Rob Clark wrote:
> > On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
> > wrote:
> >>
> >>
> >>
> >> On 3/10/2022 4:24 PM, Rob Clark wrote:
> >>> On Thu, Mar 10, 2022 at 1:55 AM Christian König
> >>> wrote:
> >
On Tue, 08 Mar 2022 21:15:43 +, Lad Prabhakar wrote:
> The Renesas RZ/V2L SoC (a.k.a R9A07G054) has a Bifrost Mali-G31 GPU,
> add a compatible string for it.
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Biju Das
> ---
> Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 1:55 AM Christian König
wrot
Hi Xin,
On Thu, Mar 10, 2022 at 05:16:53PM +0800, Xin Ji wrote:
> The property length which returns from "of_get_property", divided by
> sizeof(int) to get the total property counts.
>
> Fixes: fd0310b6fe7d ("drm/bridge: anx7625: add MIPI DPI input feature")
>
> Signed-off-by: Xin Ji
> ---
> d
Hi
Am 09.03.22 um 23:25 schrieb Dmitry Osipenko:
The reason for this work is to keep GEM shmem pages mapped and allocated
even while the BO is neither mapped nor pinned. As it is now, GEM SHMEM
creates and releases pages on each pin and unpin, and maps and unmaps
memory ranges on each vmap and
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 8:21 AM Sharma, Shashank
wrote:
On 3/10/2022 4:24 PM, Rob Clark wrote:
On Thu,
Hi
Am 09.03.22 um 11:39 schrieb Geert Uytterhoeven:
Hi Marek,
On Wed, Mar 9, 2022 at 10:22 AM Marek Szyprowski
wrote:
On 09.03.2022 09:22, Thomas Zimmermann wrote:
Am 08.03.22 um 23:52 schrieb Marek Szyprowski:
On 23.02.2022 20:38, Thomas Zimmermann wrote:
Improve the performance of cfb_im
Hi Thomas,
On Thu, Mar 10, 2022 at 8:22 PM Thomas Zimmermann wrote:
> Am 09.03.22 um 11:39 schrieb Geert Uytterhoeven:
> > On Wed, Mar 9, 2022 at 10:22 AM Marek Szyprowski
> > wrote:
> >> On 09.03.2022 09:22, Thomas Zimmermann wrote:
> >>> Am 08.03.22 um 23:52 schrieb Marek Szyprowski:
> On
On Thu, Mar 10, 2022 at 11:26:31AM -0600, Alex Sierra wrote:
> @@ -606,7 +606,7 @@ static void print_bad_pte(struct vm_area_struct *vma,
> unsigned long addr,
> * PFNMAP mappings in order to support COWable mappings.
> *
> */
> -struct page *vm_normal_page(struct vm_area_struct *vma, unsigne
Hi Dave and Daniel,
here's the PR for drm-misc-fixes for this week.
Best regards
Thomas
drm-misc-fixes-2022-03-10:
* drm/sun4i: Fix P010 and P210 format numbers
The following changes since commit 62929726ef0ec72cbbe9440c5d125d4278b99894:
drm/vrr: Set VRR capable prop only if it is attached t
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
> >
> >
> > On 3/10/2022 9:40 AM, Rob Clark wrote:
> >> On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 3/10/2022 6:10 PM, Rob Clark wrote:
> On
On 3/10/2022 8:35 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 9:19 AM Sharma, Shashank
wrote:
On 3/10/2022 6:10 PM, Rob Clark wrote:
On Thu
On Thu, Mar 10, 2022 at 11:44 AM Sharma, Shashank
wrote:
>
>
>
> On 3/10/2022 8:35 PM, Rob Clark wrote:
> > On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
> > wrote:
> >>
> >>
> >>
> >> On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
> >>>
> >>>
> >>> On 3/10/2022 9:40 AM, Rob Clark wrote:
> O
On 3/10/2022 8:56 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:44 AM Sharma, Shashank
wrote:
On 3/10/2022 8:35 PM, Rob Clark wrote:
On Thu, Mar 10, 2022 at 11:14 AM Sharma, Shashank
wrote:
On 3/10/2022 7:33 PM, Abhinav Kumar wrote:
On 3/10/2022 9:40 AM, Rob Clark wrote:
On Th
On 3/10/2022 01:27, Tvrtko Ursulin wrote:
On 09/03/2022 21:16, John Harrison wrote:
On 3/8/2022 01:41, Tvrtko Ursulin wrote:
On 03/03/2022 22:37, john.c.harri...@intel.com wrote:
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling
On 3/10/22 22:02, Thomas Zimmermann wrote:
> Hi
>
> Am 09.03.22 um 23:25 schrieb Dmitry Osipenko:
>>>
>>> The reason for this work is to keep GEM shmem pages mapped and allocated
>>> even while the BO is neither mapped nor pinned. As it is now, GEM SHMEM
>>> creates and releases pages on each pin
Am 2022-03-10 um 14:25 schrieb Matthew Wilcox:
On Thu, Mar 10, 2022 at 11:26:31AM -0600, Alex Sierra wrote:
@@ -606,7 +606,7 @@ static void print_bad_pte(struct vm_area_struct *vma,
unsigned long addr,
* PFNMAP mappings in order to support COWable mappings.
*
*/
-struct page *vm_norm
On Tue, Mar 08, 2022 at 02:06:43PM +0100, Christophe Branchereau wrote:
> Add binding for the leadtek ltk035c5444t, which is a 640x480
> mipi-dbi over spi / 24-bit RGB panel based on the newvision
> NV03052C chipset.
>
> It is found in the Anbernic RG350M mips handheld.
>
> Signed-off-by: Christo
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