This patch series prepares error capture for asynchronous migration,
where the vma pages may not reflect the pages the GPU is currently
executing from but may be several migrations ahead.
The first patch deals with refcounting sg-list so that they don't
disappear under the capture code, which typi
With asynchronous migrations, the vma state may be several migrations
ahead of the state that matches the request we're capturing.
Address that by introducing an i915_vma_snapshot structure that
can be used to snapshot relevant state at request submission.
In order to make sure we access the correc
As we start to introduce asynchronous failsafe object migration,
where we update the object state and then submit asynchronous
commands we need to record what memory resources are actually used
by various part of the command stream. Initially for three purposes:
1) Error capture.
2) Asynchronous m
From: Thomas Hellström
The vma resource are needed for asynchronous bind management and are
similar to TTM resources. They contain the data needed for
asynchronous unbinding (typically the vm range, any backend
private information and a means to do refcounting and to hold
the unbinding for error
On 12/10/2021 15:09, Gal Pressman wrote:
> Hey all,
>
> This is a followup to my previous RFCs [1][2], which now adds a new api
> to the RDMA subsystem that allows drivers to get a pinned dmabuf memory
> region without requiring an implementation of the move_notify callback.
> The new api makes use
Hi Chun-Kuang,
Thanks for the review.
On Tue, 2021-10-26 at 07:11 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This modul
From: Guangming Cao
On Thu, 2021-10-14 at 18:25 +0800, guangming@mediatek.com wrote:
> From: Guangming Cao
>
> In this patch(https://patchwork.freedesktop.org/patch/310349),
> it add a new IOCTL to support dma-buf user to set debug name.
>
> But it also added a limitation of this IOCTL, it
Hi,
On 10/21/21 22:37, Matthew Brost wrote:
On Thu, Oct 21, 2021 at 08:15:49AM +0200, Thomas Hellström wrote:
Hi, Matthew,
On Mon, 2021-10-11 at 16:47 -0700, Matthew Brost wrote:
The hangcheck selftest blocks per engine resets by setting magic bits
in
the reset flags. This is incorrect for Gu
Hi George,
On Mon, Oct 25, 2021 at 9:37 PM George Kennedy
wrote:
> On 10/25/2021 3:07 PM, Greg KH wrote:
> > On Mon, Oct 25, 2021 at 02:01:30PM -0500, George Kennedy wrote:
> >> Do a sanity check on pixclock value before using it as a divisor.
> >>
> >> Syzkaller reported a divide error in cirrus
From: Arnd Bergmann
Some randconfig builds fail when drm/drm_bridge.h is not included
implicitly in this file:
drivers/gpu/drm/msm/dp/dp_parser.c:279:25: error: implicit declaration of
function 'devm_drm_panel_bridge_add' [-Werror,-Wimplicit-function-declaration]
parser->panel_bridge =
From: Arnd Bergmann
The x86 low-level cache management operations are declared in
asm/smp.h, so drivers that call into this code need to include
the header:
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c:248:3: error: implicit declaration
of function 'wbinvd_on_all_cpus' [-Werror,-Wimplicit-functio
From: Arnd Bergmann
The new driver incorrectly unwinds after errors, as clang points out:
drivers/dma-buf/st-dma-resv.c:295:7: error: variable 'i' is used uninitialized
whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
if (r) {
^
drivers/dma
From: Guangming Cao
On Tue, 2021-10-19 at 23:11 +0200, Daniel Vetter wrote:
> On Tue, Oct 19, 2021 at 05:37:27PM +0200, Christian K鰊ig wrote:
> >
> >
> > Am 19.10.21 um 14:41 schrieb Daniel Vetter:
> > > On Tue, Oct 19, 2021 at 08:23:45PM +0800,
> > > guangming@mediatek.com wrote:
> > > >
Quoting Matthew Brost (2021-10-25 18:15:09)
> On Mon, Oct 25, 2021 at 12:37:02PM +0300, Joonas Lahtinen wrote:
> > Quoting Matthew Brost (2021-10-22 19:42:19)
> > > On Fri, Oct 22, 2021 at 12:35:04PM +0300, Joonas Lahtinen wrote:
> > > > Hi Matt & John,
> > > >
> > > > Can you please queue patches
Quoting John Harrison (2021-10-26 00:06:54)
> On 10/25/2021 09:34, Matthew Brost wrote:
> > Hide the guc_id and tail fields, for request trace points, behind
> > CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS Kconfig option. Trace points
> > are ABI (maybe?) so don't change them without kernel developers Kc
Quoting Matthew Brost (2021-10-25 20:13:22)
> On Mon, Oct 25, 2021 at 03:23:00PM +0300, Joonas Lahtinen wrote:
> > Quoting Thomas Hellström (2021-10-21 08:39:48)
> > > On Wed, 2021-10-20 at 12:21 -0700, Matthew Brost wrote:
> >
> >
> >
> > > > Fixes: 1a52faed31311 ("drm/i915/guc: Take engine PM
On 10/22/21 18:48, Matthew Auld wrote:
The scratch page is directly visible in the users address space, and
while this is forced as CACHE_LLC, by the kernel, we still have to
contend with things like "Bypass-LLC" MOCS. So just flush no matter
what.
Signed-off-by: Matthew Auld
Cc: Thomas Hells
https://bugzilla.kernel.org/show_bug.cgi?id=211807
--- Comment #12 from zwer...@mail.de ---
As mentioned before, I get the same error with a monitor connected with DP to a
Lenovo ThinkPad USB-C Dock Gen2. My Laptop has an Intel i7 10510U no additional
graphics card. I am using Debian testing with
On 10/22/21 18:48, Matthew Auld wrote:
The scratch page is directly visible in the users address space, and
while this is forced as CACHE_LLC, by the kernel, we still have to
contend with things like "Bypass-LLC" MOCS. So just flush no matter
what.
Signed-off-by: Matthew Auld
Cc: Thomas Hells
On 10/22/21 18:48, Matthew Auld wrote:
Normal users shouldn't be hitting this, likely this would indicate a
userspace bug. So don't bother caching, which should be safe now that we
manually flush the page.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Chris
Am 26.10.21 um 04:33 schrieb Andrey Grodzovsky:
On 2021-10-25 3:56 p.m., Christian König wrote:
In general I'm all there to get this fixed, but there is one major
problem: Drivers don't expect the lock to be dropped.
I am probably missing something but in my approach we only modify the
code
Am 26.10.21 um 10:34 schrieb Arnd Bergmann:
From: Arnd Bergmann
The new driver incorrectly unwinds after errors, as clang points out:
drivers/dma-buf/st-dma-resv.c:295:7: error: variable 'i' is used uninitialized
whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
Just a gentle ping on those two.
The changes are straight forward and I just need an ack.
Adding Daniel, maybe he has a minute :)
Cheers,
Christian.
Am 25.10.21 um 10:05 schrieb Christian König:
Hi guys,
just two minor cleanups related to the new DMA-buf iterators. Can I get an rb
or ack-by
Am 14.10.21 um 12:25 schrieb guangming@mediatek.com:
From: Guangming Cao
In this patch(https://patchwork.freedesktop.org/patch/310349),
it add a new IOCTL to support dma-buf user to set debug name.
But it also added a limitation of this IOCTL, it needs the
attachments of dmabuf should be e
Fixes screen orientation for GPD Win 3 handheld gaming console.
Signed-off-by: Mario Risoldi
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
b/drivers/gpu/drm/drm_panel_orientation_quirks
Summary
===
This series of patches refactor some vkms components in order to introduce
new formats to the planes and writeback connector.
Now in the blend function, the plane's pixels are converted to ARGB16161616
and then blended together.
The CRC is calculated based on the ARGB1616161616 bu
Currently, the memory to the composition frame is being allocated using
the kzmalloc. This comes with the limitation of maximum size of one
page size(which in the x86_64 is 4Kb and 4MB for default and hugepage
respectively).
Somes test of igt (e.g. kms_plane@pixel-format) uses more than 4MB when
t
The `drm_mode_config_init` was deprecated since c3b790e commit, and it's
being replaced by the `drmm_mode_config_init`.
Signed-off-by: Igor Torrente
---
V2: Change the code style(Thomas Zimmermann).
---
drivers/gpu/drm/vkms/vkms_drv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
d
This commit is the groundwork to introduce new formats to the planes and
writeback buffer. As part of it, a new buffer metadata field is added to
`vkms_writeback_job`, this metadata is represented by the `vkms_composer`
struct.
This will allow us, in the future, to have different compositing and w
Add a helper function to validate the connector configuration receive in
the encoder atomic_check by the drivers.
So the drivers don't need do these common validations themselves.
Signed-off-by: Igor Torrente
---
V2: Move the format verification to a new helper at the drm_atomic_helper.c
(Th
This will be useful to write tests that depends on these formats.
ARGB format is already used as the universal format for internal uses.
Here we are just exposing it to the user space.
XRGB follows the a similar implementation of the former format.
Just overwriting the alpha channel.
Signed-off-
The `map` vector at `vkms_composer` uses a hardcoded value to define its
size.
If someday the maximum number of planes increases, this hardcoded value
can be a problem.
This value is being replaced with the DRM_FORMAT_MAX_PLANES macro.
Signed-off-by: Igor Torrente
---
drivers/gpu/drm/vkms/vkms
Currently the blend function only accepts XRGB_ and ARGB_
as a color input.
This patch refactors all the functions related to the plane composition
to overcome this limitation.
Now the blend function receives a struct `vkms_pixel_composition_functions`
containing two handlers.
One will g
Adds this common format to vkms.
This commit also adds new helper macros to deal with fixed-point
arithmetic.
It was done to improve the precision of the conversion to ARGB16161616
since the "conversion ratio" is not an integer.
Signed-off-by: Igor Torrente
---
drivers/gpu/drm/vkms/vkms_compos
Adds this common format to vkms.
This commit also adds new helper macros to deal with fixed-point
arithmetic.
It was done to improve the precision of the conversion to ARGB16161616
since the "conversion ratio" is not an integer.
Signed-off-by: Igor Torrente
---
drivers/gpu/drm/vkms/vkms_compos
the following patches are from the PREEMPT_RT queue. It is mostly about
disabling interrupts/preemption which leads to problems. Patches 1-4 are
independent of PREEMPT_RT.
Unfortunately DRM_I915_LOW_LEVEL_TRACEPOINTS had to be disabled because
it acquires locks from within trace points. It has bee
execlists_dequeue() is invoked from a function which uses
local_irq_disable() to disable interrupts so the spin_lock() behaves
like spin_lock_irq().
This breaks PREEMPT_RT because local_irq_disable() + spin_lock() is not
the same as spin_lock_irq().
execlists_dequeue_irq() and execlists_dequeue()
Luca Abeni reported this:
| BUG: scheduling while atomic: kworker/u8:2/15203/0x0003
| CPU: 1 PID: 15203 Comm: kworker/u8:2 Not tainted 4.19.1-rt3 #10
| Call Trace:
| rt_spin_lock+0x3f/0x50
| gen6_read32+0x45/0x1d0 [i915]
| g4x_get_vblank_counter+0x36/0x40 [i915]
| trace_event_raw_event_i915
The !irqs_disabled() check triggers on PREEMPT_RT even with
i915_sched_engine::lock acquired. The reason is the lock is transformed
into a sleeping lock on PREEMPT_RT and does not disable interrupts.
There is no need to check for disabled interrupts. The lockdep
annotation below already check if t
Disabling interrupts and invoking the irq_work function directly breaks
on PREEMPT_RT.
PREEMPT_RT does not invoke all irq_work from hardirq context because
some of the user have spinlock_t locking in the callback function.
These locks are then turned into a sleeping locks which can not be
acquired
This is a revert of commits
d67739268cf0e ("drm/i915/gt: Mark up the nested engine-pm timeline lock as
irqsafe")
6c69a45445af9 ("drm/i915/gt: Mark context->active_count as protected by
timeline->mutex")
The existing code leads to a different behaviour depending on whether
lockdep is enable
The order of the header files is important. If this header file is
included after tracepoint.h was included then the NOTRACE here becomes a
nop. Currently this happens for two .c files which use the tracepoitns
behind DRM_I915_LOW_LEVEL_TRACEPOINTS.
Cc: Steven Rostedt
Signed-off-by: Sebastian And
From: Mike Galbraith
Commit
8d7849db3eab7 ("drm/i915: Make sprite updates atomic")
started disabling interrupts across atomic updates. This breaks on PREEMPT_RT
because within this section the code attempt to acquire spinlock_t locks which
are sleeping locks on PREEMPT_RT.
According to the c
The !in_atomic() check in _wait_for_atomic() triggers on PREEMPT_RT
because the uncore::lock is a spinlock_t and does not disable
preemption or interrupts.
Changing the uncore:lock to a raw_spinlock_t doubles the worst case
latency on an otherwise idle testbox during testing. Therefore I'm
current
From: Mike Galbraith
Mario Kleiner suggest in commit
ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into kms
driver.")
a spots where preemption should be disabled on PREEMPT_RT. The
difference is that on PREEMPT_RT the intel_uncore::lock disables neither
preemption nor in
From: Guangming Cao
On Tue, 2021-10-26 at 13:18 +0200, Christian König wrote:
> Am 14.10.21 um 12:25 schrieb guangming@mediatek.com:
> > From: Guangming Cao
> >
> > In this patch(https://patchwork.freedesktop.org/patch/310349),
> > it add a new IOCTL to support dma-buf user to set debug nam
Dear Mark,
Thank you for your patch.
On 13.10.21 20:12, Mark Yacoub wrote:
From: Mark Yacoub
[Why]
1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
or Degamma props in the new CRTC state, allowing any invalid size to
be passed on.
2. Each driver has its own LUT size
Hi Dave and Dan,
Last pull request for me for v5.15 I hope.
Out for vacation until the third week of november,
Maxime offered to do the remainder of v5.15.
~Maarten
drm-misc-fixes-2021-10-26:
drm-misc-fixes for v5.15-rc8:
- Fix fence leak in ttm_transfered_destroy.
- Add quirk for Aya Neo 2021
-
https://bugzilla.kernel.org/show_bug.cgi?id=211807
--- Comment #13 from Alex Deucher (alexdeuc...@gmail.com) ---
(In reply to zwerg12 from comment #12)
> As mentioned before, I get the same error with a monitor connected with DP
> to a Lenovo ThinkPad USB-C Dock Gen2. My Laptop has an Intel i7 105
Hi Geert,
On 10/26/2021 4:30 AM, Geert Uytterhoeven wrote:
Hi George,
On Mon, Oct 25, 2021 at 9:37 PM George Kennedy
wrote:
On 10/25/2021 3:07 PM, Greg KH wrote:
On Mon, Oct 25, 2021 at 02:01:30PM -0500, George Kennedy wrote:
Do a sanity check on pixclock value before using it as a divisor.
On Mon, Oct 18, 2021 at 06:45:03PM +0100, Matthew Auld wrote:
> As pointed out by Thomas, we likely need to flush the pages here if the
> GPU can read the page contents directly from main memory. Underneath we
> don't know what the sg_table is pointing to, so just add a
> wbinvd_on_all_cpus() here,
On Tue, Oct 26, 2021 at 10:34:37AM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The new driver incorrectly unwinds after errors, as clang points out:
>
> drivers/dma-buf/st-dma-resv.c:295:7: error: variable 'i' is used
> uninitialized whenever 'if' condition is true
> [-Werror,-Wsomet
Hi George,
On Tue, Oct 26, 2021 at 3:38 PM George Kennedy
wrote:
> On 10/26/2021 4:30 AM, Geert Uytterhoeven wrote:
> > On Mon, Oct 25, 2021 at 9:37 PM George Kennedy
> > wrote:
> >> On 10/25/2021 3:07 PM, Greg KH wrote:
> >>> On Mon, Oct 25, 2021 at 02:01:30PM -0500, George Kennedy wrote:
> >>>
Clang warns:
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:162:6: error: variable 'commit' is
uninitialized when used here [-Werror,-Wuninitialized]
if (commit)
^~
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:106:32: note: initialize the variable
'commit' to silence this warning
Hi Stephen,
I love your patch! Yet something to improve:
[auto build test ERROR on e4e737bb5c170df6135a127739a9e6148ee3da82]
url:
https://github.com/0day-ci/linux/commits/Stephen-Boyd/component-Make-into-an-aggregate-bus/20211026-080422
base: e4e737bb5c170df6135a127739a9e6148ee3da82
On 2021-10-12 17:01, Shankar, Uma wrote:
>
>
>> -Original Message-
>> From: Pekka Paalanen
>> Sent: Tuesday, October 12, 2021 5:25 PM
>> To: Shankar, Uma
>> Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>> harry.wentl...@amd.com; ville.syrj...@linux.intel.com;
Thanks, Uma, for the updated patches. I'm finally finding
time to go through them.
On 2021-10-15 03:42, Pekka Paalanen wrote:
> On Thu, 14 Oct 2021 19:44:25 +
> "Shankar, Uma" wrote:
>
>>> -Original Message-
>>> From: Pekka Paalanen
>>> Sent: Wednesday, October 13, 2021 2:01 PM
>>>
Il 23/10/21 13:14, Flora Fu ha scritto:
Add apu core driver.
The core driver will init the reset part of apu functions.
Signed-off-by: Flora Fu
---
drivers/soc/mediatek/Kconfig | 18 +
drivers/soc/mediatek/apusys/Makefile | 3 +
drivers/soc/mediatek/apusys/apu-core.c | 91 +
Il 23/10/21 13:14, Flora Fu ha scritto:
APU IOMMU is a new iommu HW. it use a new pagetable.
Add support for mt8192 apu iommu.
Signed-off-by: Yong Wu
Signed-off-by: Flora Fu
---
drivers/iommu/mtk_iommu.c | 57 +++
include/dt-bindings/memory/mt8192-larb-po
Il 23/10/21 13:14, Flora Fu ha scritto:
Add node for APU tinysys.
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192
Il 23/10/21 13:14, Flora Fu ha scritto:
Add driver for control APU tinysys
APU integrated subsystem having MD32RV33 (MD32) that runs tinysys
The tinsys is running on a micro processor in APU.
Its firmware is load and boot from Kernel side. Kernel and tinysys use
IPI to tx/rx messages.
Signed-of
On 2021-10-14 15:44, Shankar, Uma wrote:
>
>
>> -Original Message-
>> From: Pekka Paalanen
>> Sent: Wednesday, October 13, 2021 2:01 PM
>> To: Shankar, Uma
>> Cc: harry.wentl...@amd.com; ville.syrj...@linux.intel.com; intel-
>> g...@lists.freedesktop.org; dri-devel@lists.freedesktop
On 2021-10-12 16:58, Shankar, Uma wrote:
>
>
>> -Original Message-
>> From: Pekka Paalanen
>> Sent: Tuesday, October 12, 2021 4:01 PM
>> To: Shankar, Uma
>> Cc: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>> harry.wentl...@amd.com; ville.syrj...@linux.intel.com
On 2021-10-25 at 14:20:02 +0300, Juha-Pekka Heikkila wrote:
> On 21.10.2021 17.35, Ville Syrjälä wrote:
> > On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote:
> > > From: Matt Roper
> > >
> > > DG2 unifies render compression and media compression into a single
> > > format for the firs
Hi Geert,
On 10/26/2021 10:11 AM, Geert Uytterhoeven wrote:
Hi George,
On Tue, Oct 26, 2021 at 3:38 PM George Kennedy
wrote:
On 10/26/2021 4:30 AM, Geert Uytterhoeven wrote:
On Mon, Oct 25, 2021 at 9:37 PM George Kennedy
wrote:
On 10/25/2021 3:07 PM, Greg KH wrote:
On Mon, Oct 25, 2021 at
On Tue, Oct 26, 2021 at 11:59:35AM +0300, Joonas Lahtinen wrote:
> Quoting Matthew Brost (2021-10-25 18:15:09)
> > On Mon, Oct 25, 2021 at 12:37:02PM +0300, Joonas Lahtinen wrote:
> > > Quoting Matthew Brost (2021-10-22 19:42:19)
> > > > On Fri, Oct 22, 2021 at 12:35:04PM +0300, Joonas Lahtinen wro
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> rx_callback is a standard mailbox callback mechanism and could cover the
> function of proprietary cmdq_task_cb, so use the standard one instead of
> the proprietary one.
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-b
On Tue, Oct 26, 2021 at 11:59:35AM +0300, Joonas Lahtinen wrote:
> Quoting Matthew Brost (2021-10-25 18:15:09)
> > On Mon, Oct 25, 2021 at 12:37:02PM +0300, Joonas Lahtinen wrote:
> > > Quoting Matthew Brost (2021-10-22 19:42:19)
> > > > On Fri, Oct 22, 2021 at 12:35:04PM +0300, Joonas Lahtinen wro
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> In mailbox rx_callback, it pass struct mbox_client to callback
> function, but it could not map back to mtk_drm_crtc instance
> because struct cmdq_client use a pointer to struct mbox_client:
>
> struct cmdq_client {
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> CMDQ is used to update display register in vblank period, so
> it should be execute in next 2 vblank. One vblank interrupt
> before send message (occasionally) and one vblank interrupt
> after cmdq done. If it fail to
On 2021-10-21 at 17:27:08 +0300, Lisovskiy, Stanislav wrote:
> On Thu, Oct 21, 2021 at 07:56:23PM +0530, Ramalingam C wrote:
> > From: Stanislav Lisovskiy
> >
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be su
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Chun-Kuang Hu
>
> One mtk_crtc need just one cmdq_handle, so add one cmdq_handle
> in mtk_crtc to prevent frequently allocation and free of
> cmdq_handle.
>
> Signed-off-by: Chun-Kuang Hu
> Signed-off-by: jason-jh.lin
> ---
> driver
Am 2021-10-25 um 12:16 a.m. schrieb Alistair Popple:
> MIGRATE_PFN_LOCKED is used to indicate to migrate_vma_prepare() that a
> source page was already locked during migrate_vma_collect(). If it
> wasn't then the a second attempt is made to lock the page. However if
> the first attempt failed it's
Hi, Jason:
jason-jh.lin 於 2021年10月26日 週二 下午1:29寫道：
>
> From: Yongqiang Niu
>
> In cmdq mode, packet may be flushed before it is executed, so
> the pending flag should be cleared after cmdq packet is done.
Reviewed-by: Chun-Kuang Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: jason-jh.l
The huge page functionality in TTM does not work safely because PUD and
PMD entries do not have a special bit.
get_user_pages_fast() considers any page that passed pmd_huge() as
usable:
if (unlikely(pmd_trans_huge(pmd) || pmd_huge(pmd) ||
pmd_devmap(pmd))) {
And vmf_
sbios settings
given suggestion this may be a BIOS issue, I've posted this issue as a question
@,
https://forum.asrock.com/forum_posts.asp?TID=19749&title=x470d4u-p4-20-ryzen5600g-fatal-error-gpu-boot
and pinged ASRockRack tech support via their online tech supp form.
If anyone _here_ kno
Hi George,
On Tue, Oct 26, 2021 at 5:48 PM George Kennedy
wrote:
> On 10/26/2021 10:11 AM, Geert Uytterhoeven wrote:
> > On Tue, Oct 26, 2021 at 3:38 PM George Kennedy
> > wrote:
> >> On 10/26/2021 4:30 AM, Geert Uytterhoeven wrote:
> >>> On Mon, Oct 25, 2021 at 9:37 PM George Kennedy
> >>> wro
Hi "Thomas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next airlied/drm-next v5.15-rc7 next-20211026]
[If your patch is applied to the wron
Linking the CMA frambuffer helpers into a CMA helper library in
commit 4b2b5e142ff4 ("drm: Move GEM memory managers into modules")
results in linker errors:
arm-linux-gnueabihf-ld: drivers/gpu/drm/drm_fb_cma_helper.o: \
in function `drm_fb_cma_get_gem_obj': \
drivers/gpu/drm/
Hi
Am 25.10.21 um 16:01 schrieb Naresh Kamboju:
On Mon, 25 Oct 2021 at 17:43, Naresh Kamboju wrote:
Regression found on arm gcc-11 built with multi_v5_defconfig
Following build warnings / errors reported on linux next 20211025.
metadata:
git_describe: next-20211025
git_repo: https:
Instead of having one 'hwdesc' variable for the plane #0, one for the
plane #1 and one for the palette, use a 'hwdesc[3]' array, where the
DMA hardware descriptors are indexed by the plane's number.
v2: dma_hwdesc_addr() extended to support palette hwdesc. The palette
hwdesc is now hwdesc[3] t
Until now, the ingenic-drm as well as the ingenic-ipu drivers used to
put state-specific information in their respective private structure.
Add boilerplate code to support private objects in the two drivers, so
that state-specific information can be put in the state-specific private
structure.
Si
The IPU scaling information is computed in the plane's ".atomic_check"
callback, and used in the ".atomic_update" callback. As such, it is
state-specific, and should be moved to a private state structure.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-ipu.c | 73 +++
Hi,
I resend the V3 of my patchset for drm/ingenic, verbatim.
The previous submission of my V3 received a lot of replies, but none of
these replies were actually talking about the patches themselves.
Cheers,
-Paul
Paul Cercueil (6):
drm/ingenic: Simplify code by using hwdescs array
drm/ing
Setting the DMA descriptor chain register in the probe function has been
fine until now, because we only ever had one descriptor per foreground.
As the driver will soon have real descriptor chains, and the DMA
descriptor chain register updates itself to point to the current
descriptor being proces
When using C8 color mode, make sure that the palette is always uploaded
before a frame; otherwise the very first frame will have wrong colors.
Do that by changing the link order of the DMA descriptors.
v3: Fix ingenic_drm_get_new_priv_state() called instead of
ingenic_drm_get_priv_state()
Si
Attach a top-level bridge to each encoder, which will be used for
negociating the bus format and flags.
All the bridges are now attached with DRM_BRIDGE_ATTACH_NO_CONNECTOR.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 92 +--
1 file changed,
Hi
Am 25.10.21 um 14:13 schrieb Naresh Kamboju:
Regression found on arm gcc-11 built with multi_v5_defconfig
Following build warnings / errors reported on linux next 20211025.
metadata:
git_describe: next-20211025
git_repo: https://gitlab.com/Linaro/lkft/mirrors/next/linux-next
g
Hi Thomas,
On Tue, Oct 26, 2021 at 07:57:00PM +0200, Thomas Zimmermann wrote:
> Linking the CMA frambuffer helpers into a CMA helper library in
> commit 4b2b5e142ff4 ("drm: Move GEM memory managers into modules")
> results in linker errors:
>
> arm-linux-gnueabihf-ld: drivers/gpu/drm/drm_fb_cma
Hi Paul,
> Am 26.10.2021 um 20:12 schrieb Paul Cercueil :
>
> Hi,
>
> I resend the V3 of my patchset for drm/ingenic, verbatim.
>
> The previous submission of my V3 received a lot of replies, but none of
> these replies were actually talking about the patches themselves.
Indeed. And since we h
Hi Stephen,
On 2021-10-21 23:32, Stephen Boyd wrote:
Quoting Sankeerth Billakanti (2021-10-20 05:14:10)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 62e75dc..9fea49c 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@
Hi,
On Mon, Oct 25, 2021 at 1:10 PM Stephen Boyd wrote:
>
> Quoting Philip Chen (2021-10-21 14:06:00)
> > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
> > b/drivers/gpu/drm/bridge/parade-ps8640.c
> > index 220ca3b03d24..f99a2e0808b7 100644
> > --- a/drivers/gpu/drm/bridge/parade-ps8640.c
Hi Mario,
On Tue, Oct 26, 2021 at 01:27:37PM +0200, Mario wrote:
> Fixes screen orientation for GPD Win 3 handheld gaming console.
>
> Signed-off-by: Mario Risoldi
Thanks for the resend.
A couple of points for your, hopefully soonish, next contribution:
1) Use the same name/email in the Signed
Fit ps8640 driver into runtime power management framework:
First, break _poweron() to 3 parts: (1) turn on power and wait for
ps8640's internal MCU to finish init (2) check panel HPD (which is
proxied by GPIO9) (3) the other configs. As runtime_resume() can be
called before panel is powered, we on
Conventionally, panel is listed under the root of the device tree.
When userland asks for display mode, ps8640 bridge is responsible
for returning EDID when ps8640_bridge_get_edid() is called.
Now enable a new option of listing panel under "aux-bus" of ps8640
bridge node in the device tree. In thi
Hi Nikolaus,
On Tue, Oct 26, 2021 at 08:50:19PM +0200, H. Nikolaus Schaller wrote:
> Hi Paul,
>
> > Am 26.10.2021 um 20:12 schrieb Paul Cercueil :
> >
> > Hi,
> >
> > I resend the V3 of my patchset for drm/ingenic, verbatim.
> >
> > The previous submission of my V3 received a lot of replies, bu
Hi
On Mon, Oct 25, 2021 at 1:05 PM Stephen Boyd wrote:
>
> Quoting Philip Chen (2021-10-21 14:05:59)
> > Fit ps8640 driver into runtime power management framework:
> >
> > First, break _poweron() to 3 parts: (1) turn on power and wait for
> > ps8640's internal MCU to finish init (2) check panel H
From: Mark Yacoub
[Why]
This function and enum do not do generic checking on the luts but they
test color channels in the LUTs.
Keeping the name explicit as more generic LUT checks will follow.
Tested on Eldrid ChromeOS (TGL).
Signed-off-by: Mark Yacoub
---
drivers/gpu/drm/drm_color_mgmt.c
From: Mark Yacoub
[Why]
1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
or Degamma props in the new CRTC state, allowing any invalid size to
be passed on.
2. Each driver has its own LUT size, which could also be different for
legacy users.
[How]
1. Create |degamma_lut_
From: Mark Yacoub
[Why]
drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
sizes. There is no need to check it within amdgpu_dm_atomic_check.
[How]
Remove the local call to verify LUT sizes and use DRM Core function
instead.
Tested on ChromeOS Zork.
v1:
Remove amdgpu_dm_v
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