C/20210816-220020
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a006-20210817 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project
2c6448cdc2f68f8c28fd0bd9404182b81306e6e6)
reproduce (this is a W=1 build):
w
Hi Sam,
On Mon, Aug 16, 2021 at 11:36:13PM +0200, Sam Ravnborg wrote:
> Hi Markus,
>
> A few general things in the following. This is what I look for first in
> a bridge driver - and I had no time today to review the driver in full.
> Please address these, then cc: me on next revision where I hop
Hi,
On Tue, Aug 17, 2021 at 01:36:45PM +0800, CK Hu wrote:
> Hi, Markus:
>
> On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote:
> > This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
> >
> > It supports both functional units on the mt8195, the embedded
> > Display
[AMD Official Use Only]
> -Original Message-
> From: amd-gfx On Behalf Of
> Michel Dänzer
> Sent: Monday, August 16, 2021 6:35 PM
> To: Deucher, Alexander ; Koenig, Christian
>
> Cc: Liu, Leo ; Zhu, James ; amd-
> g...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: [
On 17-08-21, 04:27, Dmitry Osipenko wrote:
> Add dev_pm_opp_sync() helper which syncs OPP table with hardware state
> and vice versa.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/opp/core.c | 42 +++---
> include/linux/pm_opp.h | 6 ++
> 2 files
On 8/17/2021 1:21 PM, Quan, Evan wrote:
[AMD Official Use Only]
-Original Message-
From: amd-gfx On Behalf Of
Michel Dänzer
Sent: Monday, August 16, 2021 6:35 PM
To: Deucher, Alexander ; Koenig, Christian
Cc: Liu, Leo ; Zhu, James ; amd-
g...@lists.freedesktop.org; dri-devel@list
On 8/17/21 5:01 AM, Dmitry Osipenko wrote:
Fix troubles introduced by recent commits.
Dmitry Osipenko (3):
drm/tegra: dc: Remove unused variables
drm/tegra: uapi: Fix wrong mapping end address in case of disabled
IOMMU
gpu/host1x: fence: Make spinlock static
drivers/gpu/drm/tegr
From: Michel Dänzer
schedule_delayed_work does not push back the work if it was already
scheduled before, so amdgpu_device_delay_enable_gfx_off ran ~100 ms
after the first time GFXOFF was disabled and re-enabled, even if GFXOFF
was disabled and re-enabled again during those 100 ms.
This resulted
On Fri, Aug 13, 2021 at 11:59:23AM -0500, Tom Lendacky wrote:
> Introduce a powerpc version of the prot_guest_has() function. This will
> be used to replace the powerpc mem_encrypt_active() implementation, so
> the implementation will initially only support the PATTR_MEM_ENCRYPT
> attribute.
>
> C
The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
hence the panel settings that were retrieved with a FEX dump are named
after the device NOT the actual panel.
The LCD in question is a 50 pin MISO TFT LCD panel of the resolution
1024x600 used by the aforementioned device.
Sign
This is a very confusingly named function, because not just does it
init an object, it arms it and provides a point of no return for
pushing a job into the scheduler. It would be nice if that's a bit
clearer in the interface.
But the real reason is that I want to push the dependency tracking
helpe
On 2021-08-17 10:17 a.m., Lazar, Lijo wrote:
> On 8/17/2021 1:21 PM, Quan, Evan wrote:
>>> -Original Message-
>>> From: amd-gfx On Behalf Of
>>> Michel Dänzer
>>> Sent: Monday, August 16, 2021 6:35 PM
>>> To: Deucher, Alexander ; Koenig, Christian
>>>
>>> Cc: Liu, Leo ; Zhu, James ; amd-
Originally drm_sched_job_init was the point of no return, after which
drivers really should submit a job. I've split that up, which allows
us to fix this issue pretty easily.
Only thing we have to take care of is to not skip to error paths after
that. Other drivers do this the same for out-fence a
On Fri, Aug 13, 2021 at 11:59:24AM -0500, Tom Lendacky wrote:
> diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c
> index edc67ddf065d..5635ca9a1fbe 100644
> --- a/arch/x86/mm/mem_encrypt.c
> +++ b/arch/x86/mm/mem_encrypt.c
> @@ -144,7 +144,7 @@ void __init sme_unmap_bootdata(char
Am 17.08.21 um 00:29 schrieb Rob Clark:
dma_fence_array looks simple enough, just propagate the deadline to
all children.
I guess dma_fence_chain is similar (ie. fence is signalled when all
children are signalled), the difference being simply that children are
added dynamically?
No, new chain
On Mon, Aug 16, 2021 at 08:58:49AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/16/2021 8:15 AM, Daniel Vetter wrote:
> > On Fri, Aug 13, 2021 at 08:18:02AM -0700, Daniele Ceraolo Spurio wrote:
> > >
> > > On 8/13/2021 7:37 AM, Daniel Vetter wrote:
> > > > On Wed, Jul 28, 2021 at 07:01:01PM -
On Mon, Aug 16, 2021 at 03:25:20PM -0700, Rob Clark wrote:
> On Mon, Aug 16, 2021 at 8:38 AM Daniel Vetter wrote:
> >
> > On Mon, Aug 16, 2021 at 12:14:35PM +0200, Christian König wrote:
> > > Am 07.08.21 um 20:37 schrieb Rob Clark:
> > > > From: Rob Clark
> > > >
> > > > As the finished fence is
On 8/17/2021 1:53 PM, Michel Dänzer wrote:
From: Michel Dänzer
schedule_delayed_work does not push back the work if it was already
scheduled before, so amdgpu_device_delay_enable_gfx_off ran ~100 ms
after the first time GFXOFF was disabled and re-enabled, even if GFXOFF
was disabled and re-e
Add support type switch by pericfg register between USB3, PCIe,
SATA, SGMII, this is used to replace the way through efuse or
jumper.
Reviewed-by: Rob Herring
Signed-off-by: Chunfeng Yun
---
v3: no changes
v2: add reviewed-by Rob
---
.../devicetree/bindings/phy/mediatek,tphy.yaml | 16 +++
Print error log using child devices instead of parent device.
Signed-off-by: Chunfeng Yun
---
v2~3: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
b/drivers/phy/mediatek/phy-mt
Use clock bulk helpers to get/enable/disable clocks
Signed-off-by: Chunfeng Yun
---
v2~3: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 43 +
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
b/drivers/phy/medi
devm_ioremap_resource() will print log if error happens.
Signed-off-by: Chunfeng Yun
---
v2~3: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c
b/drivers/phy/mediatek/phy-mtk-tphy.c
index 9d4b34298137..cdce
Add support type switch between USB3, PCIe, SATA and SGMII by
pericfg register, this is used to take the place of efuse or
jumper.
Signed-off-by: Chunfeng Yun
---
v2~3: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 84 -
1 file changed, 82 insertions(+), 2 dele
Use devm_platform_ioremap_resource to simplify code
Acked-by: Chun-Kuang Hu
Signed-off-by: Chunfeng Yun
---
v3: no changes
v2: add acked-by CK
---
drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi
Use clock bulk helpers to get/enable/disable clocks
Reviewed-by: Stanley Chu
Signed-off-by: Chunfeng Yun
---
v3: add reviewed-by Stanley
v2: no changes
---
drivers/phy/mediatek/phy-mtk-ufs.c | 44 --
1 file changed, 11 insertions(+), 33 deletions(-)
diff --git a/dri
Return the error number directly without assignment
Acked-by: Chun-Kuang Hu
Signed-off-by: Chunfeng Yun
---
v3: no changes
v2: add acked-by CK
---
drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-
Use devm_platform_ioremap_resource to simplify code
Acked-by: Chun-Kuang Hu
Signed-off-by: Chunfeng Yun
---
v3: no changes
v2: add acked-by CK
---
drivers/phy/mediatek/phy-mtk-hdmi.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c
On Mon, Aug 16, 2021 at 06:51:23AM -0700, Matthew Brost wrote:
> Progagating errors to dependent fences is wrong, don't do it. Selftest
> in following patch exposes this bug.
Please explain what "this bug" is, it's hard to read minds, especially at
a distance in spacetime :-)
> Fixes: 8e9f84cf5ca
On 2021-08-17 11:12 a.m., Lazar, Lijo wrote:
>
>
> On 8/17/2021 1:53 PM, Michel Dänzer wrote:
>> From: Michel Dänzer
>>
>> schedule_delayed_work does not push back the work if it was already
>> scheduled before, so amdgpu_device_delay_enable_gfx_off ran ~100 ms
>> after the first time GFXOFF was
On Mon, Aug 16, 2021 at 06:51:22AM -0700, Matthew Brost wrote:
> If the context is reset as a result of the request cancelation the
> context reset G2H is received after schedule disable done G2H which is
> likely the wrong order. The schedule disable done G2H release the
> waiting request cancelat
[AMD Official Use Only]
Thanks! This seems fine to me.
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Michel Dänzer
> Sent: Tuesday, August 17, 2021 4:23 PM
> To: Deucher, Alexander ; Koenig, Christian
>
> Cc: Liu, Leo ; Zhu, James ; amd-
> g...@lists.freede
On 8/17/2021 2:56 PM, Michel Dänzer wrote:
On 2021-08-17 11:12 a.m., Lazar, Lijo wrote:
On 8/17/2021 1:53 PM, Michel Dänzer wrote:
From: Michel Dänzer
schedule_delayed_work does not push back the work if it was already
scheduled before, so amdgpu_device_delay_enable_gfx_off ran ~100 ms
a
On Mon, Aug 16, 2021 at 06:51:19AM -0700, Matthew Brost wrote:
> A small race that could result in incorrect accounting of the number
> of outstanding G2H. Basically prior to this patch we did not increment
> the number of outstanding G2H if we encoutered a GT reset while sending
> a H2G. This was
On 7/2/21 8:07 PM, Marek Vasut wrote:
> On 7/2/21 11:23 AM, Raphael Gallais-Pou wrote:
>> Hello Marek,
>
> Hi,
>
>> Sorry for the late answer.
>
> No worries, take your time
>
>> On 6/30/21 2:35 AM, Marek Vasut wrote:
>>> On 6/29/21 1:58 PM, Raphael GALLAIS-POU - foss wrote:
>>>
>>> [...]
>>>
>>>
On Mon, Aug 16, 2021 at 06:51:25AM -0700, Matthew Brost wrote:
> When unblocking a context, do not enable scheduling if the context is
> banned, guc_id invalid, or not registered.
>
> Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
> Signed-off-by: Matthew Brost
> Cc:
> ---
>
Hi, Markus:
On Mon, 2021-08-16 at 21:25 +0200, Markus Schneider-Pargmann wrote:
> dpintf is the displayport interface hardware unit. This unit is similar
> to dpi and can reuse most of the code.
>
> This patch adds support for mt8195-dpintf to this dpi driver. Main
> differences are:
> - Some fe
On Tue, Aug 17, 2021 at 11:47:53AM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:25AM -0700, Matthew Brost wrote:
> > When unblocking a context, do not enable scheduling if the context is
> > banned, guc_id invalid, or not registered.
> >
> > Fixes: 62eaf0ae217d ("drm/i915/guc: Suppo
On 2021-08-17 11:37 a.m., Lazar, Lijo wrote:
>
>
> On 8/17/2021 2:56 PM, Michel Dänzer wrote:
>> On 2021-08-17 11:12 a.m., Lazar, Lijo wrote:
>>>
>>>
>>> On 8/17/2021 1:53 PM, Michel Dänzer wrote:
From: Michel Dänzer
schedule_delayed_work does not push back the work if it was alre
On Fri, Aug 13, 2021 at 11:59:25AM -0500, Tom Lendacky wrote:
> diff --git a/arch/x86/kernel/machine_kexec_64.c
> b/arch/x86/kernel/machine_kexec_64.c
> index 8e7b517ad738..66ff788b79c9 100644
> --- a/arch/x86/kernel/machine_kexec_64.c
> +++ b/arch/x86/kernel/machine_kexec_64.c
> @@ -167,7 +167,7
On Fri, Aug 13, 2021 at 11:59:26AM -0500, Tom Lendacky wrote:
> Replace occurrences of sev_es_active() with the more generic
> prot_guest_has() using PATTR_GUEST_PROT_STATE, except for in
> arch/x86/kernel/sev*.c and arch/x86/mm/mem_encrypt*.c where PATTR_SEV_ES
> will be used. If future support is
On Mon, Aug 16, 2021 at 06:51:31AM -0700, Matthew Brost wrote:
> Error captures can now be done in a work queue processing G2H messages.
> These messages need to be completely done being processed in the reset
> path, to avoid races in the missing G2H cleanup, which create a
> dependency on memory
On Mon, Aug 16, 2021 at 06:51:32AM -0700, Matthew Brost wrote:
> It isn't safe to scrub for missing G2H or continue with the reset until
> all G2H processing is complete. Flush the G2H work queue during reset to
> ensure it is done running.
>
> Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementat
On Mon, Aug 16, 2021 at 06:51:33AM -0700, Matthew Brost wrote:
> A subsequent patch will flip the locking hierarchy from
> ce->guc_state.lock -> sched_engine->lock to sched_engine->lock ->
> ce->guc_state.lock. As such we need to release the submit fence for a
> request from an IRQ to break a lock
On Mon, Aug 16, 2021 at 06:51:34AM -0700, Matthew Brost wrote:
> Move guc_blocked fence to struct guc_state as the lock which protects
> the fence lives there.
>
> s/ce->guc_blocked/ce->guc_state.blocked_fence/g
>
> Signed-off-by: Matthew Brost
General comment, but latest when your combine your
On Mon, Aug 16, 2021 at 06:51:35AM -0700, Matthew Brost wrote:
> Rework and simplify the locking with GuC subission. Drop
> sched_state_no_lock and move all fields under the guc_state.sched_state
> and protect all these fields with guc_state.lock . This requires
> changing the locking hierarchy fro
On Fri, Aug 13, 2021 at 11:59:28AM -0500, Tom Lendacky wrote:
> The mem_encrypt_active() function has been replaced by prot_guest_has(),
> so remove the implementation.
>
> Reviewed-by: Joerg Roedel
> Signed-off-by: Tom Lendacky
> ---
> include/linux/mem_encrypt.h | 4
> 1 file changed, 4
On 17-08-21, 17:19, Chunfeng Yun wrote:
> Add support type switch by pericfg register between USB3, PCIe,
> SATA, SGMII, this is used to replace the way through efuse or
> jumper.
Applied all, thanks
--
~Vinod
On Tue, Aug 17, 2021 at 12:22:33PM +0200, Borislav Petkov wrote:
> This one wants to be part of the previous patch.
... and the three following patches too - the treewide patch does a
single atomic :) replacement and that's it.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-a
On Mon, Aug 16, 2021 at 06:51:36AM -0700, Matthew Brost wrote:
> Lock the xarray and take ref to the context if needed.
>
> v2:
> (Checkpatch)
> - Add new line after declaration
>
> Signed-off-by: Matthew Brost
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 84 ---
>
On 8/17/2021 3:29 PM, Michel Dänzer wrote:
On 2021-08-17 11:37 a.m., Lazar, Lijo wrote:
On 8/17/2021 2:56 PM, Michel Dänzer wrote:
On 2021-08-17 11:12 a.m., Lazar, Lijo wrote:
On 8/17/2021 1:53 PM, Michel Dänzer wrote:
From: Michel Dänzer
schedule_delayed_work does not push back the
On 2021-08-17 12:37 p.m., Lazar, Lijo wrote:
>
>
> On 8/17/2021 3:29 PM, Michel Dänzer wrote:
>> On 2021-08-17 11:37 a.m., Lazar, Lijo wrote:
>>>
>>>
>>> On 8/17/2021 2:56 PM, Michel Dänzer wrote:
On 2021-08-17 11:12 a.m., Lazar, Lijo wrote:
>
>
> On 8/17/2021 1:53 PM, Michel Dän
On Mon, Aug 16, 2021 at 06:51:39AM -0700, Matthew Brost wrote:
> Add GuC kernel doc for all structures added thus far for GuC submission
> and update the main GuC submission section with the new interface
> details.
>
> Signed-off-by: Matthew Brost
There's quite a bit more, e.g. intel_guc_ct, wh
On 8/17/2021 4:36 PM, Michel Dänzer wrote:
On 2021-08-17 12:37 p.m., Lazar, Lijo wrote:
On 8/17/2021 3:29 PM, Michel Dänzer wrote:
On 2021-08-17 11:37 a.m., Lazar, Lijo wrote:
On 8/17/2021 2:56 PM, Michel Dänzer wrote:
On 2021-08-17 11:12 a.m., Lazar, Lijo wrote:
On 8/17/2021 1:53 P
On Tue, 17 Aug 2021 at 03:30, Dmitry Osipenko wrote:
>
> Add runtime PM and OPP support to the Host1x driver. It's required for
> enabling system-wide DVFS and supporting dynamic power management using
> a generic power domain. For the starter we will keep host1x always-on
> because dynamic power
On Tue, Aug 17, 2021 at 04:27:42AM +0300, Dmitry Osipenko wrote:
> The SPI on Tegra belongs to the core power domain and we're going to
> enable GENPD support for the core domain. Now SPI driver must use OPP
> API for driving the controller's clock rate because OPP API takes care
> of reconfiguring
Hi,
This adds some more pixel formats and gives the user the ability to
choose the xrgb emulation format.
Pixel formats:
R8: For greyscale e-ink displays
RGB332: For e-ink displays and some niche displays
RGB888: Same color depth as XRGB but the smaller buffer gives better
fps
Noralf.
Add an entry in drm_format_info for the existing format DRM_FORMAT_R8.
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/drm_fourcc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index eda832f9200d..783844bfecc1 100644
--- a/driv
Add support for the RGB332 pixel format.
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/gud/gud_drv.c | 2 ++
drivers/gpu/drm/gud/gud_internal.h | 4
drivers/gpu/drm/gud/gud_pipe.c | 2 ++
include/drm/gud.h | 1 +
4 files changed, 9 insertions(+)
diff --git a/d
Add XRGB emulation support for devices that can only do RGB332.
Cc: Thomas Zimmermann
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/drm_format_helper.c | 47 +
include/drm/drm_format_helper.h | 2 ++
2 files changed, 49 insertions(+)
diff --git a/driver
Add support for the RGB888 pixel format.
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/gud/gud_drv.c | 2 ++
drivers/gpu/drm/gud/gud_internal.h | 4
drivers/gpu/drm/gud/gud_pipe.c | 2 ++
include/drm/gud.h | 1 +
4 files changed, 9 insertions(+)
diff --git a/d
Add XRGB emulation support for devices that can only do RGB888.
Cc: Thomas Zimmermann
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/drm_format_helper.c | 38 +
include/drm/drm_format_helper.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/driver
Add support for 8-bit greyscale format.
Signed-off-by: Noralf Trønnes
---
drivers/gpu/drm/gud/gud_drv.c | 2 ++
drivers/gpu/drm/gud/gud_internal.h | 4
drivers/gpu/drm/gud/gud_pipe.c | 2 ++
include/drm/gud.h | 4 ++--
4 files changed, 10 insertions(+), 2 deletions
For devices that don't support XRGB give the user the ability to
choose what's most important: Color depth or frames per second.
Add an 'xrgb' module parameter to override the emulation format.
Assume the user wants full control if xrgb is set and don't set
DRM_CAP_DUMB_PREFERRED_DEPT
Tom Lendacky writes:
> Introduce a powerpc version of the prot_guest_has() function. This will
> be used to replace the powerpc mem_encrypt_active() implementation, so
> the implementation will initially only support the PATTR_MEM_ENCRYPT
> attribute.
>
> Cc: Michael Ellerman
> Cc: Benjamin Herre
On 8/17/2021 5:19 PM, Lazar, Lijo wrote:
On 8/17/2021 4:36 PM, Michel Dänzer wrote:
On 2021-08-17 12:37 p.m., Lazar, Lijo wrote:
On 8/17/2021 3:29 PM, Michel Dänzer wrote:
On 2021-08-17 11:37 a.m., Lazar, Lijo wrote:
On 8/17/2021 2:56 PM, Michel Dänzer wrote:
On 2021-08-17 11:12 a.m
On Tue, Aug 17, 2021 at 02:29:17PM +0200, Noralf Trønnes wrote:
> For devices that don't support XRGB give the user the ability to
> choose what's most important: Color depth or frames per second.
>
> Add an 'xrgb' module parameter to override the emulation format.
>
> Assume the user wan
On Tue, Aug 17, 2021 at 02:29:12PM +0200, Noralf Trønnes wrote:
> Add XRGB emulation support for devices that can only do RGB332.
>
> Cc: Thomas Zimmermann
> Signed-off-by: Noralf Trønnes
> ---
> drivers/gpu/drm/drm_format_helper.c | 47 +
> include/drm/drm_forma
On Tue, Aug 17, 2021 at 02:29:11PM +0200, Noralf Trønnes wrote:
> Add an entry in drm_format_info for the existing format DRM_FORMAT_R8.
>
> Signed-off-by: Noralf Trønnes
> ---
> drivers/gpu/drm/drm_fourcc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b
On Tue, Aug 17, 2021 at 02:04:38PM +0200, Ulf Hansson wrote:
> On Tue, 17 Aug 2021 at 03:30, Dmitry Osipenko wrote:
> >
> > Add runtime PM and OPP support to the Host1x driver. It's required for
> > enabling system-wide DVFS and supporting dynamic power management using
> > a generic power domain.
On Tue, Aug 17, 2021 at 02:29:13PM +0200, Noralf Trønnes wrote:
> Add XRGB emulation support for devices that can only do RGB888.
>
> Cc: Thomas Zimmermann
> Signed-off-by: Noralf Trønnes
> ---
> drivers/gpu/drm/drm_format_helper.c | 38 +
> include/drm/drm_forma
On 8/17/21 3:35 AM, Borislav Petkov wrote:
> On Fri, Aug 13, 2021 at 11:59:23AM -0500, Tom Lendacky wrote:
>> Introduce a powerpc version of the prot_guest_has() function. This will
>> be used to replace the powerpc mem_encrypt_active() implementation, so
>> the implementation will initially only s
Den 17.08.2021 15.49, skrev Daniel Vetter:
> On Tue, Aug 17, 2021 at 02:29:17PM +0200, Noralf Trønnes wrote:
>> For devices that don't support XRGB give the user the ability to
>> choose what's most important: Color depth or frames per second.
>>
>> Add an 'xrgb' module parameter to over
On Tue, Aug 17, 2021 at 09:37:00AM -0400, George Kennedy wrote:
> Hello Thomas,
>
> I sent this backport request to sta...@vger.kernel.org a while ago including
> the maintainers, but mistakenly did not CC you. Sorry about that.
>
> Can you please review this backport request for 5.4.y? Greg is w
On Tue, Aug 17, 2021 at 03:59:56PM +0200, Daniel Vetter wrote:
> On Tue, Aug 17, 2021 at 02:29:11PM +0200, Noralf Trønnes wrote:
> > Add an entry in drm_format_info for the existing format DRM_FORMAT_R8.
> >
> > Signed-off-by: Noralf Trønnes
> > ---
> > drivers/gpu/drm/drm_fourcc.c | 1 +
> > 1
On Tue, Aug 17, 2021 at 05:01:50AM +0300, Dmitry Osipenko wrote:
> Fix troubles introduced by recent commits.
>
> Dmitry Osipenko (3):
> drm/tegra: dc: Remove unused variables
> drm/tegra: uapi: Fix wrong mapping end address in case of disabled
> IOMMU
> gpu/host1x: fence: Make spinlock
From: Colin Ian King
There is a spelling mistake in a dev_err error message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gp
On Tue, Aug 17, 2021 at 10:32:01AM +0200, Nikola Pavlica wrote:
> The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
> hence the panel settings that were retrieved with a FEX dump are named
> after the device NOT the actual panel.
>
> The LCD in question is a 50 pin MISO TFT LCD
On 8/17/21 4:00 AM, Borislav Petkov wrote:
> On Fri, Aug 13, 2021 at 11:59:24AM -0500, Tom Lendacky wrote:
>> diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c
>> index edc67ddf065d..5635ca9a1fbe 100644
>> --- a/arch/x86/mm/mem_encrypt.c
>> +++ b/arch/x86/mm/mem_encrypt.c
>> @@ -14
Greetings,
Original proposal:
https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg62387.html
Abstract: Add "preferred color format", "active color format", "active
bpc", and "active Broadcast RGB" drm properties,
to control color information send to the monitor.
It seems that the
On 16/8/21 9:59 pm, Daniel Vetter wrote:
On Mon, Aug 16, 2021 at 12:31 PM Desmond Cheong Zhi Xi
wrote:
On 16/8/21 5:04 pm, Daniel Vetter wrote:
On Mon, Aug 16, 2021 at 10:53 AM Desmond Cheong Zhi Xi
wrote:
On 16/8/21 2:47 am, kernel test robot wrote:
Hi Desmond,
Thank you for the patch! Y
On Tue, Aug 17, 2021 at 11:32:56AM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:22AM -0700, Matthew Brost wrote:
> > If the context is reset as a result of the request cancelation the
> > context reset G2H is received after schedule disable done G2H which is
> > likely the wrong orde
On Tue, Aug 17, 2021 at 11:21:27AM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:23AM -0700, Matthew Brost wrote:
> > Progagating errors to dependent fences is wrong, don't do it. Selftest
> > in following patch exposes this bug.
>
> Please explain what "this bug" is, it's hard to re
On 8/15/21 9:39 AM, Borislav Petkov wrote:
> On Sun, Aug 15, 2021 at 08:53:31AM -0500, Tom Lendacky wrote:
>> It's not a cross-vendor thing as opposed to a KVM or other hypervisor
>> thing where the family doesn't have to be reported as AMD or HYGON.
>
> What would be the use case? A HV starts a g
On 8/17/21 5:02 AM, Borislav Petkov wrote:
> On Fri, Aug 13, 2021 at 11:59:25AM -0500, Tom Lendacky wrote:
>> diff --git a/arch/x86/kernel/machine_kexec_64.c
>> b/arch/x86/kernel/machine_kexec_64.c
>> index 8e7b517ad738..66ff788b79c9 100644
>> --- a/arch/x86/kernel/machine_kexec_64.c
>> +++ b/arch
On 8/17/21 5:24 AM, Borislav Petkov wrote:
> On Tue, Aug 17, 2021 at 12:22:33PM +0200, Borislav Petkov wrote:
>> This one wants to be part of the previous patch.
>
> ... and the three following patches too - the treewide patch does a
> single atomic :) replacement and that's it.
Ok, I'll squash t
On Tue, Aug 17, 2021 at 12:27:29PM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:36AM -0700, Matthew Brost wrote:
> > Lock the xarray and take ref to the context if needed.
> >
> > v2:
> > (Checkpatch)
> > - Add new line after declaration
> >
> > Signed-off-by: Matthew Brost
> >
On Tue, Aug 17, 2021 at 12:15:21PM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:35AM -0700, Matthew Brost wrote:
> > Rework and simplify the locking with GuC subission. Drop
> > sched_state_no_lock and move all fields under the guc_state.sched_state
> > and protect all these fields w
Am 2021-08-17 um 1:50 a.m. schrieb Christoph Hellwig:
> On Mon, Aug 16, 2021 at 03:00:49PM -0400, Felix Kuehling wrote:
>> Am 2021-08-15 um 11:40 a.m. schrieb Christoph Hellwig:
>>> On Fri, Aug 13, 2021 at 01:31:45AM -0500, Alex Sierra wrote:
Add MEMORY_DEVICE_GENERIC case to free_zone_device_
Hi Nikola,
see a few comments in the following.
On Tue, Aug 17, 2021 at 10:32:01AM +0200, Nikola Pavlica wrote:
> The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
> hence the panel settings that were retrieved with a FEX dump are named
> after the device NOT the actual panel.
17.08.2021 10:55, Viresh Kumar пишет:
...
>> +int dev_pm_opp_sync(struct device *dev)
>> +{
>> +struct opp_table *opp_table;
>> +struct dev_pm_opp *opp;
>> +int ret = 0;
>> +
>> +/* Device may not have OPP table */
>> +opp_table = _find_opp_table(dev);
>> +if (IS_ERR(opp_tab
On Tue, Aug 17, 2021 at 5:13 PM Matthew Brost wrote:
> On Tue, Aug 17, 2021 at 11:21:27AM +0200, Daniel Vetter wrote:
> > On Mon, Aug 16, 2021 at 06:51:23AM -0700, Matthew Brost wrote:
> > > Progagating errors to dependent fences is wrong, don't do it. Selftest
> > > in following patch exposes thi
17.08.2021 15:22, Mark Brown пишет:
> On Tue, Aug 17, 2021 at 04:27:42AM +0300, Dmitry Osipenko wrote:
>> The SPI on Tegra belongs to the core power domain and we're going to
>> enable GENPD support for the core domain. Now SPI driver must use OPP
>> API for driving the controller's clock rate beca
The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
hence the panel settings that were retrieved with a FEX dump are named
after the device NOT the actual panel.
The LCD in question is a 50 pin MISO TFT LCD panel of the resolution
1024x600 used by the aforementioned device.
Vers
Daniel Vetter wrote:
> Also I just realized we've totally ignored endianess on these, which is
> not great, because strictly speaking all the drm_fourcc codes should be
> little endian. But I'm also not sure that's worth fixing ...
We discussed framebuffer endianess when introducing the driver,
in
On Tue, Aug 17, 2021 at 12:06:16PM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:31AM -0700, Matthew Brost wrote:
> > Error captures can now be done in a work queue processing G2H messages.
> > These messages need to be completely done being processed in the reset
> > path, to avoid r
From: Colin Ian King
The variable delta is not initialized and this will cause unexpected
behaviour with the comparison of tmpdelta < delta. Fix this by setting
it to 0x. This matches the behaviour as in the similar function
mgag200_pixpll_compute_g200se_04.
Addresses-Coverity: ("Uniniti
The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
hence the panel settings that were retrieved with a FEX dump are named
after the device NOT the actual panel.
The LCD in question is a 50 pin MISO TFT LCD panel of the resolution
1024x600 used by the aforementioned device.
Vers
Apologies for the spammy emails, I didn't see Sam's comment on time.
On Tue, Aug 17, 2021 at 6:36 PM Nikola Pavlica
wrote:
> The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
> hence the panel settings that were retrieved with a FEX dump are named
> after the device NOT the a
On Tue, Aug 17, 2021 at 01:11:41PM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:39AM -0700, Matthew Brost wrote:
> > Add GuC kernel doc for all structures added thus far for GuC submission
> > and update the main GuC submission section with the new interface
> > details.
> >
> > Sig
On Tue, Aug 17, 2021 at 11:47:53AM +0200, Daniel Vetter wrote:
> On Mon, Aug 16, 2021 at 06:51:25AM -0700, Matthew Brost wrote:
> > When unblocking a context, do not enable scheduling if the context is
> > banned, guc_id invalid, or not registered.
> >
> > Fixes: 62eaf0ae217d ("drm/i915/guc: Suppo
1 - 100 of 246 matches
Mail list logo
