On Mon, Jul 19, 2021 at 11:25:55AM -0700, John Harrison wrote:
> On 7/19/2021 10:24, Matthew Brost wrote:
> > On Fri, Jul 16, 2021 at 01:17:14PM -0700, Matthew Brost wrote:
> > > From: John Harrison
> > >
> > > The media watchdog mechanism involves GuC doing a silent reset and
> > > continue of t
Hi Zheyu,
On Wed, Jul 14, 2021 at 04:09:22AM +, Zheyu Ma wrote:
> The user can pass in any value to the driver through the 'ioctl'
> interface. The driver dost not check, which may cause DoS bugs.
>
> The following log reveals it:
>
> divide error: [#1] PREEMPT SMP KASAN PTI
> RIP: 0010:
On Thu, Jul 15, 2021 at 09:10:29PM -0700, Daniele Ceraolo Spurio wrote:
> This api allow user mode to create protected buffers and to mark
> contexts as making use of such objects. Only when using contexts
> marked in such a way is the execution guaranteed to work as expected.
>
> Contexts can onl
Hi Geert,
On Wed, Jul 14, 2021 at 04:58:01PM +0200, Geert Uytterhoeven wrote:
> Simplify the nested loops to handle conversion from linear frame buffer
> to ssd1307 page layout:
> 1. Move last page handling one level up, as the value of "m" is the
> same inside a page,
> 2. array->data[] i
Hi Geert,
On Wed, Jul 14, 2021 at 04:58:02PM +0200, Geert Uytterhoeven wrote:
> Extract the code to set the column and page ranges into a helper
> function.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> drivers/video/fbdev/ssd1307fb.c | 61 +++--
> 1 file changed, 36
Hi Geert,
On Wed, Jul 14, 2021 at 04:58:03PM +0200, Geert Uytterhoeven wrote:
> Currently, each screen update triggers an I2C transfer of all screen
> data, up to 1 KiB of data for a 128x64 display, which takes at least 20
> ms in Fast mode.
>
> Reduce the amount of transferred data by only updat
Am 19.07.21 um 20:30 schrieb Jason Ekstrand:
If we have a failure, decrement the reference count so that the next
call to ttm_global_init() will actually do something instead of assume
everything is all set up.
Signed-off-by: Jason Ekstrand
Fixes: 62b53b37e4b1 ("drm/ttm: use a static ttm_bo_glo
Hi Geert,
On Wed, Jul 14, 2021 at 04:57:59PM +0200, Geert Uytterhoeven wrote:
> Hi all,
>
> This patch series optimizes console operations on ssd1307fb, after the
> customary fixes and cleanups.
>
> Currently, each screen update triggers an I2C transfer of all screen
> data, up to 1 KiB of
The graph schema doesn't allow custom properties on endpoint nodes for
'#/properties/port' and '#/$defs/port-base' should be used instead. This
doesn't matter until 'unevaluatedProperties' support is implemented.
Cc: David Airlie
Cc: Daniel Vetter
Cc: Rob Clark
Cc: Sean Paul
Cc: Marek Vasut
C
On Mon, Jul 19, 2021 at 4:10 AM Matthew Auld
wrote:
>
> On Fri, 16 Jul 2021 at 16:23, Jason Ekstrand wrote:
> >
> > On Fri, Jul 16, 2021 at 9:52 AM Tvrtko Ursulin
> > wrote:
> > >
> > >
> > > On 15/07/2021 11:15, Matthew Auld wrote:
> > > > The CPU domain should be static for discrete, and on DG
Hi Rob,
On Mon, Jul 19, 2021 at 01:50:01PM -0600, Rob Herring wrote:
> The graph schema doesn't allow custom properties on endpoint nodes for
> '#/properties/port' and '#/$defs/port-base' should be used instead. This
> doesn't matter until 'unevaluatedProperties' support is implemented.
>
> Cc: Da
On 7/19/21 1:06 AM, Geert Uytterhoeven wrote:
> Hi Randy,
>
> On Mon, Jul 19, 2021 at 4:34 AM Randy Dunlap wrote:
>> When DRM_SIMPLEDRM=m, all of FB_CFB_{FILLRECT,COPYAREA,IMAGEBLIT} are =m,
>
> Why does that happen?
> FB_SIMPLE does select FB_CFB_*, so all of the latter should be builtin?
> Do
Hi Xiyu, Xin,
On Mon, Jul 19, 2021 at 01:59:45PM +0800, Xiyu Yang wrote:
> refcount_t type and corresponding API can protect refcounters from
> accidental underflow and overflow and further use-after-free situations.
>
> Signed-off-by: Xiyu Yang
> Signed-off-by: Xin Tan
Looks like a nice improv
Regards,
Oak
On 2021-07-17, 3:22 PM, "amd-gfx on behalf of Alex Sierra"
wrote:
Two helpers added. One checks if zone device page is generic
type. The other if page is either private or generic type.
Signed-off-by: Alex Sierra
---
include/linux/mm.h | 8
On 7/16/2021 13:16, Matthew Brost wrote:
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a single tasklet submits is used for the submission path.
This still needs fixing - 'a single tasklet submits
On Mon, Jul 19, 2021 at 04:01:56PM -0700, John Harrison wrote:
> On 7/16/2021 13:16, Matthew Brost wrote:
> > Implement GuC submission tasklet for new interface. The new GuC
> > interface uses H2G to submit contexts to the GuC. Since H2G use a single
> > channel, a single tasklet submits is used fo
On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function to virtual
engine specific functions, set all other variables / functions to guc
versions, and set the engine mask to t
On Mon, Jul 19, 2021 at 04:33:56PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/16/2021 1:16 PM, Matthew Brost wrote:
> > Implement GuC virtual engines. Rather simple implementation, basically
> > just allocate an engine, setup context enter / exit function to virtual
> > engine specific funct
On 7/19/2021 4:27 PM, Matthew Brost wrote:
On Mon, Jul 19, 2021 at 04:33:56PM -0700, Daniele Ceraolo Spurio wrote:
On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function t
On Mon, Jul 19, 2021 at 04:42:50PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/19/2021 4:27 PM, Matthew Brost wrote:
> > On Mon, Jul 19, 2021 at 04:33:56PM -0700, Daniele Ceraolo Spurio wrote:
> > >
> > > On 7/16/2021 1:16 PM, Matthew Brost wrote:
> > > > Implement GuC virtual engines. Rathe
On 7/16/2021 1:16 PM, Matthew Brost wrote:
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical
On 7/16/2021 13:16, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
Signed-off-by: John
On 7/19/2021 15:55, Matthew Brost wrote:
On Mon, Jul 19, 2021 at 04:01:56PM -0700, John Harrison wrote:
On 7/16/2021 13:16, Matthew Brost wrote:
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a si
On 7/16/2021 13:16, Matthew Brost wrote:
Semaphores are an optimization and not required for basic GuC submission
to work properly. Disable until we have time to do the implementation to
enable semaphores and tune them for performance. Also long direction is
just to delete semaphores from the i91
Hi,
In the display core, we utilize floats and doubles units for calculating
modesetting parameters. One side effect of our approach to use double-precision
is the fact that we spread multiple FPU access across our driver, which means
that we can accidentally clobber user space FPU state.
# Chall
DC invokes DC_FPU_START/END in multiple parts of the code; this can
create a situation where we invoke this FPU operation in a nested way or
exit too early. For avoiding this situation, this commit adds a
mechanism where dc_fpu_begin/end manages the access to
kernel_fpu_begin/end.
Change since V2:
To fully isolate FPU operations in a single place, we must avoid
situations where compilers spill FP values to registers due to FP enable
in a specific C file. Note that even if we isolate all FPU functions in
a single file and call its interface from other files, the compiler
might enable the use
The display core files rely on FPU, which requires to be compiled with
special flags. Ideally, we don't want these FPU operations spread around
the DC code; nevertheless, it happens in the current source. This commit
introduces a new directory named fpu_operations that intends to
centralize all fil
We don't have any mechanism for tracing FPU operations inside the
display core, making the debug work a little bit tricky. This commit
introduces a trace mechanism inside our DC_FP_START/END macros for
trying to alleviate this problem.
Changes since V2:
- Make sure that we compile FPU operation on
On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
Signed-off-by:
On 7/16/2021 13:16, Matthew Brost wrote:
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2: rtime
On 7/16/2021 13:16, Matthew Brost wrote:
Update GuC debugfs to support the new GuC structures.
v2:
(John Harrison)
- Remove intel_lrc_reg.h include from i915_debugfs.c
(Michal)
- Rename GuC debugfs functions
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Joh
On Tue, Jul 20, 2021 at 12:03 AM Madhurkiran Harikrishnan
wrote:
>
> Hi,
>
> I had created a patch sometimes ago to test on our platform. That is correct,
> we have three clocks going to gp,pp0 and pp1 (Although all are at same rate).
> DVFS is not supported primarily because at zynqmp clocks ar
On 7/16/2021 13:16, Matthew Brost wrote:
Add trace points for request dependencies and GuC submit. Extended
existing request trace points to include submit fence value,, guc_id,
Still has misplaced commas.
Also, Tvrtko has a bunch of comments/questions on the previous version
that need to be a
On 7/16/2021 13:16, Matthew Brost wrote:
From: John Harrison
The serial number tracking of engines happens at the backend of
request submission and was expecting to only be given physical
engines. However, in GuC submission mode, the decomposition of virtual
to physical engines does not happen
On Mon, Jul 19, 2021 at 06:03:05PM -0700, John Harrison wrote:
> On 7/16/2021 13:16, Matthew Brost wrote:
> > When running the GuC the GPU can't be considered idle if the GuC still
> > has contexts pinned. As such, a call has been added in
> > intel_gt_wait_for_idle to idle the UC and in turn the G
On Mon, Jul 19, 2021 at 06:28:47PM -0700, John Harrison wrote:
> On 7/16/2021 13:16, Matthew Brost wrote:
> > From: John Harrison
> >
> > The serial number tracking of engines happens at the backend of
> > request submission and was expecting to only be given physical
> > engines. However, in GuC
On Tue, Jul 13, 2021 at 10:06:17AM +0100, Tvrtko Ursulin wrote:
>
> On 24/06/2021 08:04, Matthew Brost wrote:
> > Add trace points for request dependencies and GuC submit. Extended
> > existing request trace points to include submit fence value,, guc_id,
> > and ring tail value.
> >
> > Cc: John
On Mon, Jul 19, 2021 at 06:27:06PM -0700, John Harrison wrote:
> On 7/16/2021 13:16, Matthew Brost wrote:
> > Add trace points for request dependencies and GuC submit. Extended
> > existing request trace points to include submit fence value,, guc_id,
> Still has misplaced commas.
>
> Also, Tvrtko
On Mon, Jul 19, 2021 at 05:23:55PM -0700, John Harrison wrote:
> On 7/16/2021 13:16, Matthew Brost wrote:
> > Implement GuC context operations which includes GuC specific operations
> > alloc, pin, unpin, and destroy.
> >
> > v2:
> > (Daniel Vetter)
> >- Use msleep_interruptible rather than
On Mon, Jul 19, 2021 at 04:46:57PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/16/2021 1:16 PM, Matthew Brost wrote:
> > If two requests are on the same ring, they are explicitly ordered by the
> > HW. So, a submission fence is sufficient to ensure ordering when using
> > the new GuC submissi
On Mon, Jul 19, 2021 at 07:48:17PM -0700, Matthew Brost wrote:
> On Mon, Jul 19, 2021 at 04:46:57PM -0700, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 7/16/2021 1:16 PM, Matthew Brost wrote:
> > > If two requests are on the same ring, they are explicitly ordered by the
> > > HW. So, a submission
On Mon, Jul 19, 2021 at 05:51:46PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/16/2021 1:16 PM, Matthew Brost wrote:
> > Implement GuC context operations which includes GuC specific operations
> > alloc, pin, unpin, and destroy.
> >
> > v2:
> > (Daniel Vetter)
> >- Use msleep_interrupt
On Mon, Jul 19, 2021 at 4:24 PM Yongqiang Niu
wrote:
>
> in the first version dither patch
> https://patchwork.kernel.org/project/linux-mediatek/patch/1553667561-25447-13-git-send-email-yongqiang@mediatek.com/
> dither 6 setting is included in that patch
I think you don't need to link the firs
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/nouveau/dispnv50/headc57d.c:173:1: warning: no previous
prototype for ‘headc57d_olut’ [-Wmissing-prototypes]
headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
And no header file define a prototype for thi
Change since v2:
- add fixes tag and modify commit message
Yongqiang Niu (1):
Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()
function)
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
1 file changed, 2 insertions(+)
--
1.8.1.1.dirty
dither 6 setting is missed in a6b7c98afdca
bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
bit 2 is rdither_en(Enables running order dithering), need disable
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
1 file changed, 2 insertions(+)
diff -
Hi, Nancy:
On Sat, 2021-07-17 at 17:04 +0800, Nancy.Lin wrote:
> Add pseudo ovl module files:
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
> Two RDMAs merge into one layer, so this module support 4
> layers
Fixes the following W=1 kernel build warning(s):
drivers/gpu/drm/nouveau/nouveau_bo.c: In function ‘nouveau_ttm_tt_populate’:
drivers/gpu/drm/nouveau/nouveau_bo.c:1245:17: warning: variable ‘dev’ set but
not used [-Wunused-but-set-variable]
struct device *dev;
^~~
drivers/gpu/d
On Tue, Jul 20, 2021 at 1:51 PM Yongqiang Niu
wrote:
>
> dither 6 setting is missed in a6b7c98afdca
> bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
> bit 2 is rdither_en(Enables running order dithering), need disable
>
Fixes tag should be here, and the title of this patch should b
Change since v3:
- change tilte and commit message
Yongqiang Niu (1):
Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()
function)
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
1 file changed, 2 insertions(+)
--
1.8.1.1.dirty
Hi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.14-rc2 next-20210719]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()
dither 6 setting is missed in a6b7c98afdca
bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
bit 2 is rdither_en(Enables running order dithering), need disable
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_
Change since v4:
- change commit message
Yongqiang Niu (1):
Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()
function)
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
1 file changed, 2 insertions(+)
--
1.8.1.1.dirty
dither 6 setting is missed in a6b7c98afdca
bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
bit 2 is rdither_en(Enables running order dithering), need disable
Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common())
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk
Hi all,
After merging the drm-intel-fixes tree, today's linux-next build
(htmldocs) produced this warning:
drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter
'jump_whitelist' description in 'intel_engine_cmd_parser'
drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warnin
no need to get error code when IS_ERR is false
Signed-off-by: Cai Huoqing
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index e48acdd
On Mon, 19 Jul 2021 at 04:59, Dave Airlie wrote:
>
> On Thu, 15 Jul 2021 at 18:11, Thomas Zimmermann wrote:
> >
> > Hi
> >
> > Am 13.07.21 um 18:59 schrieb Javier Martinez Canillas:
> > > On 6/25/21 3:09 PM, Javier Martinez Canillas wrote:
> > >> The simplefb and simpledrm drivers match against a
refcount_t type and corresponding API can protect refcounters from
accidental underflow and overflow and further use-after-free situations.
Signed-off-by: Xiyu Yang
Signed-off-by: Xin Tan
---
drivers/video/fbdev/core/fbmem.c | 6 +++---
include/linux/fb.h | 3 ++-
2 files changed,
refcount_t type and corresponding API can protect refcounters from
accidental underflow and overflow and further use-after-free situations.
Signed-off-by: Xiyu Yang
Signed-off-by: Xin Tan
---
drivers/gpu/drm/exynos/exynos_drm_g2d.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(
Yongqiang Niu (1):
drm/mediatek: add dither 6 setting
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
1 file changed, 2 insertions(+)
mode change 100644 => 100755 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
--
1.8.1.1.dirty
in the first version dither patch
https://patchwork.kernel.org/project/linux-mediatek/patch/1553667561-25447-13-git-send-email-yongqiang@mediatek.com/
dither 6 setting is included in that patch
bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
bit 2 is rdither_en(Enables running ord
On 7/18/21 4:56 AM, Qiang Yu wrote:
> On Sat, Jul 17, 2021 at 10:52 PM Marek Vasut wrote:
>>
>> On 7/17/21 4:21 PM, Qiang Yu wrote:
>>> On Sat, Jul 17, 2021 at 9:08 PM Marek Vasut wrote:
On 7/17/21 2:34 PM, Qiang Yu wrote:
> On Sat, Jul 17, 2021 at 2:20 AM Marek Vasut wrote:
>>>
On Sun, Jul 18, 2021 at 9:43 PM Andy Shevchenko
wrote:
> On Sun, Jul 18, 2021 at 4:43 PM Len Baker wrote:
> > strcpy() performs no bounds checking on the destination buffer. This
> > could result in linear overflows beyond the end of the buffer, leading
> > to all kinds of misbehaviors. The safe
Hi Randy,
On Mon, Jul 19, 2021 at 4:34 AM Randy Dunlap wrote:
> When DRM_SIMPLEDRM=m, all of FB_CFB_{FILLRECT,COPYAREA,IMAGEBLIT} are =m,
Why does that happen?
FB_SIMPLE does select FB_CFB_*, so all of the latter should be builtin?
Do I need my morning coffee? I'm about to fetch it...
> causing
On Fri, 16 Jul 2021 at 20:21, Matthew Auld
wrote:
>
> On Fri, 16 Jul 2021 at 15:14, Jason Ekstrand wrote:
> >
> > Instead of hand-rolling the same three calls in each function, pull them
> > into an i915_gem_object_create_user helper. Apart from re-ordering of
> > the placements array ENOMEM che
On Fri, 16 Jul 2021 at 15:14, Jason Ekstrand wrote:
>
> Since we don't allow changing the set of regions after creation, we can
> make ext_set_placements() build up the region set directly in the
> create_ext and assign it to the object later. This is similar to what
> we did for contexts with th
in the first version dither patch
https://patchwork.kernel.org/project/linux-mediatek/patch/1553667561-25447-13-git-send-email-yongqiang@mediatek.com/
dither 6 setting is included in that patch
bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
bit 2 is rdither_en(Enables running ord
Change since v1:
- -x
Yongqiang Niu (1):
drm/mediatek: add dither 6 setting
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
1 file changed, 2 insertions(+)
--
1.8.1.1.dirty
On Sat, Jul 17, 2021 at 12:48 AM Jason Ekstrand wrote:
> In i915_exit(), we check i915_pci_driver.driver.owner to detect if
> i915_init exited early and don't tear anything down. However, we didn't
> have proper tear-down paths for early exits in i915_init().
>
> Most of the time, you would never
Hi Vinod,
I love your patch! Perhaps something to improve:
[auto build test WARNING on v5.13]
[also build test WARNING on next-20210716]
[cannot apply to linus/master v5.14-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '-
On Sat, Jul 17, 2021 at 12:48 AM Jason Ekstrand wrote:
>
> We should tear down in the opposite order we set up.
>
> Signed-off-by: Jason Ekstrand
> Fixes: 537f9c84a427 ("drm/i915/pmu: Fix CPU hotplug with multiple GPUs")
> Cc: Daniel Vetter
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/
Jason is trying to sort out the unwinding in i915_init and i915_exit,
while reviewing those patches I noticed that we also have the
nomodeset handling now in the middle of things.
Pull that out for simplisity in unwinding - if you run selftest with
nomodeset you get nothing, *shrug*.
Cc: Jason Ek
Am 17.07.21 um 22:29 schrieb Rob Clark:
From: Rob Clark
Conversion to gpu_scheduler, and bonus removal of
drm_gem_object_put_locked()
Oh yes please!
If I'm not completely mistaken that was the last puzzle piece missing to
unify TTMs and GEMs refcount of objects.
Only problem is that I onl
Hi Vinod,
I love your patch! Perhaps something to improve:
[auto build test WARNING on v5.13]
[cannot apply to linus/master v5.14-rc1 next-20210716]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https
Noticed PMU being mentioned..
On 16/07/2021 23:47, Jason Ekstrand wrote:
We should tear down in the opposite order we set up.
Signed-off-by: Jason Ekstrand
Fixes: 537f9c84a427 ("drm/i915/pmu: Fix CPU hotplug with multiple GPUs")
1)
You can use 'dim fixes ' to get you the correct cc list wh
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - 2734d6c1b1a089fb593ef6a23d4b70903526fe0c
The changes were as follows (shortlog from
b10733527bfd864605c33ab2e9a886eec317ec39):
Lionel Landwerlin (1):
drm: fix drm_m
On 16/07/2021 16:23, Jason Ekstrand wrote:
On Fri, Jul 16, 2021 at 9:52 AM Tvrtko Ursulin
wrote:
On 15/07/2021 11:15, Matthew Auld wrote:
The CPU domain should be static for discrete, and on DG1 we don't need
any flushing since everything is already coherent, so really all this
does is an
On 16/07/2021 21:16, Matthew Brost wrote:
As discussed in [1], [2] we are enabling GuC submission support in the
i915. This is a subset of the patches in step 5 described in [1],
basically it is absolute to enable CI with GuC submission on gen11+
platforms.
This series itself will likely be br
On 19/07/2021 09:35, Daniel Vetter wrote:
Jason is trying to sort out the unwinding in i915_init and i915_exit,
while reviewing those patches I noticed that we also have the
nomodeset handling now in the middle of things.
Pull that out for simplisity in unwinding - if you run selftest with
nom
On Fri, 16 Jul 2021 at 16:23, Jason Ekstrand wrote:
>
> On Fri, Jul 16, 2021 at 9:52 AM Tvrtko Ursulin
> wrote:
> >
> >
> > On 15/07/2021 11:15, Matthew Auld wrote:
> > > The CPU domain should be static for discrete, and on DG1 we don't need
> > > any flushing since everything is already coherent
On Thu, Jul 15, 2021 at 09:58:08AM +0800, lichenyang wrote:
> static int loongson_get_modes(struct drm_connector *connector)
> {
> - int count;
> + struct loongson_connector *lconnector;
> + struct i2c_adapter *adapter;
> + struct edid *edid = NULL;
> + u32 ret;
> +
> + lc
On 19/07/2021 10:09, Tvrtko Ursulin wrote:
On 19/07/2021 09:35, Daniel Vetter wrote:
Jason is trying to sort out the unwinding in i915_init and i915_exit,
while reviewing those patches I noticed that we also have the
nomodeset handling now in the middle of things.
Pull that out for simplisit
On Thu, Jul 15, 2021 at 09:58:07AM +0800, lichenyang wrote:
> From: Chenyang Li
>
> This patch adds an initial DRM driver for the Loongson LS7A1000
> bridge chip(LS7A). The LS7A bridge chip contains two display
> controllers, support dual display output. The maximum support for
> each channel dis
On Thu, Jul 15, 2021 at 09:58:09AM +0800, lichenyang wrote:
> Add LS7A DC vsync interrupt enable and close function, and
> register irq_handler function interface.
> Add vbrank event processing flow.
>
> V2:
> - Remove the useless flags parameter.
Do this in a separate patch. It is an unrelated
Hi all, this patch series implement MIPI rx DPI feature. Please help to review.
This is the v10 version, rebase all patches on the latest code.
Any mistakes, please let me know, I'll fix it in the next series.
Change history:
v10: Fix Rob Herring and Laurent Pinchart comments
- Add more descript
Add 'bus-type' and 'data-lanes' define for port0. Define DP tx lane0,
lane1 swing register array define, and audio enable flag.
The device which cannot pass DP tx PHY CTS caused by long PCB trace or
embedded MUX, adjusting ANX7625 PHY parameters can pass the CTS test. The
adjusting type include Pr
At some time, the original code may return non zero value, force return 0
if operation finished.
Reviewed-by: Robert Foss
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/a
The basic anx7625 driver only support MIPI DSI rx signal input.
This patch add MIPI DPI rx input configuration support, after apply
this patch, the driver can support DSI rx or DPI rx by adding
'bus-type' in DT.
Reviewed-by: Robert Foss
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/
Add audio HDMI codec function support, enable it through device true
flag "analogix,audio-enable".
Reviewed-by: Robert Foss
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 226 ++
drivers/gpu/drm/bridge/analogix/anx7625.h | 5 +
2 files changed, 231 i
Video captured in 1400x1050 resolution (bytesperline aka stride = 1408
bytes) is invalid. Fix it.
Signed-off-by: Krzysztof Halasa
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -585,21 +585,21 @@ static const struct ipu_rgb def_bgra_16 = {
.bits_per_pixel =
5434b85dcf
config: arm64-randconfig-p002-20210719 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 10.3.0
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
Hi Jason-jh,
Thank you for your patch. Please prefix this patch with 'drm/mediatek'
so it is clear what the changes are.
Missatge de jason-jh.lin del dia dl., 19
de jul. 2021 a les 10:24:
>
> The cursor plane should use the current plane state in atomic_async_update
> because it would not be the
Hi Guangming,
Am 19.07.21 um 07:19 schrieb guangming@mediatek.com:
From: Guangming Cao
Dmabuf sysfs stat is used for dmabuf info track.
but these file maybe still use after buffer release/detach,
should clear it before buffer release/detach.
In general looks correct to me, but Hridya alr
On Sun, Jul 18, 2021 at 11:14:15PM +0200, Marek Vasut wrote:
> If the backlight enable GPIO is configured as input, the driver currently
> unconditionally forces the GPIO to output-enable. This can cause backlight
> flicker on boot e.g. in case the GPIO should not be enabled before the PWM
> is con
On Mon, Jul 19, 2021 at 05:57:30PM +0800, Xiaotian Feng wrote:
> On Fri, Jul 16, 2021 at 5:13 AM Greg Kroah-Hartman
> wrote:
> >
> > From: Thomas Zimmermann
> >
> > commit 0ecb51824e838372e01330752503ddf9c0430ef7 upstream.
> >
> > Using struct drm_device.pdev is deprecated. Upcast with to_pci_dev
On Wed, Jul 14 2021, Jason Gunthorpe wrote:
> The patch to move the get/put to core and the patch to convert the samples
> to use vfio_device crossed in a way that this was missed. When both
> patches are together the samples do not need their own get/put.
>
> Fixes: 437e41368c01 ("vfio/mdpy: Con
Keep track for which BO a resource was allocated.
This is necessary to move the LRU handling into the resources.
A bit problematic is i915 since it tries to use the resource
interface without a BO which is illegal from the conceptional
point of view.
v2: Document that this is a weak reference and
This way we finally fix the problem that new resource are
not immediately evict-able after allocation.
That has caused numerous problems including OOM on GDS handling
and not being able to use TTM as general resource manager.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_
Instead of duplicating that at different places add an iterator over all
the resources in a resource manager.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 41 +++
drivers/gpu/drm/ttm/ttm_device.c | 37
drivers/gpu/drm/
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