Hi Sam
Am 07.03.20 um 21:08 schrieb Sam Ravnborg:
> Hi Thomas.
>
> On Fri, Mar 06, 2020 at 04:18:52PM +0100, Thomas Zimmermann wrote:
>> Hi Laurent
>>
>> Am 06.03.20 um 15:22 schrieb Laurent Pinchart:
>>> Hi Thomas,
>>>
>>> Thank you for the patch.
>>>
>>> On Thu, Mar 05, 2020 at 04:59:28PM +0100
Hi Sam
Am 06.03.20 um 22:35 schrieb Sam Ravnborg:
> Hi Thomas.
>
> On Thu, Mar 05, 2020 at 04:59:33PM +0100, Thomas Zimmermann wrote:
>> The gma500 driver uses empty implementations for some of its encoders.
>> Replace the code with the generic simple encoder.
> This parts looks good.
>
>
>> As
Hi
Am 07.03.20 um 10:37 schrieb Chris Wilson:
> Pull the drm_pci_agp_init() underneath the legacy ifdeffry alongside its
> only caller.
My I suggest to change the commit message slightly, because the patch
actually moves drm_pci_agp_destroy(). Something along 'implement
_destroy() before _init()
Hi Gustavo
Am 03.03.20 um 19:20 schrieb Gustavo A. R. Silva:
>
>
> On 2/25/20 08:17, Jani Nikula wrote:
>> On Tue, 25 Feb 2020, "Gustavo A. R. Silva" wrote:
>>> The current codebase makes use of the zero-length array language
>>> extension to the C90 standard, but the preferred mechanism to dec
Hi Sam
Am 06.03.20 um 22:18 schrieb Sam Ravnborg:
> On Thu, Mar 05, 2020 at 04:59:29PM +0100, Thomas Zimmermann wrote:
>> The arc driver uses empty implementations for its encoders. Replace
>> the code with the generic simple encoder.
>
> We should , as a follow-up patch, embed the encoder in
> a
Add assign function in cmdq helper which assign constant value into
internal register by index.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 24 +++-
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
include/linux/soc/mediat
Add documentation for the mt6779 gce.
Add gce header file defined the gce hardware event,
subsys number and constant for mt6779.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: Rob Herring
Reviewed-by: CK Hu
---
.../devicetree/bindings/mailbox/mtk-gce.txt | 8 +-
include/dt-bindings/gce/mt677
add write_s function in cmdq helper functions which
writes value contains in internal register to address
with large dma access support.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 34 +++-
include/linux/mailbox/mtk-cmdq-m
Hi,
Question for robh:
In the old txt situation we add/describe only properties that are used
by the driver/hardware itself. With yaml it also filters things in a
node that are used by other drivers like:
assigned-clocks:
assigned-clock-rates:
power-domains:
Should we add or not?
Kind regards,
This patch support gce on mt6779 platform.
Change since v4:
- do not clear disp event again in drm driver
- symbolize value 1 to jump relative
Change since v3:
- refine code for local variable usage
- use cmdq error code to consistent with current design
- return error directly after send if erro
Add set event function in cmdq helper functions to set specific event.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
include/linux/soc/mediatek/mtk-cmdq.h| 9 +
3
Runtime PM and RGB output need to be released when host1x client
registration fails. The releasing is missed in the code, let's correct it.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/dc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/teg
06.03.2020 03:21, Derek Basehore пишет:
> This adds the plumbing for reading panel rotation from the devicetree
> and sets up adding a panel property for the panel orientation on
> Mediatek SoCs when a rotation is present.
Hello Derek and everyone,
I'm looking at adding display rotation support t
The devm_platform_ioremap_resource() helper replaces few lines of a
boilerplate code with a single line, making code to look cleaner a tad.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/dc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tegra/d
On Mon 02 Mar 04:55 PST 2020, Kiran Gunda wrote:
> diff --git a/drivers/video/backlight/qcom-wled.c
> b/drivers/video/backlight/qcom-wled.c
[..]
> @@ -147,14 +187,39 @@ struct wled {
> u32 max_brightness;
> u32 short_count;
> u32 auto_detect_count;
> + u32 version;
> bo
From: Allen Chen
This adds support for the iTE IT6505.
This device can convert DPI signal to DP output.
Signed-off-by: Jitao Shi
Signed-off-by: Yilun Lin
Signed-off-by: Allen Chen
Signed-off-by: Pi-Hsun Shih
---
drivers/gpu/drm/bridge/Kconfig | 11 +-
drivers/gpu/drm/bridge/Makefile
'dc_stream_release()' may be called twice. Once here, and once below in the
error handling path if we branch to the 'fail' label.
Set 'new_stream' to NULL, once released to avoid the duplicated release
function call.
Signed-off-by: Christophe JAILLET
---
Maybe the 'goto fail' at line 7745 should
Add gce v4 hardware support with different thread number and shift.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/mailbox/mtk-cmdq-mailbox.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
b/drivers/mailbox/mtk-cmdq-mailbox.c
index 4dbee
On Fri, 2020-03-06 at 14:43 +, Steven Price wrote:
> On Fri, Mar 06, 2020 at 02:13:08PM +, Rob Herring wrote:
> > On Thu, Mar 5, 2020 at 8:34 PM Nick Fan wrote:
> > >
> > > Sorry for my late reply.
> > > I have checked internally.
> > > The MT8183_POWER_DOMAIN_MFG_2D is just a legacy name,
Add binding document for the Chrontel CH7033 VGA/DVI/HDMI Encoder.
Signed-off-by: Lubomir Rintel
Reviewed-by: Rob Herring
---
Changes since v1:
- Dual licensed with BSD-2-Clause
- Collected Rob's reviewed-by tag
.../display/bridge/chrontel,ch7033.yaml | 86 +++
1 file ch
Add support for Visionox panel driver.
Signed-off-by: Harigovindan P
---
Changes in v2:
- Dropping redundant space in Kconfig(Sam Ravnborg).
- Changing structure for include files(Sam Ravnborg).
- Removing backlight related code and functions(Sam Ravnborg).
- Remo
Add clear parameter to let client decide if
event should be clear to 0 after GCE receive it.
Signed-off-by: Dennis YC Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +-
drivers/soc/mediatek/mtk-cmdq-helper.c | 5 +++--
include/linux/mailbox/mtk-cmdq-mailbox.h | 3 +--
include/linux/soc
Add a DT binding documentation for IT6505.
Acked-by: Sam Ravnborg
Signed-off-by: Allen Chen
Signed-off-by: Pi-Hsun Shih
---
.../bindings/display/bridge/ite,it6505.yaml| 96 ++
1 file changed, 96 insertions(+)
create mode 100644
Documentation/devicetree/bindings/di
Driver fails to probe with -EPROBE_DEFER if display output isn't ready
yet. This produces a bit noisy error message in KMSG during kernel's boot
up on Tegra20 and Tegra30 because RGB output tends to be probed earlier
than a corresponding voltage regulator driver.
Signed-off-by: Dmitry Osipenko
--
This is a driver for video encoder with VGA and DVI/HDMI outputs.
There is no documentation for the chip -- the operation was guessed from
what was sniffed on a Dell Wyse 3020 ThinOS terminal, the register names
come from the ch7035 driver in Mediatek's GPL code dump.
Only bare minimum is impleme
Chrontel makes encoders for video displays and perhaps other stuff.
Their web site is http://www.chrontel.com/.
Signed-off-by: Lubomir Rintel
Acked-by: Rob Herring
---
Changes since v1:
- Collect Rob's ack
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insert
add write_s function in cmdq helper functions which
writes a constant value to address with large dma
access support.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 26 ++
include/linux/soc/mediatek/mtk-cmdq.h | 14 +++
This fixes the following sparse warning:
drivers/gpu/drm/tiny/ili9486.c:61:16: sparse: sparse: incorrect type in
assignment (different base types)
drivers/gpu/drm/tiny/ili9486.c:61:16: sparse:expected unsigned short
[usertype]
drivers/gpu/drm/tiny/ili9486.c:61:16: sparse:got restricted _
Hi allen,
On Mon, Mar 9, 2020 at 2:32 PM allen wrote:
>
> From: Allen Chen
>
> This adds support for the iTE IT6505.
> This device can convert DPI signal to DP output.
>
> Signed-off-by: Jitao Shi
> Signed-off-by: Yilun Lin
> Signed-off-by: Allen Chen
> Signed-off-by: Pi-Hsun Shih
> ---
> d
Add read_s function in cmdq helper functions which support read value from
register or dma physical address into gce internal register.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++
include/linux/mailbox/mtk-cmdq-mailbox.h |
Some gce hardware shift pc and end address in register to support
large dram addressing.
Implement gce address shift when write or read pc and end register.
And add shift bit in platform definition.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/mailbox/mtk-cmdq-mailbox.c |
Return error code to client if send message fail,
so that client has chance to error handling.
Signed-off-by: Dennis YC Hsieh
Fixes: 576f1b4bc802 ("soc: mediatek: Add Mediatek CMDQ helper")
Reviewed-by: CK Hu
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 4 +++-
1 file changed, 3 insertions(+),
Add jump function so that client can jump to any address which
contains instruction.
Signed-off-by: Dennis YC Hsieh
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 13 +
include/linux/soc/mediatek/mtk-cmdq.h | 11 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/soc/
Add bindings for visionox rm69299 panel.
Signed-off-by: Harigovindan P
---
Changes in v2:
- Removed unwanted properties from description.
- Creating source files without execute permissions(Rob Herring).
Changes in v3:
- Changing txt file into yaml
Changes in v4:
Hi,
chained to this message is a driver for CH7033 along with device tree
binding docs. I'm hoping that it could perhaps make it into 5.7. Please
take a look.
Previous submission [1] contained the exact same patches as this one,
but at that time they relied on Laurent's omapdrm/bridge/devel branc
Export finalize function to client which helps append eoc and jump
command to pkt. Let client decide call finalize or not.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 +
drivers/soc/mediatek/mtk-cmdq-helper.c | 7 ++-
include/linux/soc/
The IT6505 is a high-performance DisplayPort 1.1a transmitter, fully compliant
with DisplayPort 1.1a, HDCP 1.3 specifications. The IT6505 supports color depth
of up to 36 bits (12 bits/color) and ensures robust transmission of
high-quality uncompressed video content, along with uncompressed and
On 2020-03-09 03:17, Bjorn Andersson wrote:
On Mon 02 Mar 04:55 PST 2020, Kiran Gunda wrote:
diff --git a/drivers/video/backlight/qcom-wled.c
b/drivers/video/backlight/qcom-wled.c
[..]
@@ -147,14 +187,39 @@ struct wled {
u32 max_brightness;
u32 short_count;
u32 auto_det
Do success callback in channel when shutdown. For those task not finish,
callback with error code thus client has chance to cleanup or reset.
Signed-off-by: Dennis YC Hsieh
Reviewed-by: CK Hu
---
drivers/mailbox/mtk-cmdq-mailbox.c | 38 ++
1 file changed, 38 insertio
Hello,
syzbot found the following crash on:
HEAD commit:63623fd4 Merge tag 'for-linus' of git://git.kernel.org/pub..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=177bf331e0
kernel config: https://syzkaller.appspot.com/x/.config?x=9833e26bab355358
das
Adding support for visionox rm69299 panel driver and adding bindings for the
same panel.
Harigovindan P (2):
dt-bindings: display: add visionox rm69299 panel variant
drm/panel: add support for rm69299 visionox panel driver
.../display/panel/visionox,rm69299.yaml | 85 +
drivers/g
Von: kernel-janitors-ow...@vger.kernel.org
im Auftrag von Christophe JAILLET
Gesendet: Sonntag, 8. März 2020 10:26
An: harry.wentl...@amd.com; sunpeng...@amd.com; alexander.deuc...@amd.com;
christian.koe...@amd.com; david1.z...@amd.com; airl...@linux.
On Fri, 06 Mar 2020, Manasi Navare wrote:
> On Fri, Mar 06, 2020 at 12:30:46PM +0200, Jani Nikula wrote:
>> On Thu, 05 Mar 2020, Manasi Navare wrote:
>> > This patch adds defines for the detailed monitor
>> > range flags as per the EDID specification.
>> >
>> > Suggested-by: Ville Syrjälä
>> > C
On Fri, 6 Mar 2020 18:51:22 +
Emil Velikov wrote:
> On Fri, 6 Mar 2020 at 14:00, Pekka Paalanen wrote:
> >
> > On Wed, 19 Feb 2020 13:27:28 +
> > Emil Velikov wrote:
> >
> > > From: Emil Velikov
> > >
> >
> > ...
> >
> > > +/*
> > > + * In the olden days the SET/DROP_MASTER ioctl
On Wed, Mar 04, 2020 at 05:32:11PM -0800, Gurchetan Singh wrote:
> A resource will be a shmem based resource or a (planned)
> vram based resource, so it makes sense to factor out common fields
> (resource handle, dumb).
>
> v2: move mapped field to shmem object
Pushed to drm-misc-next.
thanks,
Hello Marek,
Thank for your patch. Pm_runtime_put_sync is also done into function
ltdc_crtc_mode_fixup.
To avoid several call of Pm_runtime_put_sync, it could be better to check
pm_runtime activity:
+ int ret;
DRM_DEBUG_DRIVER("\n");
+ if (!pm_runtime_active(ddev->dev)) {
Hi Laurent,
On Tue, 25 Feb 2020 10:13:54 +0100
Boris Brezillon wrote:
> > > diff --git
> > > a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
> > > b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
> > > index 8f373029f5d2..7c4e42f4de61 100644
> > > --- a/Doc
Hi Marek,
On Thu, 2019-11-14 at 14:17 +0100, Marek Vasut wrote:
> The bus_flags and bus_format handling logic does not seem to cover
> all potential usecases. Specifically, this seems to fail with an
> "edt,etm0700g0edh6" display attached to an 24bit display interface,
> with interface-pix-fmt = "
Store the IOMMU mapping created by the device core of each Exynos DRM
sub-device and restore it when the Exynos DRM driver is unbound. This
fixes IOMMU initialization failure for the second time when a deferred
probe is triggered from the bind() callback of master's compound DRM
driver. This also f
Pierre-eric, just a gentle ping on this? Could I get a tested-by?
Ray can you ack or even review this?
Thanks,
Christian.
Am 06.03.20 um 13:41 schrieb Christian König:
The assert sometimes incorrectly triggers when pinned BOs are destroyed.
Signed-off-by: Christian König
---
drivers/gpu/dr
[ 1715.899800] BUG: KCSAN: data-race in drm_gem_handle_create_tail /
drm_gem_object_handle_put_unlocked
[ 1715.899838]
[ 1715.899861] write to 0x8881830f3604 of 4 bytes by task 7834 on cpu 1:
[ 1715.899896] drm_gem_handle_create_tail+0x62/0x250
[ 1715.899927] drm_gem_open_ioctl+0xc1/0x160
[
Mark up the potential racy read in drm_mm_initialized(), as we want a
cheap and cheerful check:
[ 121.098731] BUG: KCSAN: data-race in _i915_gem_object_create_stolen [i915] /
rm_hole
[ 121.098766]
[ 121.098789] write (marked) to 0x8881f01ed330 of 8 bytes by task 3568 on
cpu 3:
[ 121.0988
On Thu, Mar 05, 2020 at 08:41:43PM +0100, H. Nikolaus Schaller wrote:
>
> > Am 03.03.2020 um 16:49 schrieb H. Nikolaus Schaller :
> >
> > Hi,
> >
> >> Am 03.03.2020 um 16:03 schrieb Ville Syrjälä
> >> :
> >>
> >>> I haven't looked into the driver code, but would it be
> >>> possible to specify
On Mon, 9 Mar 2020 at 08:38, Pekka Paalanen wrote:
>
> On Fri, 6 Mar 2020 18:51:22 +
> Emil Velikov wrote:
>
> > On Fri, 6 Mar 2020 at 14:00, Pekka Paalanen wrote:
> > >
> > > On Wed, 19 Feb 2020 13:27:28 +
> > > Emil Velikov wrote:
> > >
> > > > From: Emil Velikov
> > > >
> > >
> > >
On Fri, Mar 06, 2020 at 09:02:57AM +0100, Marco Felsch wrote:
> On 20-03-03 16:52, Ville Syrjälä wrote:
> > On Tue, Mar 03, 2020 at 08:33:20AM +0100, Marco Felsch wrote:
> > > Hi Ville,
> > >
> > > On 20-03-02 22:34, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > The currently
From: Ville Syrjälä
The dotclock is three orders of magnitude out. Fix it.
v2: Just set it to 20MHz (Linus)
Cc: Linus Walleij
Cc: Sam Ravnborg
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/panel/panel-novatek-nt35510.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
From: Ville Syrjälä
The listed dotclocks are two orders of mangnitude out.
Fix them.
v2: Just divide everything by 100 (Linus)
Cc: Linus Walleij
Cc: Thierry Reding
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/panel/panel-ilitek-ili9322.c | 14 +++---
1 file changed, 7 insertions
On 09/03/2020 13:41, Lukasz Luba wrote:
> Register devfreq cooling device and attempt to register Energy Model. This
> will add the devfreq device to the Energy Model framework. It will create
> a dedicated and unified data structures used i.e. in thermal framework.
> The last NULL parameter indica
On Mon, Mar 09, 2020 at 07:18:04AM -0400, Brian Masney wrote:
> The sram property was incorrectly added to the GMU binding when it
> really belongs with the GPU binding instead. Let's go ahead and
> move it.
>
> While changes are being made here, let's update the sram property
> description to men
When CONFIG_INIT_ON_ALLOC_DEFAULT_ON the GMU memory allocator runs afoul of
cache coherency issues because it is mapped as write-combine without clearing
the cache after it was zeroed.
Rather than duplicate the hacky workaround we use in the GEM allocator for the
same reason it turns out that we d
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Acked-by: Sam Ravnborg
Reviewed-by: Rob Herring
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 65 ---
.../devicetree/bindings/display/msm/gmu.yaml | 12
The GMU has very few memory allocations and uses a flat memory space so
there is no good reason to go out of our way to bypass the DMA APIs which
were basically designed for this exact scenario.
v4: Use dma_alloc_wc()
v3: Set the dma mask correctly and use dma_addr_t for the iova type
v2: Pass for
On Mon, Mar 9, 2020 at 2:36 PM Ville Syrjala
wrote:
> From: Ville Syrjälä
>
> The dotclock is three orders of magnitude out. Fix it.
>
> v2: Just set it to 20MHz (Linus)
>
> Cc: Linus Walleij
> Cc: Sam Ravnborg
> Signed-off-by: Ville Syrjälä
Reviewed-by: Linus Walleij
Yours,
Linus Walleij
On Mon, Mar 9, 2020 at 2:38 PM Ville Syrjala
wrote:
> From: Ville Syrjälä
>
> The listed dotclocks are two orders of mangnitude out.
> Fix them.
>
> v2: Just divide everything by 100 (Linus)
>
> Cc: Linus Walleij
> Cc: Thierry Reding
> Signed-off-by: Ville Syrjälä
Reviewed-by: Linus Walleij
Am 05.03.20 um 16:54 schrieb Jason Ekstrand:
On Thu, Mar 5, 2020 at 7:06 AM Christian König wrote:
[SNIP]
Well as far as I can see this won't work because it would break the
semantics of the timeline sync.
I'm not 100% convinced it has to. We already have support for the
seqno regressing and
Hi,
On Mon, Mar 09, 2020 at 10:53:04AM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v2:
> - Dropping redundant space in Kconfig(Sam Ravnborg).
> - Changing structure for include files(Sam Ravnborg).
>
Hi Phong.
On Mon, Mar 09, 2020 at 04:36:52PM +0100, Phong LE wrote:
> Add ITE Tech Inc. prefix "ite" in vendor-prefixes
Maybe add to the changelog that their domain is http://www.ite.com.tw/?
>
> Signed-off-by: Phong LE
Acked-by: Sam Ravnborg
> ---
> Documentation/devicetree/bindings/vendor-
Hi Phong.
On Mon, Mar 09, 2020 at 04:36:53PM +0100, Phong LE wrote:
> Add the ITE bridge HDMI it66121 bindings.
Good to see that you used DT Schema.
>
> Signed-off-by: Phong LE
> ---
> .../bindings/display/bridge/ite,it66121.yaml | 95 +++
> 1 file changed, 95 insertions(+)
>
On Fri, 6 Mar 2020 17:06:00 +0530, Krishna Manikandan wrote:
> MSM Mobile Display Subsytem(MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema
> for the device tree bindings for the same.
>
> Signed-off-by: Krishna Manikandan
> ---
> .../bindings/display/msm/dp
On Mon, 9 Mar 2020 at 13:13, Emil Velikov wrote:
> > OTOH, if applications exist that rely on drop-master failing in this
> > specific case, making drop-master succeed would break them. That might
> > include a buggy set-master path that was written, but does not actually
> > work because it was
The OrtusTech COM43H4M85ULC is a DPI panel, set the connector type
accordingly.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index e14c14ac
The TFP410 supports configuration through I2C (in which case the
corresponding DT node is a child of an I2C controller) or through pins
(in which case the DT node creates a platform device). When I2C access
to the device is available, read and validate the device ID at probe
time to ensure that the
Hi Phong.
On Mon, Mar 09, 2020 at 04:36:54PM +0100, Phong LE wrote:
> This commit is a simple driver for bridge HMDI it66121.
> The input format is RBG and there is no color conversion.
> Audio, HDCP and CEC are not supported yet.
Nice driver. Some few comments below.
Patch fails to apply/build
Hi Laurent.
On Mon, Mar 09, 2020 at 08:42:10PM +0200, Laurent Pinchart wrote:
> The OrtusTech COM43H4M85ULC is a DPI panel, set the connector type
> accordingly.
>
> Signed-off-by: Laurent Pinchart
Reviewed-by: Sam Ravnborg
I assume you will apply to drm-misc-next - OK?
Sam
> ---
>
Hi Sam,
On Mon, Mar 09, 2020 at 08:00:47PM +0100, Sam Ravnborg wrote:
> On Mon, Mar 09, 2020 at 08:42:10PM +0200, Laurent Pinchart wrote:
> > The OrtusTech COM43H4M85ULC is a DPI panel, set the connector type
> > accordingly.
> >
> > Signed-off-by: Laurent Pinchart
>
> Reviewed-by: Sam Ravnborg
Hi Philipp,
(CC'ing Boris)
On Mon, Mar 09, 2020 at 11:50:59AM +0100, Philipp Zabel wrote:
> On Thu, 2019-11-14 at 14:17 +0100, Marek Vasut wrote:
> > The bus_flags and bus_format handling logic does not seem to cover
> > all potential usecases. Specifically, this seems to fail with an
> > "edt,et
On Mon, Mar 09, 2020 at 09:01:27PM +0200, Laurent Pinchart wrote:
> Hi Sam,
>
> On Mon, Mar 09, 2020 at 08:00:47PM +0100, Sam Ravnborg wrote:
> > On Mon, Mar 09, 2020 at 08:42:10PM +0200, Laurent Pinchart wrote:
> > > The OrtusTech COM43H4M85ULC is a DPI panel, set the connector type
> > > accordi
On Mon, Mar 9, 2020 at 4:18 AM Brian Masney wrote:
>
> The sram property was incorrectly added to the GMU binding when it
> really belongs with the GPU binding instead. Let's go ahead and
> move it.
>
> While changes are being made here, let's update the sram property
> description to mention that
The LCDC_CTRL register is located at address 0x. Some of the
accesses to the register simply use the mxsfb->base address. Reference
the LCDC_CTRL register explicitly instead to clarify the code.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 8
1 file chang
The mxsfb driver is only used by OF platforms. Drop non-OF support.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
b/drivers/gpu/drm/mxsfb/mxsf
The vblank event is armed in the plane .atomic_update(). This works fine
as we have a single plane, but will break as soon as multiple planes are
supported (not to mention it's logically the wrong place to perform the
operation). Move it to CRTC .atomic_flush().
Signed-off-by: Laurent Pinchart
--
Commit 8e93f1028d74 ("drm/mxsfb: Use drm_fbdev_generic_setup()")
replaced fbdev handling with drm_fbdev_generic_setup() but left
inclusion of the drm/drm_fb_cma_helper.h header. Remove it.
Fixes: 8e93f1028d74 ("drm/mxsfb: Use drm_fbdev_generic_setup()")
Signed-off-by: Laurent Pinchart
---
driver
The LCDIF present in the i.MX6SX has extra features compared to
the i.MX28. It has however lost its IP version register, so no official
version number is known. Bump the version to MXSFB_V6 following the i.MX
version, in preparation for support for the additional features.
Signed-off-by: Laurent P
Replace the manual connector implementation based on drm_panel with the
drm_panel_bridge helper. This simplifies the mxsfb driver by removing
connector-related code, and standardizing all pipeline control
operations on bridges.
A hack is needed to get hold of the connector, as that's our only sour
The driver attempts agressive power management by enabling and disabling
the AXI clock around register accesses. This results in attempts to
enable and disable the clock in the IRQ handler, which is a no-go as
preparing or unpreparing the clock may sleep.
On the other hand, the driver enables the
The debug0 and ipversion fields of the mxsfb_devdata structure are
unused. Remove them.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 4
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 2 --
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
b/dri
Replace the convoluted way to set the format and bus width through
difficult to read macros with more explicit ones. Also remove the
outdated comment related to the limitations on bus width setting as it
doesn't apply anymore (the bus width can be specified through the
display_info bus format).
Si
The mxsfb_crtc.c file doesn't handle just the CRTC, but also the other
KMS objects. Rename it accordingly.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/Makefile | 2 +-
drivers/gpu/drm/mxsfb/{mxsfb_crtc.c => mxsfb_kms.c} | 0
2 files changed, 1 insertion(+), 1 d
Enable vblank handling when the CRTC is turned on and disable it when it
is turned off. This requires moving vblank init after the KMS pipeline
initialisation, otherwise drm_vblank_init() gets called with 0 CRTCs.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 15 +++
A fair number of includes are not needed. Drop them, and add a couple of
required includes that were included indirectly.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 +++-
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 5 -
2 files changed, 3 insertions(+), 14
mxsfb_regs.h defines macros related to register bits. Some of them are
not used and don't clearly map to any particular register, so their
purpose isn't known. Remove them.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 8
1 file changed, 8 deletions(-)
diff -
The mxsfb_set_pixel_fmt() and mxsfb_set_bus_fmt() functions both deal
with format configuration, are always called in a row from
mxsfb_crtc_mode_set_nofb(), and set fields from the LCDC_CTRL register.
This requires a read-modify-update cycle in mxsfb_set_bus_fmt(). Make
this more efficient by mergi
The mxsfb_reset_block() function isn't special, pass it the
mxsfb_drm_private pointer instead of a pointer to the base address.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/
Using BIT() is preferred over manual shifts as it's more readable,
handles the 1 << 31 case properly, and avoids other mistakes as shown by
the DEBUG0_HSYNC and DEBUG0_VSYNC bits (that are currently unused). Use
it.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_regs.h | 56
The DRM simple display pipeline helper only supports a single plane. In
order to prepare for support of the alpha plane on i.MX6SX and i.MX7,
move away from the helper. No new feature is added.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 184 +
The mxsfb_set_pixel_fmt() function returns an error when the selected
pixel format is unsupported. This can never happen, as such errors are
caught by the DRM core. Remove the error check.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 11 ++-
1 file changed, 2 i
Extend the Kconfig option description by listing the i.MX7 SoCs, as they
are supported by the same driver.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mxsfb/Kconfig b/drivers/gpu/drm/mxs
The LCDIF in the i.MX6SX and i.MX7 have a second plane called the alpha
plane. Support it.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 3 +
drivers/gpu/drm/mxsfb/mxsfb_drv.h | 16 ++--
drivers/gpu/drm/mxsfb/mxsfb_kms.c | 129 +
driver
mxsfb_crtc.c defines several macros related to register addresses and
bit, which duplicates macros from mxsfb_regs.h. Use the macros from
mxsfb_regs.h instead and remove them.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 14 +-
1 file changed, 5 insertions
Hello,
This patch series adds i.MX7 support to the mxsfb driver. The eLCDIF
instance found in the i.MX7 is backward-compatible with the already
supported LCDC v4, but has extended features amongst which the most
notable one is a second plane.
The first 9 patches (01/21 to 09/21) contain miscellan
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