Re: [PATCH] drm/i915/gvt: fix memory leak in intel_vgpu_ioctl()

On 2018.08.03 08:41:19 +0800, Yi Wang wrote: > The 'sparse' variable may leak when return in function > intel_vgpu_ioctl(), and this patch fixes this. > > Signed-off-by: Yi Wang > Reviewed-by: Jiang Biao > --- > drivers/gpu/drm/i915/gvt/kvmgt.c | 3 +++ > 1 file changed, 3 insertions(+) > > di

Re: [PATCH] drm/vkms: Fix vmap_count increment position

On Wed, Aug 08, 2018 at 06:59:26AM +0300, Haneen Mohammed wrote: > On Wed, Aug 01, 2018 at 12:08:07PM +0300, Haneen Mohammed wrote: > > Move vmap_count out of the conditional statement since it needs > > to be updated for every successful call to vkms_gem_vmap. > > > > Signed-off-by: Haneen Mohamm

Re: [PATCH 2/2] drm/vkms: Compute CRC with Cursor Plane

On Wed, Aug 08, 2018 at 06:53:17AM +0300, Haneen Mohammed wrote: > On Tue, Aug 07, 2018 at 06:33:36PM +0200, Daniel Vetter wrote: > > On Mon, Aug 06, 2018 at 06:58:29AM +0300, Haneen Mohammed wrote: > > > This patch compute CRC for output frame with cursor and primary plane. > > > Blend cursor with

Re: [PATCH v5 10/10] drm/rcar-du/crc: Implement get_crc_sources callback

Hi Mahesh, Thank you for the patch. On Monday, 23 July 2018 13:44:51 EEST Mahesh Kumar wrote: > This patch implements get_crc_sources callback, which returns list of > all the crc sources supported by driver in current platform. > > Changes Since V1: > - move sources list per-crtc > - init sou

Re: [PATCH] drm/doc: clarify how to acquire required vblank event reference

On Tue, Aug 07, 2018 at 10:11:43PM +0200, Stefan Agner wrote: > As a driver write it is not entirely obvious that a reference to > the event e mentioned in the doc can be obtained via > drm_crtc_vblank_get(). Clarify how to obtain the reference. > > Signed-off-by: Stefan Agner > --- > drivers/gp

Re: [PATCH] dma-buf: fix sanity check in dma_buf_export

On Wed, Aug 08, 2018 at 08:25:40AM +0200, Gerd Hoffmann wrote: > Commit 09ea0dfbf972 made map_atomic and map function pointers optional, > but didn't adapt the sanity check in dma_buf_export. Fix that. > > Note that the atomic map interface has been removed altogether meanwhile > (commit f664a526

Re: [PATCH] drm/cirrus: flip default to 32bpp

On Mon, Jul 09, 2018 at 09:39:24AM +0200, Daniel Vetter wrote: > On Fri, Jul 06, 2018 at 02:35:07PM -0400, Adam Jackson wrote: > > On Fri, 2018-07-06 at 11:12 +0200, Gerd Hoffmann wrote: > > > cirrus can handle 1024x768 (and slightly higher) with 24bpp depth. > > > cirrus can handle up to 800x600 w

[PATCH v2] drm/cirrus: flip default from 24bpp to 16bpp

The problem with 24bpp is that it is a rather unusual depth these days, cirrus is pretty much the only relevant device still using that, and it is a endless source of issues. Wayland doesn't support it at all. Bugs in Xorg keep showing up. Typically either 32bpp or 16bpp are used. Using 32bpp w

[PATCH 0/5] drm/ttm,amdgpu: Introduce LRU bulk move functionality

The idea and proposal is originally from Christian, and I continue to work to deliver it. Background: amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of them on the end of LRU list one by one. Thus, that cause so many BOs moved to the end of the LRU, and impact perfor

[PATCH 1/5] drm/ttm: add helper structures for bulk moves on lru list

From: Christian König Add bulk move pos to store the pointer of first and last buffer object. The list in between will be bulk moved on lru list. Signed-off-by: Christian König Signed-off-by: Huang Rui --- include/drm/ttm/ttm_bo_driver.h | 28 1 file changed, 28 i

[PATCH 2/5] drm/ttm: revise ttm_bo_move_to_lru_tail to support bulk moves

From: Christian König When move a BO to the end of LRU, it need remember the BO positions. Make sure all moved bo in between "first" and "last". And they will be bulk moving together. Signed-off-by: Christian König Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 -

[PATCH 3/5] drm/ttm: add bulk move function on LRU

This function allow us to bulk move a group of BOs to the tail of their LRU. The positions of group of BOs are stored on the (first, last) bulk_move_pos structure. Signed-off-by: Christian König Signed-off-by: Huang Rui --- drivers/gpu/drm/ttm/ttm_bo.c | 52 +

[PATCH 4/5] drm/amdgpu: use bulk moves for efficient VM LRU handling

I continue to work for bulk moving that based on the proposal by Christian. Background: amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of them on the end of LRU list one by one. Thus, that cause so many BOs moved to the end of the LRU, and impact performance seriousl

[PATCH 5/5] drm/amdgpu: move PD/PT bos on LRU again

The new bulk moving functionality is ready, the overhead of moving PD/PT bos to LRU is fixed. So move them on LRU again. Signed-off-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Re: [PATCH 4/5] drm/amdgpu: use bulk moves for efficient VM LRU handling

Am 08.08.2018 um 11:59 schrieb Huang Rui: I continue to work for bulk moving that based on the proposal by Christian. Background: amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of them on the end of LRU list one by one. Thus, that cause so many BOs moved to the end

Re: [PATCH] drm/scheduler: fix last_scheduled handling

Ping, Nayan any comments on that or can I commit it? This is just a stripped down version of my original last_scheduled improvement patch. Christian. Am 07.08.2018 um 14:54 schrieb Christian König: Make sure we access last_scheduled only after checking that there are no more jobs on the enti

Re: [PATCH] drm/scheduler: fix last_scheduled handling

Hi Christian, On Wed, Aug 8, 2018 at 4:20 PM Christian König < ckoenig.leichtzumer...@gmail.com> wrote: > Ping, Nayan any comments on that or can I commit it? > > This is just a stripped down version of my original last_scheduled > improvement patch. > > I had missed the mail yesterday. I was jus

Re: [PATCH] drm/scheduler: fix last_scheduled handling

Am 08.08.2018 um 12:55 schrieb Nayan Deshmukh: Hi Christian, On Wed, Aug 8, 2018 at 4:20 PM Christian König > wrote: Ping, Nayan any comments on that or can I commit it? This is just a stripped down version of my original last_scheduled im

Re: [PATCH] drm/scheduler: fix last_scheduled handling

On Wed, Aug 8, 2018 at 4:36 PM Christian König < ckoenig.leichtzumer...@gmail.com> wrote: > Am 08.08.2018 um 12:55 schrieb Nayan Deshmukh: > > Hi Christian, > > On Wed, Aug 8, 2018 at 4:20 PM Christian König < > ckoenig.leichtzumer...@gmail.com> wrote: > >> Ping, Nayan any comments on that or can

[PATCH v3] drm/cirrus: flip default from 24bpp to 16bpp

The problem with 24bpp is that it is a rather unusual depth these days, cirrus is pretty much the only relevant device still using that, and it is a endless source of issues. Wayland doesn't support it at all. Bugs in Xorg keep showing up. Typically either 32bpp or 16bpp are used. Using 32bpp w

[PATCH] drm/scheduler: change entities rq even earlier

Looks like for correct debugging we need to know the scheduler even earlier. So move picking a rq for an entity into job creation. Signed-off-by: Christian König --- drivers/gpu/drm/scheduler/gpu_scheduler.c | 50 --- drivers/gpu/drm/scheduler/sched_fence.c | 2 +-

Re: [PATCH] drm/scheduler: fix last_scheduled handling

On Wed, Aug 8, 2018 at 4:42 PM Nayan Deshmukh wrote: > > > On Wed, Aug 8, 2018 at 4:36 PM Christian König < > ckoenig.leichtzumer...@gmail.com> wrote: > >> Am 08.08.2018 um 12:55 schrieb Nayan Deshmukh: >> >> Hi Christian, >> >> On Wed, Aug 8, 2018 at 4:20 PM Christian König < >> ckoenig.leichtzu

Re: drm/imx: ipu-v3 plane offset and IPU id fixes

On Mon, 2018-08-06 at 12:51 +0200, Philipp Zabel wrote: > Hi Dave, > > please consider merging these two fixes for code used by imx-media. > Setting the IPU id to 0 if there are no OF aliases set fixes probing > on i.MX51 and i.MX53, and calculating odd YUV offsets correctly will > help fixing int

Re: [PATCH] drm/scheduler: change entities rq even earlier

On Wed, Aug 8, 2018 at 4:44 PM Christian König < ckoenig.leichtzumer...@gmail.com> wrote: > Looks like for correct debugging we need to know the scheduler even > earlier. So move picking a rq for an entity into job creation. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/scheduler/gp

Re: [PATCH v3 4/4] drm/mxsfb: Switch to drm_atomic_helper_commit_tail_rpm

On 08.08.2018 10:00, Leonard Crestez wrote: > On Tue, 2018-08-07 at 21:01 +0200, Stefan Agner wrote: >> On 06.08.2018 21:31, Leonard Crestez wrote: >> > The lcdif block is only powered on when display is active so plane >> > updates when not enabled are not valid. Writing to an unpowered IP block >

Re: [PATCH v3] drm/cirrus: flip default from 24bpp to 16bpp

On Wed, 2018-08-08 at 13:13 +0200, Gerd Hoffmann wrote: > The problem with 24bpp is that it is a rather unusual depth these days, Nit: s/depth/bpp/ here. Depth 24 is very common, it's packing that into three bytes per pixel that's unusual. > cirrus is pretty much the only relevant device still us

[Bug 107518] polaris powerplay init fails: There must be 1 or more PCIE levels defined in PPTable

https://bugs.freedesktop.org/show_bug.cgi?id=107518 --- Comment #5 from Alex Deucher --- (In reply to Shawn Anastasio from comment #4) > Does the driver do the reset on a kexec reboot? If so, it seems insufficient > to mitigate this issue. Probably not. I'm not that familiar with kexec unfortun

[PATCH V6 10/10] drm/rcar-du/crc: Implement get_crc_sources callback

This patch implements get_crc_sources callback, which returns list of all the crc sources supported by driver in current platform. Changes Since V1: - move sources list per-crtc - init sources-list only for gen3 Changes Since V2: - Adopt to driver style - Address other review comments from Lau

[Bug 107296] WARNING: CPU: 0 PID: 370 at drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:1355 dcn_bw_update_from_pplib+0x16b/0x280 [amdgpu]

https://bugs.freedesktop.org/show_bug.cgi?id=107296 Paul Menzel changed: What|Removed |Added CC||pmenzel+bugs.freedesktop@mo

Re: [PATCH v1 2/5] pardata: new bus for parallel data access

Den 08.08.2018 10.24, skrev Sam Ravnborg: Hi Noralf. On Tue, Aug 07, 2018 at 06:40:29PM +0200, Noralf Trønnes wrote: Hi Sam, Den 02.08.2018 21.45, skrev Sam Ravnborg: The pardata supports implement a simple bus for devices that are connected using a parallel bus driven by GPIOs. The is often

Re: [PATCH v1 5/5] tinydrm: add winstar wg160160 driver

Den 08.08.2018 10.32, skrev Sam Ravnborg: Hi Noralf. On Tue, Aug 07, 2018 at 07:35:30PM +0200, Noralf Trønnes wrote: Den 02.08.2018 21.45, skrev Sam Ravnborg: Add driver for the winstar wg160160 display. The driver utilises pardata-dbi that again utilise the pardata subsystem. Signed-off-by:

[PATCH][next] drm/msm: a6xx: fix spelling mistake: "initalization" -> "initialization"

From: Colin Ian King Trivial fix to spelling mistake in dev_err message and comment Signed-off-by: Colin Ian King --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adren

Re: [PATCH v3 09/10] drm/vc4: Use __drm_atomic_helper_plane_reset instead of copying the logic

Hi Eric, On Mon, Aug 06, 2018 at 12:58:20PM -0700, Eric Anholt wrote: > Alexandru Gheorghe writes: > > > A new helper function(__drm_atomic_helper_plane_reset) has been added > > for linking a plane with its state and resetting the core > > properties(alpha, rotation, etc.) to their default value

Re: [PATCH v4 2/5] drm/mxsfb: Fix initial corrupt frame when activating display

On 08.08.2018 18:08, Leonard Crestez wrote: > LCDIF will repeatedly display data from CUR_BUF and set CUR_BUF to > NEXT_BUF when done. Since we are only ever writing to NEXT_BUF the > display will show an initial corrupt frame. > > Fix by writing the FB paddr to both CUR_BUF and NEXT_BUF when > ac

Re: [PATCH v4 1/5] drm/mxsfb: Move axi clk enable/disable to crtc enable/disable

On 08.08.2018 18:08, Leonard Crestez wrote: > The main axi clk is disabled at the end of mxsfb_crtc_mode_set_nofb and > immediately reenabled in mxsfb_enable_controller. > > Avoid this by moving the handling of axi clk one level up to > mxsfb_crtc_enable. Do the same for mxsfb_crtc_disable for sim

Re: [PATCH v2 4/7] drm/i2c: tda998x: convert to bridge driver

On Mon, Jul 30, 2018 at 05:42:21PM +0100, Russell King wrote: > Convert tda998x to a bridge driver with built-in encoder support for > compatibility with existing component drivers. > > Signed-off-by: Russell King Hi Russell, Thanks for doing the bridge conversion, it certainly seems a better fi

[Bug 103199] [CI] igt@drv_missed_irq - fail - Failed assertion: missed_rings == expect_rings

https://bugs.freedesktop.org/show_bug.cgi?id=103199 --- Comment #4 from Chris Wilson --- (In reply to Martin Peres from comment #3) > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_93/fi-icl-u/ > igt@drv_missed_irq.html > > (drv_missed_irq:1510) CRITICAL: Test assertion failure function > __rea

[PATCH] drm/panel: sn65dsi86: Implement AUX channel

This was hand-rolled in the first version, and will surely be useful as we expand the driver to support more varied use cases. Cc: Sandeep Panda Signed-off-by: Sean Paul --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 107 -- 1 file changed, 100 insertions(+), 7 deletions(-)

[Bug 107001] hard system freeze with mesa 18.1.1 and 18.1.2 on AMD RX 580

https://bugs.freedesktop.org/show_bug.cgi?id=107001 cla...@mathr.co.uk changed: What|Removed |Added Resolution|FIXED |--- Status|RESOLVED

[PATCH] drm/msm/a6xx: Renmae gmu phandle to qcom,gmu

From the review for the DT bindings for the GPU/GMU it was suggested that the phandle for the GMU be 'qcom,gmu' instead of just 'gmu'. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/ad

[PATCH] drm/msm/a6xx: Fix PDC register overlap

The current design greedily takes a big chunk of the PDC register space instead of just the GPU specific sections which conflicts with other drivers and generally makes a mess of things. Furthermore we only need to map the GPU PDC sections just once during init so map the memory inside the functio

[v3 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU

Add DT nodes for the sdm845 GPU/GMU (graphics management unit) and the companion arm-smmu-v2 compatible SMMU. This builds on the following dependencies - https://patchwork.kernel.org/patch/10286369/ - bindings for qcom,level https://patchwork.kernel.org/patch/10281599/ - qcom,smmu-v2 bindings And

[PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

Add the nodes to describe the Adreno GPU and GMU devices. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cd

[PATCH 1/2] dt-bindings: Document qcom,adreno-gmu

Document the device tree bindings for the Adreno GMU device available on Adreno a6xx targets. Reviewed-by: Rob Herring Signed-off-by: Jordan Crouse --- .../devicetree/bindings/display/msm/gmu.txt | 54 +++ .../devicetree/bindings/display/msm/gpu.txt | 10 +++- 2 files change

[Bug 102322] System crashes after "[drm] IP block:gmc_v8_0 is hung!" / [drm] IP block:sdma_v3_0 is hung!

https://bugs.freedesktop.org/show_bug.cgi?id=102322 --- Comment #37 from dwagner --- In the related bug report (https://bugs.freedesktop.org/show_bug.cgi?id=107152) I noticed that this bug can be triggered very reliably and quickly by playing a video with a deliberately lowered frame rate: "mpv

[Bug 107152] GPU fault detected: 146 / VM_CONTEXT1_PROTECTION_FAULT / ring gfx timeout

https://bugs.freedesktop.org/show_bug.cgi?id=107152 --- Comment #12 from dwagner --- Indeed, I found my theory confirmed by many experiments: If I use a script like > #!/bin/bash > cd /sys/class/drm/card0/device > echo manual >power_dpm_force_performance_level > # low > echo 0 >pp_dpm_mclk > ech

[Bug 105251] [Vega10] GPU lockup on boot: VMC page fault

https://bugs.freedesktop.org/show_bug.cgi?id=105251 --- Comment #15 from dergottdergrun...@gmail.com --- I think my issue is related. I get black screen boots roughly every 2/3 times I boot up my computer. This last time, it booted up, kernel panic'd and I could still see the output so I took some

Re: [PATCH] drm/panel: sn65dsi86: Implement AUX channel

On Wed, Aug 8, 2018, 5:53 PM Sean Paul wrote: Just realized I put drm/panel in the subject, should be drm/bridge. Sean This was hand-rolled in the first version, and will surely be useful as > we expand the driver to support more varied use cases. > > Cc: Sandeep Panda > Signed-off-by: Sean Pa

[PATCH v4 02/14] drm/mediatek: add connection from RDMA0 to DSI1

This patch add connection from RDMA0 to DSI1 Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 03e3628b5b0d..310d84

[PATCH v4 10/14] drm/mediatek: add function to return OVL layer number

This patch add function to return OVL layer number For now, MT8173, MT2712, MT2701 OVL all has 4 layer. Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/d

[PATCH v4 03/14] drm/mediatek: add connection from RDMA1 to DSI0

This patch add connection from RDMA1 to DSI0 Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 310d8482d5a0..31189f

[PATCH v4 05/14] drm/mediatek: add memory mode and layer_config for RDMA

This patch add memory mode for RDMA and layer_config for RDMA If use RDMA to read data from memory, it should set memory mode to RDMA Layer config set the data address and pitch to RDMA from plane setting. Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_rdma.

[PATCH v4 08/14] drm/mediatek: add YUYV/UYVY color format support for RDMA

This patch add YUYV/UYVY color format support for RDMA and transform matrix for YUYV/UYVY. Signed-off-by: Stu Hsieh --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 20 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/m

[PATCH v4 01/14] drm/mediatek: add connection from RDMA0 to DPI1

This patch add connection from RDMA0 to DPI1 Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 87e4191c250e..03e362

[PATCH v4 11/14] drm/mediatek: add function to return RDMA layer number

This patch add function to return RDMA layer number RDMA always has one layer. Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek

[PATCH v4 12/14] drm/mediatek: use layer_nr function to get layer number to init plane

This patch use layer_nr function to get layer number to init plane When plane init in crtc create, it use the number of OVL layer to init plane. That's OVL can read 4 memory address. For mt2712 third ddp, it use RDMA to read memory. RDMA can read 1 memory address, so it just init one plane. For

[PATCH v4 14/14] drm/mediatek: fix connection from RDMA2 to DSI1

This patch fix connection from RDMA2 to DSI1 Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 3239f227

[PATCH v4 04/14] drm/mediatek: add connection from RDMA2 to DSI0

This patch add connection from RDMA2 to DSI0 Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 31189fad8d4e..3239f2

[PATCH v4 07/14] drm/mediatek: add the comment about color format setting for OVL

This patch add the comment about color format setting for OVL Signed-off-by: Stu Hsieh --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 978782a77629..0facd

[PATCH v4 06/14] drm/mediatek: add RGB color format support for RDMA

This patch add RGB color format support for RDMA, including RGB565, RGB888, RGBA and ARGB. Signed-off-by: Stu Hsieh --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 46 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c

[PATCH v4 13/14] drm/mediatek: update some variable name from ovl to comp

This patch update some variable name from ovl to comp Because RDMA would be first HW in ddp, the naming ovl should be change to comp. Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 26 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.h

[PATCH v4 00/14] Add RDMA memory mode support for mediatek SOC MT2712

This patch series add RDMA memory mode support for mediatek SOC MT2712. MT2712 has three display data path, including three HW engine, two OVL and one RDMA. The RDMA used in third ddp and it need to be set memory mode, then RDMA could read data from memory and output to panel. Change in v4: - Add

[PATCH v4 09/14] drm/mediatek: add function to get layer number for component

This patch add function to get layer number for component Signed-off-by: Stu Hsieh Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_

Re: [PATCH v4 06/14] drm/mediatek: add RGB color format support for RDMA

Hi, Stu: On Thu, 2018-08-09 at 10:15 +0800, Stu Hsieh wrote: > This patch add RGB color format support for RDMA, > including RGB565, RGB888, RGBA and ARGB. > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 46 > +++

Re: [PATCH v4 07/14] drm/mediatek: add the comment about color format setting for OVL

Hi, Stu: On Thu, 2018-08-09 at 10:15 +0800, Stu Hsieh wrote: > This patch add the comment about color format setting for OVL > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/

Re: [PATCH v4 08/14] drm/mediatek: add YUYV/UYVY color format support for RDMA

Hi, Stu: On Thu, 2018-08-09 at 10:15 +0800, Stu Hsieh wrote: > This patch add YUYV/UYVY color format support for RDMA > and transform matrix for YUYV/UYVY. > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 20 > 1 file cha

Re: [PATCH v4 12/14] drm/mediatek: use layer_nr function to get layer number to init plane

Hi, Stu: On Thu, 2018-08-09 at 10:15 +0800, Stu Hsieh wrote: > This patch use layer_nr function to get layer number to init plane > > When plane init in crtc create, > it use the number of OVL layer to init plane. > That's OVL can read 4 memory address. > > For mt2712 third ddp, it use RDMA to r

[PATCH libdrm] drm/i915/cfl: Add a new CFL PCI ID.

One more CFL ID added to spec. Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl: Add a new CFL PCI ID.") Cc: José Roberto de Souza Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/intel/intel_chipset.h b/intel/i

[PATCH] drm: Add drm.edid_quirk_param module parameter

This parameter allows the set of EDID quirks to be changed at runtime. The syntax is vendor/product/quirks,vendor/product/quirks,... where vendor is the three-letter EDID vendor value, product is the EDID product id which may be prefixed with 0x to for hex instead of decimal values and qu

Re: [PATCH 4/5] drm/amdgpu: use bulk moves for efficient VM LRU handling

On Wed, Aug 08, 2018 at 06:47:49PM +0800, Christian König wrote: > Am 08.08.2018 um 11:59 schrieb Huang Rui: > > I continue to work for bulk moving that based on the proposal by Christian. > > > > Background: > > amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move > > all of

[Bug 104289] [regression][vega10] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout on exiting certain Steam games

https://bugs.freedesktop.org/show_bug.cgi?id=104289 --- Comment #13 from Peter Klotz --- Sorry to post into this already closed bug. Should this issue be fixed in 4.17.12? I am asking because I see sporadic system hangs that start with these messages: Aug 09 08:20:18 thinkpad kernel: [drm:amdg