Hi
I see the following error over and over and as a result a black screen :/
[drm:drm_atomic_helper_commit_cleanup_done] *ERROR* [CRTC:24:crtc-0]
flip_done timed out
I am on latest longterm (4.9.31) with this four imx-drm patches atop:
https://pastebin.com/mCGkw8H8
https://pastebin.com/BmbbZSHA
[ This is a warning about very old code. -dan ]
Hello Zhao Yakui,
The patch d112a8163f83: "gma500/cdv: Add eDP support" from Aug 8,
2012, leads to the following static checker warnings:
drivers/gpu/drm/gma500/intel_bios.c:77 parse_edp()
warn: right shifting more than type allow
On Sat, Jun 10, 2017 at 12:51:02AM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年6月10日 GMT+08:00 上午12:49:15, Maxime Ripard
> 写到:
> >On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
> >> >> @@ -189,6 +211,8 @@ supported.
> >> >> Required properties:
> >> >>- compatible: value must
On Sun, Jun 11, 2017 at 02:43:42PM +0800, icen...@aosc.io wrote:
> 在 2017-06-07 17:38，Maxime Ripard 写道：
> > On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
> > > Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
> > > but has a internal fixed clock divider that d
Hi, Christophe:
Applied to my branch mediatek-drm-next-4.13, thanks.
Regards,
CK
On Fri, 2017-06-09 at 21:27 +0200, Christophe JAILLET wrote:
> If 'devm_kmalloc_array' returns NULL, we should return -ENOMEM as already
> done a few lines above instead of deferencing a NULL pointer a few lines
> b
Hi Eric,
On Wed, 7 Jun 2017 17:13:36 -0700
Eric Anholt wrote:
> This allows mesa to set the tiling format for a BO and have that
> tiling format be respected by mesa on the other side of an
> import/export (and by vc4 scanout in the kernel), without defining a
> protocol to pass the tiling thro
On Wed, 7 Jun 2017 17:13:35 -0700
Eric Anholt wrote:
> The T tiling format is what V3D uses for textures, with no raster
> support at all until later revisions of the hardware (and always at a
> large 3D performance penalty). If we can't scan out V3D's format,
> then we often need to do a relay
https://bugs.freedesktop.org/show_bug.cgi?id=101387
--- Comment #3 from Carlo Caione ---
> Looks like amdgpu_atombios_crtc_powergate_init scribbles over the stack.
Yeah, and while this is causing the panic this is not related to the display
corruption.
The garbage lines we see at boot seem to be
https://bugs.freedesktop.org/show_bug.cgi?id=101224
--- Comment #4 from Nicolai Hähnle ---
Hi Pierre-Marc! Conceptually, glTextureStorage can't take care of the sampler
settings unfortuantely because of the possibility of having separate sampler
objects.
I agree with you though that having a deb
On Sun, Jun 11, 2017 at 02:58:47PM +0800, icen...@aosc.io wrote:
> 在 2017-06-07 17:42，Maxime Ripard 写道：
> > On Mon, Jun 05, 2017 at 12:01:48AM +0800, Icenowy Zheng wrote:
> > > + soc {
> > > + display_clocks: clock@100 {
> > > + compatible = "allwinner,sun8i-a83t-de2-clk
Hi Eric,
On 8 June 2017 at 01:13, Eric Anholt wrote:
> This allows mesa to set the tiling format for a BO and have that
> tiling format be respected by mesa on the other side of an
> import/export (and by vc4 scanout in the kernel), without defining a
> protocol to pass the tiling through userspa
https://bugs.freedesktop.org/show_bug.cgi?id=101387
--- Comment #4 from Michel Dänzer ---
(In reply to Carlo Caione from comment #3)
> > What kind of artifacts in plymouth?
> https://pasteboard.co/hWu18yPj0.jpg
That could be a plymouth bug. I've noticed that it doesn't seem to call
drmModeCrtcSe
https://bugs.freedesktop.org/show_bug.cgi?id=101387
--- Comment #5 from Carlo Caione ---
> That could be a plymouth bug. I've noticed that it doesn't seem to call
> drmModeCrtcSetGamma to make sure the display CLUTs are initialized to
> appropriate values.
Yeah, it could be, I'll investigate the
https://bugs.freedesktop.org/show_bug.cgi?id=101278
nagrigoria...@gmail.com changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution|FI
Hi,
Here's three fixes for omapdrm:
- fix synclost flood on omap3
- fix analog tv-out videomode check
- fix DSI PLL setup
Tony, Aaro, Nikolaus, can you see if these fix the issues you're seeing?
Tomi
Tomi Valkeinen (3):
drm/omap: work-around for omap3 display enable
drm/omap: fix analog t
Hi,
Just spotted this thread.
On 06.06.2017 14:58, Tomi Valkeinen wrote:
> On 06/06/17 15:48, Boris Brezillon wrote:
>
>> Okay. Thanks for the clarification. Can you confirm that this version
>> is correct?
>>
>> dsi@xxx {
>> #address-cells = <1>;
>> #size-cells = <
omapdrm rejects all venc (analog tv-out) videomodes, due to somewhat
strict checking of the values, making tv-out unusable.
We only support two videomodes, one for PAL and one for NTSC, so instead
of trying to check every field in the videomode struct, this patch makes
the driver check only the pi
Seems that on omap3 enabling a crtc without any planes causes a sync
lost flood. This only happens on the first enable, and after that it
works. This looks like an HW issue.
It's unclear why this is happening or how to fix it, but as a quick
work-around, this patch enables i734 errata work-around
7d267f068a8b4944d52e8b0ae4c8fcc1c1c5c5ba ("drm/omap: work-around for
errata i886") changed how the PLL dividers and multipliers are
calculated. While the new way should work fine for all the PLLs, it
breaks omap5 PLLs. The issues seen are rather odd: seemed that the
output clock rate is half of wha
Hi Daniel,
On 9 June 2017 at 07:57, Daniel Axtens wrote:
> Currently, calling drmGetBusid from libdrm on a hibmc VGA
> card returns a string like "0007:a1:00.0".
>
> The busid reported by most cards begins with "pci:". For
> example, on an amd64 system, a VGA card reported
> "pci::00:02.0".
>
https://bugs.freedesktop.org/show_bug.cgi?id=101401
Michel Dänzer changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
2017년 06월 09일 18:23에 Hoegeun Kwon 이(가) 쓴 글:
> The bridge_node is unnecessary between FIMD and DSIM. If don't remove
> error handling, it will not work between FIMD and DSIM. So remove
> error handling.
Please make sure to describe why bridge_node is unnecessary.
For example,
In case of Exynos So
On Sat, Jun 10, 2017 at 10:57:28PM +0800, icen...@aosc.io wrote:
> 在 2017-06-09 22:46，Maxime Ripard 写道：
> > On Thu, Jun 08, 2017 at 01:01:53PM +0800, icen...@aosc.io wrote:
> > > 在 2017-06-07 22:38，Maxime Ripard 写道：
> > > > On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > > > > >I
On Sat, Jun 10, 2017 at 11:16:35PM +0800, icen...@aosc.io wrote:
> 在 2017-06-10 22:57，icen...@aosc.io 写道：
> > 在 2017-06-09 22:46，Maxime Ripard 写道：
> > > On Thu, Jun 08, 2017 at 01:01:53PM +0800, icen...@aosc.io wrote:
> > > > 在 2017-06-07 22:38，Maxime Ripard 写道：
> > > > > On Wed, Jun 07, 2017 at 06
From: Xiaojie Yuan
v2: fix an off by one error and leading white spaces
v3: use thread safe strtok_r(); initialize len before calling getline();
change printf() to drmMsg(); add initial amdgpu.ids
v4: integrate some recent internal changes, including format changes
v5: fix line number for emp
+Gustavo
On Tue, 06 Jun 2017 13:27:09 -0700
Eric Anholt wrote:
> Boris Brezillon writes:
>
> > The VC4 KMS driver is implementing its own ->atomic_commit() but there
> > are a few generic helpers we can use instead of open-coding the logic.
> >
> > Signed-off-by: Boris Brezillon
> > ---
> >
On 06/13/2017 06:25 PM, Inki Dae wrote:
2017년 06월 09일 18:23에 Hoegeun Kwon 이(가) 쓴 글:
The bridge_node is unnecessary between FIMD and DSIM. If don't remove
error handling, it will not work between FIMD and DSIM. So remove
error handling.
Please make sure to describe why bridge_node is unnecessar
Hi Boris,
Sorry lost track of this thread.
On Tue, Jun 06, 2017 at 09:13:00PM +0200, Boris Brezillon wrote:
Hi Brian,
Le Mon, 5 Jun 2017 12:25:50 +0100,
Brian Starkey a écrit :
Hi Boris,
I can't speak for the HW-specific details, but the writeback part
looks pretty good (and familiar ;-)
On Mon, Jun 12, 2017 at 03:52:35PM +1000, Jonathan Liu wrote:
> The drm_get_edid function should be used instead of drm_do_get_edid by
> exposing the DDC bus as an I2C adapter. Implement this for A10s.
>
> Signed-off-by: Jonathan Liu
Your commit log should explain *why* that function should be u
https://bugs.freedesktop.org/show_bug.cgi?id=101387
--- Comment #6 from Carlo Caione ---
Uhm, probably I have found something.
In amdgpu_atombios_crtc_powergate_init() we are declaring
ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
so that args is basically a 32byte struct. We are passing down
https://bugs.freedesktop.org/show_bug.cgi?id=100070
--- Comment #3 from Gregor Münch ---
Thanks for your response, I will try to provide the trace by the end of the
week.
Im just curious, since Plagman can give you the steam key and the problem also
exists on RX470 / RX480 according to the links
On Thu, Jun 08, 2017 at 03:25:26PM +0200, Christoph Hellwig wrote:
> DMA_ERROR_CODE is not supposed to be used by drivers.
>
> Signed-off-by: Christoph Hellwig
> ---
> drivers/firmware/tegra/ivc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Thierry Reding
signature.
On Tue, Jun 13, 2017 at 01:50:16PM +0200, Michael Thayer wrote:
> 12.06.2017 18:03, Greg Kroah-Hartman wrote:
> > On Mon, Jun 12, 2017 at 05:40:21PM +0200, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 12-06-17 13:44, Greg Kroah-Hartman wrote:
> >>> On Mon, Jun 12, 2017 at 12:07:41PM +0200, Hans de Go
https://bugs.freedesktop.org/show_bug.cgi?id=101387
--- Comment #7 from Carlo Caione ---
Just to be clear. I have already verified that the address of &args and ctx->ps
are the same, so this is definitely something we want to fix somehow.
--
You are receiving this mail because:
You are the assi
Most, but not all, paths where calling the with struct_mutex held. The
fast-path in msm_gem_get_iova() (plus some sub-code-paths that only run
the first time) was masking this issue.
So lets just always hold struct_mutex for hw_init(). And sprinkle some
WARN_ON()'s and might_lock() to avoid this
https://bugs.freedesktop.org/show_bug.cgi?id=99851
--- Comment #49 from intermedi...@hotmail.com ---
Hi Michel,
can be, i have many kernel traces on Qoriq machine from latest kernels but for
what i see look like a qman issue . i dont know if qman have something related
to pci/pcie
--
You are r
On Tue, May 23, 2017 at 03:14:22AM +0300, Dmitry Osipenko wrote:
> The framebuffers console fbcon_startup() increments the tegra_drm module
> 'use' refcount via try_module_get(), causing an interlock of the DRM subsys
> and the tegra_drm modules. In result, the tegra_drm module can't be unloaded
>
On Tue, May 23, 2017 at 03:14:23AM +0300, Dmitry Osipenko wrote:
> Commit 33a8eb8 ("Implement runtime PM") introduced HW reset control. It
> causes a hang on Tegra20 if both display controllers are utilized (RGB
> panel and HDMI). The TRM suggests that each display controller has its own
> reset co
From: Colin Ian King
The function cnl_ddi_dp_set_dpll_hw_state does not need to be in global
scope, so make it static.
Cleans up sparse warning:
"symbol 'cnl_ddi_dp_set_dpll_hw_state' was not declared. Should it
be static?"
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/intel_dpll_mg
On Tue, Jun 13, 2017 at 03:45:14PM +0200, Michael Thayer wrote:
> 13.06.2017 14:48, Greg Kroah-Hartman wrote:
> [Discussion of vboxvideo coding style.]
> > Once your code is accepted into the main kernel tree, why would you
> > continue to work in an out-of-tree repo anyway? That's ripe for
> > di
On Tue, May 23, 2017 at 02:39:33AM +0200, Erik Faye-Lund wrote:
> On Tue, May 23, 2017 at 2:14 AM, Dmitry Osipenko wrote:
> > Several channels could be made to write the same unit concurrently via the
> > SETCLASS opcode, trusting userspace is a bad idea. It should be possible to
> > drop the per-
On Tue, Jun 13, 2017 at 5:45 AM, Michel Dänzer wrote:
> From: Xiaojie Yuan
>
> v2: fix an off by one error and leading white spaces
> v3: use thread safe strtok_r(); initialize len before calling getline();
> change printf() to drmMsg(); add initial amdgpu.ids
> v4: integrate some recent inte
On Tue, Jun 13, 2017 at 09:23:45AM -0400, Rob Clark wrote:
> Most, but not all, paths where calling the with struct_mutex held. The
> fast-path in msm_gem_get_iova() (plus some sub-code-paths that only run
> the first time) was masking this issue.
>
> So lets just always hold struct_mutex for hw_
On Tue, Jun 13, 2017 at 05:18:37PM +0300, Dmitry Osipenko wrote:
> On 13.06.2017 16:45, Thierry Reding wrote:
> > On Tue, May 23, 2017 at 03:14:23AM +0300, Dmitry Osipenko wrote:
> >> Commit 33a8eb8 ("Implement runtime PM") introduced HW reset control. It
> >> causes a hang on Tegra20 if both displ
On Tue, Jun 13, 2017 at 05:00:28PM +0300, Dmitry Osipenko wrote:
> On 13.06.2017 16:43, Thierry Reding wrote:
> > On Tue, May 23, 2017 at 03:14:22AM +0300, Dmitry Osipenko wrote:
> >> The framebuffers console fbcon_startup() increments the tegra_drm module
> >> 'use' refcount via try_module_get(),
Thierry/Rob,
On Mon, May 8, 2017 at 10:54 AM, Fabio Estevam wrote:
> On Tue, Apr 25, 2017 at 1:18 PM, Marco Franchi wrote:
>> Add driver for Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480)
>> TFT with Touch-Panel.
>>
>> Datasheet available at:
>> http://www.glyn.de/data/glyn/media/doc/43wvf1g
Hi Peter,
On Tue, 13 Jun 2017 16:34:25 +0200
Peter Rosin wrote:
> Hi!
>
> I need color lookup support for the atmel-hlcdc driver, and had a peek
> at the code. I also looked at the drivers/gpu/drm/stm driver and came
> up with the below diff. It compiles, but I have not booted it for the
> simp
On Tue, Jun 13, 2017 at 05:00:15PM +0200, Michael Thayer wrote:
> 13.06.2017 15:59, Greg Kroah-Hartman wrote:
> > On Tue, Jun 13, 2017 at 03:45:14PM +0200, Michael Thayer wrote:
> >> 13.06.2017 14:48, Greg Kroah-Hartman wrote:
> >> [Discussion of vboxvideo coding style.]
> >>> Once your code is acc
Daniel Stone writes:
> Hi Eric,
>
> On 8 June 2017 at 01:13, Eric Anholt wrote:
>> This allows mesa to set the tiling format for a BO and have that
>> tiling format be respected by mesa on the other side of an
>> import/export (and by vc4 scanout in the kernel), without defining a
>> protocol to
https://bugzilla.kernel.org/show_bug.cgi?id=196037
--- Comment #3 from Mansoor Ahmed (m89...@outlook.com) ---
Contacting Nvidia did little help. It just resolved my problem, but still the
bug is there. www.devtalk.nvidia.com was the only solution I got. When Nivida
was contacted officially they ut
https://bugs.freedesktop.org/show_bug.cgi?id=101325
--- Comment #10 from Julien Isorce ---
Hi Luke,
I can reproduce the ring stalled issue using your apitrace 100% of the time.
In apitrace output I could notice:
warning: extension `GL_EXT_gpu_shader4' unsupported in fragment shader
message: api
https://bugzilla.kernel.org/show_bug.cgi?id=196037
--- Comment #4 from Len Brown (l...@kernel.org) ---
> It's absolutely ridiculous.
I think the word you are searching for us "unsupported".
--
You are receiving this mail because:
You are watching the assignee of the bug.
___
Brian Starkey writes:
> Hi Boris,
>
> Sorry lost track of this thread.
>
>
> On Tue, Jun 06, 2017 at 09:13:00PM +0200, Boris Brezillon wrote:
>>Hi Brian,
>>
>>Le Mon, 5 Jun 2017 12:25:50 +0100,
>>Brian Starkey a écrit :
>>
>>> Hi Boris,
>>>
>>> I can't speak for the HW-specific details, but the
On Tue, Jun 13, 2017 at 01:50:16PM +0200, Michael Thayer wrote:
> 12.06.2017 18:03, Greg Kroah-Hartman wrote:
> > On Mon, Jun 12, 2017 at 05:40:21PM +0200, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 12-06-17 13:44, Greg Kroah-Hartman wrote:
> >>> On Mon, Jun 12, 2017 at 12:07:41PM +0200, Hans de Go
It serves no purpose, things should be sufficiently synchronized already
by atomic framework. And it is somewhat awkward to be holding a spinlock
when msm_gem_iova() is going to start needing to grab a mutex.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 10 --
No functional change, that will come later. But this will make it
easier to deal with dynamically created address spaces (ie. per-
process pagetables for gpu).
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8
drivers/gpu/drm/msm/adreno/a5xx_power.c | 5 ++
Pull some of the logic out into msm_gem_new() (since we don't need to
care about the imported-bo case), and don't defer allocating pages. The
latter is generally a good idea, since if we are using VRAM carveout to
allocate contiguous buffers (ie. no IOMMU), the allocation is more
likely to fail.
Before we can shift to passing the address-space object to _get_iova(),
we need to fix a few places (dsi+fbdev) that were hard-coding the adress
space id. That gets somewhat easier if we just move these to the kms
base class.
Prep work for next patch.
Signed-off-by: Rob Clark
---
drivers/gpu/d
A step towards having per-process pagetables, we need to be able to map
a given buffer into multiple address spaces.
This is similar to Jordan's "drm/msm: get an iova from the address space
instead of an id" patch, except split up into smaller steps, and fixing
some issues with the non-IOMMU case.
Now that the msm_gem supports an arbitrary number of vma's, we no longer
need to assign an id (index) to each address space. So rip out the
associated code.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7 ---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 7 ---
d
It means we have to do a list traversal where we once had an index into
a table. But the list will normally have one or two entries.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 138 +-
drivers/gpu/drm/msm/msm_gem.h | 4 +-
2 files chang
On Tue, Jun 13, 2017 at 02:49:43PM -0400, Rob Clark wrote:
> It serves no purpose, things should be sufficiently synchronized already
> by atomic framework. And it is somewhat awkward to be holding a spinlock
> when msm_gem_iova() is going to start needing to grab a mutex.
>
> Signed-off-by: Rob
On Tue, Jun 13, 2017 at 02:49:44PM -0400, Rob Clark wrote:
> Before we can shift to passing the address-space object to _get_iova(),
> we need to fix a few places (dsi+fbdev) that were hard-coding the adress
nit - adress -> address. Otherwise,
Acked-By: Jordan Crouse
> space id. That gets some
On Tue, Jun 13, 2017 at 02:49:45PM -0400, Rob Clark wrote:
> No functional change, that will come later. But this will make it
> easier to deal with dynamically created address spaces (ie. per-
> process pagetables for gpu).
>
> Signed-off-by: Rob Clark
Acked-by: Jordan Crouse
> ---
> drivers
On Tue, Jun 13, 2017 at 02:49:46PM -0400, Rob Clark wrote:
> Pull some of the logic out into msm_gem_new() (since we don't need to
> care about the imported-bo case), and don't defer allocating pages. The
> latter is generally a good idea, since if we are using VRAM carveout to
> allocate contiguo
On Tue, Jun 13, 2017 at 02:49:47PM -0400, Rob Clark wrote:
> It means we have to do a list traversal where we once had an index into
> a table. But the list will normally have one or two entries.
>
> Signed-off-by: Rob Clark
I dig the rename - makes more sense.
Acked-by: Jordan Crouse
> ---
On Tue, Jun 13, 2017 at 02:49:48PM -0400, Rob Clark wrote:
> Now that the msm_gem supports an arbitrary number of vma's, we no longer
> need to assign an id (index) to each address space. So rip out the
> associated code.
>
> Signed-off-by: Rob Clark
Acked-by: Jordan Crouse
> ---
> drivers/gp
https://bugs.freedesktop.org/show_bug.cgi?id=101368
--- Comment #6 from Ben Steel ---
Created attachment 131935
--> https://bugs.freedesktop.org/attachment.cgi?id=131935&action=edit
dmesg with debug=trace
Thanks for your efforts. Boot with patched driver unsuccessful. Dmesg from
rmmod and insm
tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-4.11
head: ee1356406141af842dcd7f689749fced30185cf4
commit: 42376247f5e6b8f95e70ae9caa8b1d799a836448 [1374/1377] drm/amd/display:
add bw logging for dcn
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC
https://bugs.freedesktop.org/show_bug.cgi?id=101368
--- Comment #7 from Ilia Mirkin ---
Interesting. Dies in PMU preinit somewhere, which in turn calls nkvm_pmu_reset.
I don't see an obvious reason for that to die except ... if PTIMER is somehow
off?
The only difference is from 1e2115d8c0c0da624
ALSA SoC needs to know connected DAI ID for probing. Using
the new audio-card-graph approach, ports/endpoints are used
to describe how the links are connected. Unfortunately, since
ports/endpoints are used as well for video linkages, there
are some issues mixing the port ids to the two (video and
a
On Tue, Jun 13, 2017 at 2:59 PM, John Stultz wrote:
> ALSA SoC needs to know connected DAI ID for probing. Using
> the new audio-card-graph approach, ports/endpoints are used
> to describe how the links are connected. Unfortunately, since
> ports/endpoints are used as well for video linkages, ther
https://bugs.freedesktop.org/show_bug.cgi?id=101415
Bug ID: 101415
Summary: Error running clBLAS clblas-client: unsupported call
to function mem_fence
Product: Mesa
Version: 17.1
Hardware: x86-64 (AMD64)
OS
tree: git://people.freedesktop.org/~agd5f/linux.git raven
head: c6ee08eda872bc7ac60ed0ba82a5d85e696a894c
commit: a1146cea5877c42e10858082cf9018fd63165a92 [340/1060] drm/amdgpu: handle
CPU access for split VRAM buffers (v2)
config: parisc-allyesconfig (attached as .config)
compiler: hppa-linux-
On Tue, Jun 13, 2017 at 6:52 PM, Sushmita Susheelendra
wrote:
> Buffer object specific resources like pages, domains, sg list
> need not be protected with struct_mutex. They can be protected
> with a buffer object level lock. This simplifies locking and
> makes it easier to avoid potential recursi
https://bugs.freedesktop.org/show_bug.cgi?id=101368
Ilia Mirkin changed:
What|Removed |Added
QA Contact||xorg-t...@lists.x.org
Product|
On Tue, Jun 13, 2017 at 02:59:49PM -0700, John Stultz wrote:
> ALSA SoC needs to know connected DAI ID for probing. Using
> the new audio-card-graph approach, ports/endpoints are used
> to describe how the links are connected. Unfortunately, since
Unless someone objects in the next week or so I in
On Tegra20 an overlay plane should be clipped, otherwise its output is
distorted once plane crosses display boundary.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/dc.c | 29 +
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/t
On 13.06.2017 20:31, Mikko Perttunen wrote:
> On 05/23/2017 03:14 AM, Dmitry Osipenko wrote:
>> Do gathers coping before patching them, so the original gathers are left
>> untouched. That's not as bad as leaking a kernel addresses, but still
>> doesn't feel right.
>>
>> Signed-off-by: Dmitry Osipen
Commit 33a8eb8 ("Implement runtime PM") introduced HW reset control. It
causes a hang on Tegra20 if both display controllers are utilized (RGB
panel and HDMI). The TRM suggests that each display controller has its own
reset control, apparently it is not correct.
Fixes: 33a8eb8d40ee ("drm/tegra: dc
Perform gathers coping before patching them, so that original gathers are
left untouched. That's not as bad as leaking kernel addresses, but still
doesn't feel right.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Mikko Perttunen
---
drivers/gpu/host1x/job.c | 39 +++---
The struct host1x_cmdbuf is unused, let's remove it.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Erik Faye-Lund
Reviewed-by: Mikko Perttunen
---
drivers/gpu/host1x/job.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/host1x/job.h b/drivers/gpu/host1x/job.h
index 0debd93a
The RESTART opcode terminates the gather and restarts the CDMA fetching from
a specified word << 2 relative to the CDMA start address. That shouldn't be
allowed to be done by userspace.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Erik Faye-Lund
Reviewed-by: Mikko Perttunen
---
drivers/gpu/host
On 13.06.2017 22:03, Mikko Perttunen wrote:
>
>
> On 06/13/2017 09:21 PM, Dmitry Osipenko wrote:
>> On 13.06.2017 20:31, Mikko Perttunen wrote:
>>> On 05/23/2017 03:14 AM, Dmitry Osipenko wrote:
Do gathers coping before patching them, so the original gathers are left
untouched. That's n
On 06/13/2017 09:21 PM, Dmitry Osipenko wrote:
On 13.06.2017 20:31, Mikko Perttunen wrote:
On 05/23/2017 03:14 AM, Dmitry Osipenko wrote:
Do gathers coping before patching them, so the original gathers are left
untouched. That's not as bad as leaking a kernel addresses, but still
doesn't feel
12.06.2017 18:03, Greg Kroah-Hartman wrote:
> On Mon, Jun 12, 2017 at 05:40:21PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> On 12-06-17 13:44, Greg Kroah-Hartman wrote:
>>> On Mon, Jun 12, 2017 at 12:07:41PM +0200, Hans de Goede wrote:
> The most important thing is for the driver to be atomic if
Arguments of the .is_addr_reg() are swapped in the definition of the
function, that is quite confusing.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Erik Faye-Lund
Reviewed-by: Mikko Perttunen
---
include/linux/host1x.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include
From: Mathieu Larouche
- Changed the HiPri value for G200e4 to always be 0.
- Added Bandwith limitation to block resolution above 1920x1200x60Hz
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mgag200/mgag
Incorrectly shifted relocation address will cause a lower memory corruption
and likely a hang on a write or a read of an arbitrary data in case of IOMMU
absent. As of now there is no use for the address shifting (at least on
Tegra20) and adding a proper shifting / sizes validation is much more work
13.06.2017 14:48, Greg Kroah-Hartman wrote:
[Discussion of vboxvideo coding style.]
> Once your code is accepted into the main kernel tree, why would you
> continue to work in an out-of-tree repo anyway? That's ripe for
> disaster, what's keeping you from just working with the in-tree version?
On
On 13.06.2017 17:06, Thierry Reding wrote:
> On Tue, May 23, 2017 at 02:39:33AM +0200, Erik Faye-Lund wrote:
>> On Tue, May 23, 2017 at 2:14 AM, Dmitry Osipenko wrote:
>>> Several channels could be made to write the same unit concurrently via the
>>> SETCLASS opcode, trusting userspace is a bad id
The waitchecks along with multiple syncpoints per submit are not ready for
use yet, let's forbid them for now.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 60 ++---
drivers/gpu/host1x/job.h| 7 --
There is no host1x_cdma_stop() in the code, let's remove its definition
from the header file.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Erik Faye-Lund
Reviewed-by: Mikko Perttunen
---
drivers/gpu/host1x/cdma.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/host1x/cdma.h b/dri
Check waits in the firewall in a way it is done for relocations.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Mikko Perttunen
---
drivers/gpu/host1x/job.c | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/host1x/job.c b/drivers/
From: Mikko Perttunen
This is largely a rewrite of the Host1x channel allocation code, bringing
several changes:
- The previous code could deadlock due to an interaction
between the 'reflock' mutex and CDMA timeout handling.
This gets rid of the mutex.
- Support for more than 32 channels, re
The GART driver was disabled because it was picked by as an IOMMU provider
for the DRM driver on Tegra20, which is not the purpose of the GART. Now
DRM driver avoids to use IOMMU on Tegra20, so the GART driver can be
re-enabled. Potentially there are interesting use cases of the GART for
Tegra20, l
The blocking gather copy allocation is a major performance downside of the
Host1x firewall, it may take hundreds milliseconds which is unacceptable
for the real-time graphics operations. Let's try a non-blocking allocation
first as a least invasive solution, it makes opentegra (Xorg driver)
perform
Several channels could be made to write the same unit concurrently via the
SETCLASS opcode, trusting userspace is a bad idea. It should be possible to
drop the per-client channel reservation and add a per-unit locking by
inserting MLOCK's to the command stream to re-allow the SETCLASS opcode, but
i
There is no IOMMU on Tegra20, instead a GART would be picked as an IOMMU
provider.
Signed-off-by: Dmitry Osipenko
Acked-by: Joerg Roedel
---
drivers/gpu/drm/tegra/drm.c | 3 ++-
drivers/gpu/host1x/dev.c| 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/t
Hi!
I need color lookup support for the atmel-hlcdc driver, and had a peek
at the code. I also looked at the drivers/gpu/drm/stm driver and came
up with the below diff. It compiles, but I have not booted it for the
simple reason that I can't imagine it will work.
Sure, the code fills the clut reg
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