https://bugs.freedesktop.org/show_bug.cgi?id=99418
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Created attachment 128993
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Created attachment 128994
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Created attachment 128995
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--- Comment #5 from lei.p...@gmail.com ---
(In reply to lei.pero from comment #2)
> Created attachment 128993 [details]
> glxinfo
(In reply to Michel Dänzer from comment #1)
> Please attach the corresponding Xorg log file and output of glxinfo.
On Mon, Jan 16, 2017 at 10:44:55AM -0500, Andrey Grodzovsky wrote:
> Allows using atomic flip helpers for drivers
> using ASYNC flip.
> Remove ASYNC_FLIP restriction in helpers and
> caches the page flip flags in drm_plane_state
> to be used in the low level drivers.
>
> Signed-off-by: Andrey Grod
2017년 01월 17일 04:08에 Gustavo Padovan 이(가) 쓴 글:
> Hi Inki,
>
> 2017-01-16 Inki Dae :
>
>> This patch relpaces specific atomic commit function
>> with atomic helper commit one, which also includes
>> atomic_commit_tail callback for Exynos SoC becasue
>> crtc devices on Exynos SoC uses power domai
static void vop_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
if (WARN_ON(!vop->is_enabled))
return;
The issues seems vop is not enable. but commit planes is using
DRM_PLANE_COMMIT_ACTIVE_ONLY...
Hi Randy
Can you add some print for this
The DRM device is not guaranteed by the bridge API to be available
before the attach callback. The driver performs properly at the moment
as it doesn't use the drm_bridge_add() registration method. As this will
be changed later, move connector creation to attach time to ensure
compatibility with th
The drm_bridge instance is always needed, there's no point in allocating
it separately.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw-hdmi.
The field isn't needed, remove it.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index 2c85b6c07a80..ef
There's no need to duplicate identical code in multiple drivers (two at
the moment, one more to come soon). Move it to the dw-hdmi core where it
can be shared. If resource allocation ever becomes device-specific later
we'll always have the option of splitting it out again.
While it at pass the pla
The next commit will reference structures and functions in a way that
currently requires forward declarations. Reorder the functions to avoid
that. No functional change to the code is performed.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 72 ++
The latter is just an int wrapper around the former void function that
unconditionally returns 0. As the return value is never checked, merge
the two functions into one.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 9 +
1 file changed, 1
From: Kieran Bingham
The 'prep' parameter passed to hdmi_phy_configure() is useless. It is
hardcoded as 0, and if set, simply prevents the configure function from
executing.
Remove it.
Signed-off-by: Kieran Bingham
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/
From: Kieran Bingham
The current code hard codes the call of hdmi_phy_configure() to be 8bpp
and provides extraneous error checking to verify that this hardcoded
value is correct. Simplify the implementation by removing the argument.
Signed-off-by: Kieran Bingham
Signed-off-by: Laurent Pinchart
Hello,
This patch series contains the part of my pending dw-hdmi patches that have
been successfully tested on all three supported platforms (i.MX6, RK3288 and
R-Car H3) and have been reviewed without any problem being reported.
All patches here have been previously posted as part of the "[PATCH
The bit is documented in a Rockchip BSP as
#define m_SVSRET_SIG (1 << 5) /* depend on PHY_MHL_COMB0=1 */
This is confirmed by a Renesas platform, which uses a 2.0 DWC HDMI TX as
the RK3288. Rename the bit accordingly.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
driv
The PHY reset signal is controlled by bit PHYRSTZ in the MC_PHYRSTZ
register. The signal is active low on Gen1 PHYs and active high on Gen2
PHYs. The driver toggles the signal high then low, which is correct for
all currently supported platforms, but the register values macros are
incorrectly named
The DWC HDMI TX can be recognized by the two product identification
registers. If the registers don't read as expect the IP will be very
different than what the driver has been designed for, or will be
misconfigured in a way that makes it non-operational (invalid memory
address, incorrect clocks, .
Bit 0 in CONFIG1_ID tells whether the IP core uses an AHB slave
interface for control. The correct way to identify AHB audio DMA support
is through bit 1 in CONFIG3_ID.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 6 +++---
drivers/gpu/drm/bridg
Hotplug events should only be forwarded to the DRM core by the interrupt
handler when the bridge has been attached, otherwise the DRM device
pointer will be NULL, resulting in a crash.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 3 ++-
1 file c
The master argument isn't used. The data argument, a void pointer, is
used by the bind function only where it's cast to a drm_device pointer,
which can easily be obtained from the encoder argument instead. Remove
them.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/
Use the device version queried at runtime instead of the device type
provided through platform data to handle the overflow workaround. This
will make support of other SoCs integrating the same HDMI TX controller
version easier.
Among the supported platforms only i.MX6DL and i.MX6Q have been
identi
Make it clear that the core bridge/dw_hdmi.txt document isn't a device
tree binding by itself but is meant to be referenced by platform device
tree bindings, and update the Rockchip and Freescale DWC HDMI TX
bindings to reference it.
Signed-off-by: Laurent Pinchart
Acked-by: Rob Herring
---
...
As an option for drivers not based on the component framework, register
the bridge with the DRM core with the DRM bridge API. Existing drivers
based on dw_hdmi_bind() and dw_hdmi_unbind() are not affected as those
functions are preserved with their current behaviour.
Signed-off-by: Laurent Pinchar
Replace the hardcoded register address numerical values with macros to
clarify the code.
This change has been tested by comparing the assembly code before and
after the change.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 35 ---
According to the PHY IP core vendor, the SVSRET signal must be asserted
before resetting the PHY. Tests on RK3288 and R-Car Gen3 showed no
regression, the change should thus be safe.
Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
---
drivers/gpu/drm/bridge/dw-hdmi.c | 10 +-
1
Detect the PHY type and use it to handle the PHY type-specific SVSRET
signal.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/dw-hdmi.c | 68 ++--
include/drm/bridge/dw_hdmi.h | 10 ++
2 files changed, 75 insertions(+), 3 deletions(-)
diff
Hi Andrey,
On Tuesday 17 Jan 2017 04:03:11 Grodzovsky, Andrey wrote:
> On Monday, January 16, 2017 5:18 PM Laurent Pinchart wrote:
> > On Monday 16 Jan 2017 10:44:55 Andrey Grodzovsky wrote:
> > > Allows using atomic flip helpers for drivers using ASYNC flip.
> > > Remove ASYNC_FLIP restriction in
Hi Inki,
Thank you for the patch.
On Monday 16 Jan 2017 18:13:22 Inki Dae wrote:
> This patch relpaces specific atomic commit function
> with atomic helper commit one, which also includes
> atomic_commit_tail callback for Exynos SoC becasue
> crtc devices on Exynos SoC uses power domain device
>
Hi John
On 01/16/2017 08:44 PM, John Keeping wrote:
On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote:
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by:
same as https://patchwork.kernel.org/patch/9518417/
Tested-by: Chris Zhong
Reviewed-by: Chris Zhong
On 09/20/2016 01:17 AM, John Keeping wrote:
In a couple of places here we use "val" for the value that is about to
be written to a register but then reuse the same variable for the value
of a s
Dan Carpenter writes:
> We accidentally return success even if vc4_full_res_bounds_check() fails.
>
> Fixes: d5b1a78a772f ("drm/vc4: Add support for drawing 3D frames.")
> Signed-off-by: Dan Carpenter
Thanks. Reviewed, added Eric's review, and pushed to -fixes.
signature.asc
Description: PGP
On 09/20/2016 01:17 AM, John Keeping wrote:
There is no need to keep a pointer to the mode around since we know it
will be present in the connector state.
Signed-off-by: John Keeping
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 31 ---
1 file changed, 16 inserti
On Tue, 17 Jan 2017 17:31:53 +0800, Chris Zhong wrote:
> On 01/16/2017 08:44 PM, John Keeping wrote:
> > On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote:
> >
> >> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> >> for some panel, it will cause the screen display is n
https://bugs.freedesktop.org/show_bug.cgi?id=91880
--- Comment #147 from John Boero ---
Would love to see this get pushed through. Frustrating having to manually
build kernels each release. It looks like history of the Fedora kernels has
this being disabled and re-enabled by default a few times
The Amlogic GX SoCs implements a Synopsys DesignWare HDMI TX Controller
in combination with a very custom PHY.
Thanks to Laurent Pinchart's changes, the HW report the following :
Detected HDMI TX controller v2.01a with HDCP (Vendor PHY)
The following differs from common PHY integration as manage
The Synopsys Designware HDMI TX Controller does not enforce register access
on platforms instanciating it.
The current driver supports two different types of memory-mapped flat
register access, but in order to support the Amlogic Meson SoCs integration,
and provide a more generic way to handle all
Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/dw-hdmi.c | 7 +--
include/drm/bridge/dw_hdmi.h | 9 +
2 files change
The Synopsys DesignWare HDMI TX Controller support various Transceivers (PHY)
attached to the controller, but also allows fully custom PHYs to be connected.
Add PHY init, disable functions in plat_data to handle fully custom PHY init.
Some custom PHYs also handles the HPD and RxSense separately a
If the input pixel format is not RGB, the CSC must be enabled in order to
provide valid pixel to DVI sinks.
This patch removes the hdmi only dependency on the CSC enabling.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/bridge/dw-hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-
Hi Gabriel,
2017-01-12 Gabriel Krisman Bertazi :
> Registering the connector explicitly right after creation is not
> necessary for modesetting drivers, because drm_dev_register already takes
> care of this on the core side, by calling drm_modeset_register_all.
>
> In addition, performing the in
https://bugs.freedesktop.org/show_bug.cgi?id=99292
--- Comment #4 from Christoph Haag ---
Someone said that with mesa with --enable-debug it runs in an assert before the
gpu hang happens, so I tried it to add it to the bug report, but this did not
happen for me. I get no assert and the GPU still
Gustavo Padovan writes:
> I'm not confortable with exposing minor->type here and making qxl
> the first driver to use it outside of drm core. Don't we have any other
> way.
>
> I see that inside qxl_debugfs_add_files() we have a check for already
> registered files. Wouldn't that or some modific
This avoids using the deprecated drm_get_pci_dev() and load() hook
interfaces in the qxl driver.
The only tricky part is to ensure TTM debugfs initialization happens
after the debugfs root node is created, which is done by moving that
code into the debufs_init() hook.
Tested on qemu with igt and
This avoids using the deprecated drm_put_dev() and unload() hook
interfaces in the qxl driver.
Signed-off-by: Gabriel Krisman Bertazi
Cc: Dave Airlie
Cc: Daniel Vetter
Cc: Gustavo Padovan
---
drivers/gpu/drm/qxl/qxl_drv.c | 11 +--
drivers/gpu/drm/qxl/qxl_drv.h | 2 --
drivers/gpu/dr
decon_commit is called just after reset so video is disabled anyway.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
Hi Inki,
This is my final fight with DECON_UPDATE issues (I hope). My two previous
patches
fixed problems on panel path, this patchset fixes also TV path.
The root cause of all evil was in incorrect DECON_CMU programming.
Now it works correctly on:
- panel,
- TV,
- both.
I have not observed (so
DECON_TV requires STANDALONE_UPDATE after output enabling, otherwise it does
not start. This change is neutral for DECON.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_dec
DECON_CMU register has reserved bits which should not be zeroed, otherwise
IP can behave strangely and cause IOMMU faults.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_d
Joonyoung Shim wrote:
> The size of cmdlist is integer type, so it can be overflowed by cmd and
> cmd_buf that has too big size. This patch will fix overflow issue as
> checking maximum size of cmd and cmd_buf.
I don't understand/see the issue here. Could you point out for which
input of the set_cm
Hi Neil,
Thank you for the patch.
On Tuesday 17 Jan 2017 13:31:31 Neil Armstrong wrote:
> The Synopsys Designware HDMI TX Controller does not enforce register access
> on platforms instanciating it.
> The current driver supports two different types of memory-mapped flat
> register access, but in
Hi Neil,
Thank you for the patch.
On Tuesday 17 Jan 2017 13:31:33 Neil Armstrong wrote:
> If the input pixel format is not RGB, the CSC must be enabled in order to
> provide valid pixel to DVI sinks.
> This patch removes the hdmi only dependency on the CSC enabling.
>
> Signed-off-by: Neil Armst
Hi Neil,
Thank you for the patch.
On Tuesday 17 Jan 2017 13:31:34 Neil Armstrong wrote:
> Some display pipelines can only provide non-RBG input pixels to the HDMI TX
> Controller, this patch takes the pixel format from the plat_data if
> provided.
>
> Signed-off-by: Neil Armstrong
> ---
> driv
Hi Neil,
Thank you for the patch.
On Tuesday 17 Jan 2017 13:31:32 Neil Armstrong wrote:
> The Synopsys DesignWare HDMI TX Controller support various Transceivers
> (PHY) attached to the controller, but also allows fully custom PHYs to be
> connected.
>
> Add PHY init, disable functions in plat_d
Hello,
Here is the collected list of patches that I have accumulated since last
December in my inbox. They are offered for review and comments before
I commit them to the mali-dp tree and they get added to linux-next.
Best regards,
Liviu
Brian Starkey (4):
drm: mali-dp: Don't force source size
From: Brian Starkey
The horizontal and vertical flip flags were the wrong way around,
causing reflect-x to result in reflect-y being applied and vice-versa.
Fix them.
Fixes: ad49f8602fe8 ("drm/arm: Add support for Mali Display Processors")
Signed-off-by: Brian Starkey
Signed-off-by: Liviu Duda
From: Brian Starkey
The destination rectangle provided by userspace in the CRTC_X/Y/W/H
properties is already expressed as the dimensions after rotation.
This means we shouldn't swap the width and height ourselves when a
90/270 degree rotation is requested, so remove the code doing the swap.
Fix
This struct member managed to outlive the submission process without
being removed. It is useless.
Signed-off-by: Liviu Dudau
---
drivers/gpu/drm/arm/malidp_drv.c | 2 --
drivers/gpu/drm/arm/malidp_drv.h | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/arm/ma
From: Brian Starkey
Remove the check enforcing that src_w and src_h match crtc_w and crtc_h,
as this prevents rotation from working.
The check was intended to disallow scaling, but
drm_plane_helper_check_state() does that for us, while also taking
rotation into account, so the removed check was
From: Mihail Atanassov
When updating the rotation fields, one of the assignments zeroes out the
rest of the register fields, which include settings for chroma siting,
inverse gamma, AMBA AXI caching, and alpha blending.
Signed-off-by: Mihail Atanassov
Signed-off-by: Liviu Dudau
---
drivers/gp
From: Shailendra Verma
There is possible deference of NULL pointer on return of
malidp_duplicate_plane_state() if kmalloc fails. Check the
returned kmalloc pointer before continuing.
Signed-off-by: Shailendra Verma
[cleaned up the code and re-formatted the commit message]
Signed-off-by: Liviu D
From: Brian Starkey
We're going to use the same format list for output formats, so rename
everything related to input formats to avoid confusion.
Signed-off-by: Brian Starkey
[touched commit message to clarify the final struct name]
Signed-off-by: Liviu Dudau
---
drivers/gpu/drm/arm/malidp_hw
Mali DP's plane ->atomic_check() only checks for the new state submitting
frame buffers with supported pixel formats and if there is enough
rotation memory for rotated planes. Add a call to
drm_plane_helper_check_state() to add additional checks for plane
state validity and clipping issues.
Signed
This is just a cleanup, no functional change.
The fixup code for 1366x768 in drm_mode_create_from_cmdline_mode() is
basically a copy of the existing code in drm_edid.c. Make the latter
code public so that it can be called from the former function.
Signed-off-by: Takashi Iwai
---
v1->v2: Fix the
On Sat, Jan 14, 2017 at 11:20:58PM -0600, Andy Gross wrote:
> + Stanimir
>
> On Sat, Jan 14, 2017 at 09:49:01PM -0600, Andy Gross wrote:
> > On Fri, Jan 13, 2017 at 04:24:38PM -0700, Jordan Crouse wrote:
> > > On Fri, Jan 13, 2017 at 11:12:41AM -0600, Andy Gross wrote:
> > > > On Mon, Nov 28, 2016
On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula
wrote:
> On Fri, 13 Jan 2017, Rodrigo Vivi wrote:
>> This and all the remaining patches on this series (6,7,8 and 9) got
>> merged to dinq.
>
> Given that this patch series was not properly sent as a thread, I don't
> think our CI ran it as a whole, an
On Tue, Jan 03, 2017 at 04:52:50PM +0100, Arnaud Pouliquen wrote:
> Add helper to allow users to retrieve the speaker allocations without
> knowledge of the ELD structure.
You don't appear to have sent this to any of the DRM maintainers - it
does need review from them.
signature.asc
Description:
On Mon, Jan 16, 2017 at 09:54:31AM +0100, Arnaud Pouliquen wrote:
> Hello,
>
> Any comments on this patch-set?
> what about the introduction of pcm new callback in DAI ops to use chmap
> helpers?
> Is it something reasonable, or should i come back on V1?
Please don't send content free pings and p
We copy the unvalidated ioctl arguments from the user into kernel
temporary memory to run the validation from, to avoid a race where the
user updates the unvalidate contents in between validating them and
copying them into the validated BO.
However, in setting up the layout of the kernel side, we
By failing to set the errno, we'd continue on to trying to set up the
RCL, and then oops on trying to dereference the tile_bo that binning
validation should have set up.
Reported-by: Ingo Molnar
Signed-off-by: Eric Anholt
Fixes: d5b1a78a772f ("drm/vc4: Add support for drawing 3D frames.")
---
d
Stefan Wahren writes:
>> Hi Eric,
>>
>> could you please resend this patch [1], because it's still not applied in
>> Linux 4.10-rc2.
>>
>> Thanks
>> Stefan
>>
>> [1] - https://patchwork.kernel.org/patch/9369793/
>
> ping ...
It's in drm-vc4-fixes now. I just sent out two more fixes, and I shou
Mark Brown writes:
> [ Unknown signature status ]
> On Tue, Jan 03, 2017 at 04:52:50PM +0100, Arnaud Pouliquen wrote:
>> Add helper to allow users to retrieve the speaker allocations without
>> knowledge of the ELD structure.
>
> You don't appear to have sent this to any of the DRM maintainers -
The intel_dp_autotest_video_pattern() function gets invoked through the
compliance test handler on a HPD short pulse if the test type is
set to DP_TEST_VIDEO_PATTERN. This performs the DPCD registers
reads to read the requested test pattern, video pattern resolution,
frame rate and bits per color v
This patch addresses a few issues from the original patch for
DP Compliance EDID test support submitted by
Todd Previte
Video Mode requested in the EDID test handler for the EDID Read
test (CTS 4.2.2.3) should be set to PREFERRED as per the CTS spec.
v2:
* Added read debugfs data from test_data.e
This series is a rebased version of the previous series:
https://patchwork.freedesktop.org/series/16643/
DP 1.2 compliance testing can be acheived using DPR-120's CTS suite.
This compliance unit sends a short pulse to initiate link training
and video pattern generation compliance tests and sends a
v2:
* Add all the other DP Complianec TEST register defs (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Ville Syrjala
Signed-off-by: Manasi Navare
---
include/drm/drm_dp_helper.h | 58 +
1 file changed, 58 ins
This patch adds support to handle automated DP compliance
link training test requests. This patch has been tested with
Unigraf DPR-120 DP Compliance device for testing Link
Training Compliance.
After we get a short pulse Compliance test request, test
request values are read and hotplug uevent is se
Hi Tobias,
On 01/17/2017 11:24 PM, Tobias Jakobi wrote:
> Joonyoung Shim wrote:
>> The size of cmdlist is integer type, so it can be overflowed by cmd and
>> cmd_buf that has too big size. This patch will fix overflow issue as
>> checking maximum size of cmd and cmd_buf.
> I don't understand/see t
On Tue, Jan 17, 2017 at 10:04:59AM -0700, Jordan Crouse wrote:
> On Sat, Jan 14, 2017 at 11:20:58PM -0600, Andy Gross wrote:
> > + Stanimir
> >
> > On Sat, Jan 14, 2017 at 09:49:01PM -0600, Andy Gross wrote:
> > > On Fri, Jan 13, 2017 at 04:24:38PM -0700, Jordan Crouse wrote:
> > > > On Fri, Jan 1
Le mardi 17 janvier 2017 à 20:46 +0800, herman.c...@rock-chips.com a
écrit :
> If we move parser or part of DPB management mechanism into kernel we
> will face a issue as follows:
> One customer requires dpb management do a flush when stream occurs in
> order to keep output frame clean.
> While ano
> Hi Eric,
>
> could you please resend this patch [1], because it's still not applied in
> Linux 4.10-rc2.
>
> Thanks
> Stefan
>
> [1] - https://patchwork.kernel.org/patch/9369793/
ping ...
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On 01/17/2017 10:59 PM, Nicolas Dufresne wrote:
Le mardi 17 janvier 2017 à 20:46 +0800, herman.c...@rock-chips.com a
écrit :
If we move parser or part of DPB management mechanism into kernel we
will face a issue as follows:
One customer requires dpb management do a flush when stream occurs in
This patch adds a set remote state SCM API. This will be used by the
Venus and GPU subsystems to set state on the remote processors.
This work was based on two patch sets by Jordan Crouse and Stanimir
Varbanov.
Signed-off-by: Andy Gross
---
drivers/firmware/qcom_scm-32.c | 18 +
This series is,
Reviewed-by: Edward O'Callaghan
On 01/17/2017 04:16 PM, Andrey Grodzovsky wrote:
> This series is a folow-up on
> https://patchwork.kernel.org/patch/9501787/
>
> The first patch makes changes to atomic helpers to allow for
> drives with ASYNC flip support to use them.
> Patch 2
On 12/14/2016 04:11 PM, Daniel Vetter wrote:
On Wed, Dec 14, 2016 at 03:32:16PM +0200, Mikko Perttunen wrote:
On 14.12.2016 15:05, Daniel Vetter wrote:
On Wed, Dec 14, 2016 at 02:41:28PM +0200, Mikko Perttunen wrote:
On 14.12.2016 14:30, Daniel Vetter wrote:
On Wed, Dec 14, 2016 at 01:16:10PM
Hi all,
If we move parser or part of DPB management mechanism into kernel we will face
a issue as follows:
One customer requires dpb management do a flush when stream occurs in order to
keep output frame clean.
While another one requires output frame with error to keep output frame smooth.
And w
Hi Andrzej,
2017년 01월 17일 23:15에 Andrzej Hajda 이(가) 쓴 글:
> Hi Inki,
>
> This is my final fight with DECON_UPDATE issues (I hope). My two previous
> patches
> fixed problems on panel path, this patchset fixes also TV path.
> The root cause of all evil was in incorrect DECON_CMU programming.
>
>
On 17/01/17 07:16 AM, Laurent Pinchart wrote:
> On Monday 16 Jan 2017 10:44:57 Andrey Grodzovsky wrote:
>> Change-Id: Iad3e0b9b3546e4e4dc79be9233daf4fe4dba83e0
>> Signed-off-by: Andrey Grodzovsky
>> ---
>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 92 ++
>> 1 file chang
Hi Laurent,
2017년 01월 17일 18:17에 Laurent Pinchart 이(가) 쓴 글:
> Hi Inki,
>
> Thank you for the patch.
>
> On Monday 16 Jan 2017 18:13:22 Inki Dae wrote:
>> This patch relpaces specific atomic commit function
>> with atomic helper commit one, which also includes
>> atomic_commit_tail callback for E
On 2017年01月17日 18:38, Chris Zhong wrote:
@@ -821,8 +824,6 @@ static void dw_mipi_dsi_encoder_mode_set(struct
drm_encoder *encoder,
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
int ret;
-dsi->mode = adjusted_mode;
-
I prefer to keep the original method, although this"dsi->
https://bugs.freedesktop.org/show_bug.cgi?id=99444
Bug ID: 99444
Summary: [radeonsi] The Witcher 3 [Wine] starting menu is
distorted
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
https://bugs.freedesktop.org/show_bug.cgi?id=99444
Shmerl changed:
What|Removed |Added
Summary|[radeonsi] The Witcher 3|[radeonsi] The Witcher 3
|[Wi
https://bugs.freedesktop.org/show_bug.cgi?id=99444
--- Comment #1 from Shmerl ---
For the reference, to run the game in Wine, you need to set:
[HKEY_CURRENT_USER\Software\Wine\Direct3D]
"DirectDrawRenderer"="opengl"
"UseGLSL"="enabled"
"MaxVersionGL"=dword:00040005
And make sure you are usin
On 01/17/2017 01:58 PM, Laurent Pinchart wrote:
Hello,
This patch series contains the part of my pending dw-hdmi patches that have
been successfully tested on all three supported platforms (i.MX6, RK3288 and
R-Car H3) and have been reviewed without any problem being reported.
All patches here
On Tue, Jan 17, 2017 at 5:42 PM, Alastair Bridgewater
wrote:
> HDMI specification 1.4a, table 8-15 is very explicitly a "must
> support at least one of" table, not a "must support all of" table.
> It is not hard to find hardware that does not support some of the
> so-called "mandatory" modes.
>
>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> cleaning up unused define and refine function name and variable
>
> Signed-off-by: shaoming chen
> Signed-off-by: YT Shen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 73
> --
>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi interrupt control
>
> Signed-off-by: shaoming chen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 92
> ++
> 1 file changed, 92 insertions(+)
>
>
Hi, YT:
On Wed, 2017-01-11 at 14:51 +0800, YT Shen wrote:
> From: shaoming chen
>
> add dsi read/write commands for transfer function
>
> Signed-off-by: shaoming chen
Acked-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 168
> -
> 1 file changed
https://bugs.freedesktop.org/show_bug.cgi?id=99350
Thierry Reding changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
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