Hi Marek,
Am Freitag, den 26.08.2016, 16:24 +0200 schrieb Marek Vasut:
> This display expects DE pin to be active high, add the necessary flag.
>
> Signed-off-by: Marek Vasut
> Cc: Philipp Zabel
> Cc: Thierry Reding
> ---
> drivers/gpu/drm/panel/panel-simple.c | 1 +
> 1 file changed, 1 inser
Hi,
On Tue, Aug 23, 2016 at 07:24:42PM +0300, Jyri Sarha wrote:
> Thanks a lot!
> This is very helpful as I do not have LCDC rev1 HW my self, but only
> am335x based boards.
>
> On 08/23/16 15:56, Karl Beldan wrote:
> > Hi,
> >
> > I found some missing bits for rev1 of the LCDC and here are some
On 08/26/16 15:51, Rob Herring wrote:
>> --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
>> > +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
>> > @@ -17,6 +17,8 @@ Optional properties:
>> > the lcd controller.
>> > - max-pixelclock: The maximum pixel clock
We had only DRM_INFO() and DRM_ERROR(), whereas the underlying printk()
provides several other useful intermediate levels such as NOTICE and
WARNING. So this patch fills out the set by providing simple macros for
the additional levels. We don't provide _DEV_ or _ONCE or RATELIMITED
versions yet as
On Fri, Aug 26, 2016 at 06:50:56PM +0100, Dave Gordon wrote:
> We had only DRM_INFO() and DRM_ERROR(), whereas the underlying printk()
> provides several other useful intermediate levels such as NOTICE and
> WARNING. So this patch fills out the set by providing simple macros for
> the additional le
Reviewed-by: Sinclair Yeh
On Thu, Aug 11, 2016 at 03:46:22PM +0100, Chris Wilson wrote:
> Since fence_wait_timeout_reservation_object_wait_timeout_rcu() with a
> timeout of 0 becomes reservation_object_test_signaled_rcu(), we do not
> need to handle such conversion in the caller. The only challen
To pick this up again after a week of manic testing :)
On 08/18/2016 04:23 AM, Michel Dänzer wrote:
> On 18/08/16 01:12 AM, Mario Kleiner wrote:
>>
>> Intel as display gpu + nouveau for render offload worked nicely
>> on intel-ddx with page flipping, proper timing, dmabuf fence sync
>> and all.
>
On 08/18/2016 04:32 AM, Michel Dänzer wrote:
> On 18/08/16 08:51 AM, Mario Kleiner wrote:
>>
>> That's what the ati-ddx/amdgpu-ddx does at the moment, as it detects the
>> mismatch in tiling flags and uses the DRI3/Present copy path instead of
>> the pageflip path. The problem is that the servers
On 08/18/2016 09:21 PM, Marek Olšák wrote:
> On Thu, Aug 18, 2016 at 4:23 AM, Michel Dänzer wrote:
>> Maybe the rasterization as two triangles results in bad PCIe bandwidth
>> utilization. Using the asynchronous DMA engine for these transfers would
>> probably be ideal, but having the 3D engine
On Fri, Aug 26, 2016 at 4:10 PM, Mario Kleiner
wrote:
> On 08/18/2016 09:21 PM, Marek Olšák wrote:
>>
>> On Thu, Aug 18, 2016 at 4:23 AM, Michel Dänzer
>> wrote:
>>>
>>> Maybe the rasterization as two triangles results in bad PCIe bandwidth
>>> utilization. Using the asynchronous DMA engine f
i915 sometimes needs to disable planes in the middle of an atomic
commit, and then reenable them later in the same commit. Because of
this, we can't make the assumption that the state of the plane actually
changed. Since the state of the plane hasn't actually changed, neither
have it's watermarks.
u are the assignee for the bug.
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On Fri, Aug 26, 2016 at 04:25:13PM +0200, Marek Vasut wrote:
> The content of gpu->memory_base should point to start of RAM, not zero.
>
> Signed-off-by: Marek Vasut
> Cc: Lucas Stach
> Cc: Christian Gmeiner
> Cc: Russell King
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 2 ++
> 1 file cha
This display expects DE pin and data lines to be active high,
add the necessary flags.
Signed-off-by: Marek Vasut
Cc: Philipp Zabel
Cc: Thierry Reding
---
V2: Add DRM_BUS_FLAG_PIXDATA_POSEDGE to cater for the video data.
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 inserti
On 08/26/2016 05:58 PM, Philipp Zabel wrote:
> Hi Marek,
>
> Am Freitag, den 26.08.2016, 16:24 +0200 schrieb Marek Vasut:
>> This display expects DE pin to be active high, add the necessary flag.
>>
>> Signed-off-by: Marek Vasut
>> Cc: Philipp Zabel
>> Cc: Thierry Reding
>> ---
>> drivers/gpu/
Taking our cue from commit a42f6e3f8f03 ("drm/panel: simple: Add delay
timing for Sharp LQ123P1JX31"), let's add timings:
.prepare = t1 + t3
.enable = t7
.unprepare = t11 + 12
Without this, the panel may not be given enough time to come up.
Signed-off-by: Brian Norris
---
drivers/gpu/drm/pa
On Fri, Aug 26, 2016 at 05:53:38PM +0200, Lucas Stach wrote:
> Sorry, please ignore the FEC patches. Those are test patches still
> residing in my to-send folder. Sorry for the noise.
This patch actually looks correct: you are indeed correct that the
driver can end up with a packet sitting waiting
On Fri, Aug 26, 2016 at 05:49:54PM +0200, Lucas Stach wrote:
> The devicetree documentation states that those are required properties,
> so the driver should refuse to probe if those are absent to be
> consistent. This will also allow to drop some error checking from the
> clock enable/disable path
+ devicetree list
You should be including devicetree at vger.kernel.org on all binding
documents. And as Chanwoo Choi already mentioned, you didn't fix his
comments from v6:
https://lkml.org/lkml/2016/8/16/913
On Mon, Aug 22, 2016 at 11:36:22AM +0800, Lin Huang wrote:
> This patch adds the docum
Hi,
On Mon, Aug 22, 2016 at 11:36:23AM +0800, Lin Huang wrote:
> base on dfi result, we do ddr frequency scaling, register
> dmc driver to devfreq framework, and use simple-ondemand
> policy.
>
> Signed-off-by: Lin Huang
> Reviewed-by: Chanwoo Choi
> ---
> Changes in v7:
> - remove a blank line
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