it? The LLVM patch or game update?
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On 23.02.2016 04:32, Alex Deucher wrote:
> From: Christian König
>
> A fence is never later than itself. This caused a bunch of overhead for
> AMDGPU.
>
> v2: simplify check as suggested by Michel.
>
> Signed-off-by: Christian König
> Reviewed-by: Michel Dänzer
> Reviewed-by: Alex Deucher
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Reviewed-by: Rex Zhu
Best Regards
Rex Zhu
-Original Message-
From: Bradley Pankow [mailto:btpan...@gmail.com]
Sent: Tuesday, February 23, 2016 9:12 AM
To: Deucher, Alexander; Zhu, Rex; Zhou, Jammy
Cc: dri-devel at lists.freedesktop.org; linux-kernel at vger.kernel.org;
Bradley Pankow
This patch set adds a new drm driver for HiSilicon Kirin hi6220 SoC.
Current testing and support board is Hikey board which is one of Linaro
96boards. It is an arm64 open source board. For more information about
this board, please access https://www.96boards.org.
Hardware Detail
---
Add ADE display controller binding doc.
Add DesignWare DSI Host Controller v1.20a binding doc.
v5:
- Remove endpoint unit address of dsi output port.
- Add "hisilicon,noc-syscon" property for ADE NOC QoS syscon.
- Add "resets" property for ADE reset.
v4:
- Describe more specific of clocks and port
Add kirin DRM master driver for hi6220 SoC which used in HiKey board.
Add dumb buffer feature.
Add prime dmabuf feature.
v5: None.
v4: None.
v3:
- Move and rename all the files to kirin sub-directory.
So that we could separate different seires SoCs' driver.
- Replace drm_platform_init, load, unl
Add crtc funcs and helper funcs for ADE.
v5:
- Use syscon to access ADE media NOC QoS registers instread of directly
writing registers.
- Use reset controller to reset ADE instead of directly writing registers.
v4: None.
v3:
- Make ade as the master driver.
- Use port to connect with encoder.
-
Add plane funcs and helper funcs for ADE.
v5: None.
v4: None.
v3:
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 535 +++-
1 file changed, 534 insertions(+), 1 deletion(-)
diff --git a/driver
Add vblank irq handle.
v5: None.
v4: None.
v3:
- Remove hisi_get_crtc_from_index func.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 62 +
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
Add cma Fbdev, Fbdev is legency and optional, you can enable/disable it by
configuring DRM_FBDEV_EMULATION.
Add hotplug.
v5: None.
v4: None.
v3: None.
v2:
- Use CONFIG_DRM_FBDEV_EMULATION instead of CONFIG_DRM_HISI_FBDEV.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm
Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
for hi6220 SoC.
v5: None.
v4: None.
v3:
- Rename file name to dw_drm_dsi.c
- Make encoder type as DRM_MODE_ENCODER_DSI.
- A few cleanup.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
Signed-off-by: Xinwei Kong
Signed-off-
Add DesignWare dsi host driver for hi6220 SoC.
v5: None.
v4: None.
v3: None.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 50
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/hisilicon/ki
Add support for external HDMI bridge.
v5: None.
v4: None.
v3:
- Fix a typo: s/exteranl/external.
v2:
- Remove abtraction layer.
Signed-off-by: Xinliang Liu
---
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 52
1 file changed, 52 insertions(+)
diff --git a/drivers/
Add maintainer and reviewer for hisilicon DRM driver.
v5: None.
v4:
- Add Chen Feng as Designated reviewer.
v3: First version.
Signed-off-by: Xinliang Liu
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4978dc19a4d2..b94ac713916a
Add ade, dsi and adv7533 DT nodes for hikey board.
Signed-off-by: Xinliang Liu
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 40 +++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 55 ++
2 files changed, 95 insertions(+)
diff --git a/arch/arm64/b
On 15 February 2016 at 19:04, Oded Gabbay wrote:
> On Sun, Feb 14, 2016 at 2:58 PM, Daniel Vetter wrote:
>> On Sun, Feb 14, 2016 at 11:16:52AM +0200, Oded Gabbay wrote:
>>> Following Daniel's request, I spent some time removing the hard requirement
>>> that radeon and amdgpu will always appear _a
On 15 February 2016 at 19:04, Oded Gabbay wrote:
> On Sun, Feb 14, 2016 at 2:58 PM, Daniel Vetter wrote:
>> On Sun, Feb 14, 2016 at 11:16:52AM +0200, Oded Gabbay wrote:
>>> Following Daniel's request, I spent some time removing the hard requirement
>>> that radeon and amdgpu will always appear _a
On 9 February 2016 at 17:50, Daniel Vetter wrote:
> On Fri, Feb 05, 2016 at 11:10:30AM +0800, Xinliang Liu wrote:
>> This patch cleans up the Makefile of drm root directory.
>> Make core and device drivers configuration list sorted Alphabetically.
>>
>> Signed-off-by: Xinliang Liu
>> Reviewed-by:
ort->cached_edid)
> edid = drm_edid_duplicate(port->cached_edid);
> - else {
> - edid = drm_get_edid(connector, &port->aux.ddc);
> - drm_mode_connector_set_tile_property(connector);
> - }
> +
> port->has_audio = drm_detect_monitor_audio(edid);
> drm_dp_put_port(port);
> return edid;
> --
> 2.1.4
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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The default DMA mask covers a 32 bits address range, but tegradrm can
address more than that. Set the DMA mask to the actual addressable range
to avoid the use of unneeded bounce buffers.
Signed-off-by: Alexandre Courbot
---
Thierry, I am not absolutely sure whether the size is correct and applie
The current settings leaves the DRM device's dma_ops field NULL, which
makes it use the dummy DMA ops on arm64 and return an error whenever we
try to import a buffer. Call of_dma_configure() with a NULL node (since
the device is not spawn from the device tree) so that
arch_setup_dma_ops() is called
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On Tue, Feb 23, 2016 at 5:10 AM, Xinliang Liu
wrote:
> On 15 February 2016 at 19:04, Oded Gabbay wrote:
>> On Sun, Feb 14, 2016 at 2:58 PM, Daniel Vetter wrote:
>>> On Sun, Feb 14, 2016 at 11:16:52AM +0200, Oded Gabbay wrote:
Following Daniel's request, I spent some time removing the hard
On 23 February 2016 at 14:51, Oded Gabbay wrote:
> On Tue, Feb 23, 2016 at 5:10 AM, Xinliang Liu
> wrote:
>> On 15 February 2016 at 19:04, Oded Gabbay wrote:
>>> On Sun, Feb 14, 2016 at 2:58 PM, Daniel Vetter wrote:
On Sun, Feb 14, 2016 at 11:16:52AM +0200, Oded Gabbay wrote:
> Follow
Hi Simon,
Thank you for the patch.
On Tuesday 23 February 2016 10:06:12 Simon Horman wrote:
> Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.
>
> This is part of an ongoing process to migrate from ARCH_SHMOBILE to
> ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
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Hi Dave,
On Monday 22 February 2016 03:46:30 Laurent Pinchart wrote:
> Hi Dave,
>
> The following changes since commit 4c4400504f6ada0cfed682fbe7e6c65efbda3952:
>
> Merge remote-tracking branch 'linuxtv/vsp1' into HEAD (2016-02-20 02:58:43
> +0200)
>
> are available in the git repository at:
tps://lists.freedesktop.org/archives/dri-devel/attachments/20160223/14795463/attachment.html>
Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: Simon Horma
of_device_id
> platform_of_match[]
> > > = {
> > > .compatible = "lg,lb070wv8",
> > > .data = &lg_lb070wv8,
> > > }, {
> > > + .compatible = "lg,lp120up1",
> > > + .data = &lg_lp120up1,
> > > + }, {
> > > .compatible = "lg,lp129qe",
> > > .data = &lg_lp129qe,
> > > }, {
> > > --
> > > 1.7.9.5
> > >
> > >
> > > ___
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > >
>
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This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Signed-off-by: Jitao Shi
---
Changes since v10:
- Tuning PS8640 reset sleep pins squence
The following patches are needed to support dsi host through none dsi bus:
https://patchwork.kernel.org/patch/8289181/ ("drm/dsi: check
Add documentation for DT properties supported by
ps8640 DSI-eDP converter.
Signed-off-by: Jitao Shi
Acked-by: Rob Herring
Reviewed-by: Philipp Zabel
---
Chnages since v10:
- set sleep reset pin as GPIO_ACTIVE_LOW
---
.../devicetree/bindings/display/bridge/ps8640.txt | 43 ++
Hi Jitao,
[auto build test ERROR on drm/drm-next]
[also build test ERROR on v4.5-rc5 next-20160223]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Jitao-Shi/Documentation-bridge-Add
t; 16 files changed, 669 insertions(+), 81 deletions(-)
> create mode 100644 drivers/gpu/drm/drm_blend.c
>
> --
> 1.9.2
>
>
--
Benjamin Gaignard
Graphic Working Group
Linaro.org <http://www.linaro.org/> *â *Open source software for ARM SoCs
Follow *Linaro: *Facebook <http://www.facebook.com/pages/Linaro> | Twitter
<http://twitter.com/#!/linaroorg> | Blog
<http://www.linaro.org/linaro-blog/>
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e) is all about pin/signal
> numbers. Either simplify the binding to be lanes or describe the
> binding in terms of pins.
Perhaps "lane-pins" or something would be more descriptive. If we want
to make the description common, I could change the OMAP implementation
to accept the new property name too.
But, I'm not sure if a common description helps much. Any thoughts?
Tomi
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Let ipu_cpmem_set_yuv_planar_full take a DRM_FORMAT instead of a
V4L2_PIXFMT and allow better control over U/V stride, U offset and
V offset settings in the CPMEM.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-cpmem.c | 79 +++---
include/video/imx-i
The IPU addresses multiplanar formats using a base address and relative
offsets for the secondary planes. Since those offsets must be positive
and not too large, and none of the plane parameters except the base address
may be changed while scanout is active, store the pitches and u/v offsets
and ch
The driver already advertises multi-planar YUV support, but
previously the U/V offset and stride setup was missing.
Signed-off-by: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-plane.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
b/drivers/gp
https://bugzilla.kernel.org/show_bug.cgi?id=112921
Bug ID: 112921
Summary: Lock-up after screensaver on radeon
Product: Drivers
Version: 2.5
Kernel Version: 4.4
Hardware: x86-64
OS: Linux
Tree: Mainline
https://bugzilla.kernel.org/show_bug.cgi?id=112921
Jean Delvare changed:
What|Removed |Added
Regression|No |Yes
--- Comment #1 from Jean Delvare ---
https://bugzilla.kernel.org/show_bug.cgi?id=112921
--- Comment #2 from Jean Delvare ---
Created attachment 204371
--> https://bugzilla.kernel.org/attachment.cgi?id=204371&action=edit
dmesg output
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https://bugzilla.kernel.org/show_bug.cgi?id=112921
--- Comment #3 from Jean Delvare ---
Created attachment 204381
--> https://bugzilla.kernel.org/attachment.cgi?id=204381&action=edit
Xorg.0.log
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On 02/23/2016 12:57 AM, Rob Herring wrote:
> On Mon, Feb 22, 2016 at 5:07 AM, Archit Taneja
> wrote:
>>
>>
>> On 02/22/2016 08:24 AM, Rob Herring wrote:
>>>
>>> On Mon, Feb 15, 2016 at 12:23:26PM +0530, Archit Taneja wrote:
Add HDMI PHY bindings. Update the example to use HDMI PHY.
>>
Hi Tomi,
Thank you for the patch.
On Friday 19 February 2016 11:47:36 Tomi Valkeinen wrote:
> We occasionally see DISPC sync-lost errors when enabling and disabling
> HDMI. Sometimes we get only a few, which get handled (ignored) by the
> driver, but sometimes there's a flood of the errors which
Hi Tomi,
Thank you for the patch.
On Friday 19 February 2016 11:47:37 Tomi Valkeinen wrote:
> The current driver uses non-blocking DMM fill when releasing memory.
> This gives us a small performance increase as we don't have to wait for
> the fill operation to finish.
>
> However, the driver doe
On 23/02/16 00:38, Matt Roper wrote:
> On Mon, Feb 22, 2016 at 02:18:08PM +, Lionel Landwerlin wrote:
>> Implement Daniel Stone's recommendation to not read registers to infer
>> the hardware's state.
>>
>> Signed-off-by: Lionel Landwerlin
> Do we need to ensure that software and hardware stat
On 02/23/2016 02:48 PM, Tomi Valkeinen wrote:
>
> On 22/02/16 22:10, Rob Herring wrote:
>
>>> If we want all DSI host controllers to use a common binding to describe
>>> lanes, we'd need to go with the most flexible one, and the driver
>>> restricts it to the subsets that we support.
>
> True, bu
Picked it up.
Thanks,
Inki Dae
2016ë
02ì 12ì¼ 22:31ì Chanho Park ì´(ê°) ì´ ê¸:
> This patch adds a exynos5420 driver data to support mic_bypass
> option to bypass the mic from display out path.
> The mic(Mobile image compressor) compresses RGB data from fimd
> and send the compressed d
t lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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uld be private to the
driver handling the device, except for some special cases like following
the graph.
Tomi
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Tomi
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*/
Tomi
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The defconfigs for the AXS boards were updated to
enable Designware I2S driver.
Signed-off-by: Jose Abreu
---
arch/arc/configs/axs101_defconfig | 1 +
arch/arc/configs/axs103_defconfig | 1 +
arch/arc/configs/axs103_smp_defconfig | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch
ARC AXS10x platforms consist of a mainboard with several peripherals.
One of those peripherals is an HDMI output port controlled by ADV7511
transmitter.
This patch set adds audio for the ADV7511 transmitter and I2S audio for the
AXS10x platform.
Jose Abreu (4):
[adv7511] Add audio support
[a
The defconfigs for the AXS boards were updated so that
ALSA SoC is enabled and also the audio for the ADV7511
HDMI transmitter.
Signed-off-by: Jose Abreu
---
arch/arc/configs/axs101_defconfig | 3 +++
arch/arc/configs/axs103_defconfig | 5 +
arch/arc/configs/axs103_smp_defconfig | 5
HDMI audio support was added to the AXS board using an
I2S cpu driver and a custom platform driver.
The platform driver supports two channels @ 16 bits with
rates 32k, 44.1k and 48k. ALSA Simple audio card is used to
glue the cpu, platform and codec driver (adv7511).
Signed-off-by: Jose Abreu
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anything else you'd like? I'm going to mention the I provided
above too
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On Tue, Feb 23, 2016 at 5:55 AM, Christian König
wrote:
> Hi Mehul,
>
> Am 22.02.2016 um 13:28 schrieb Mehul Sawarkar:
>
> Hello,
>
> I am Mehul Sawarkar from India .I want to be part of X.Org during GSoC
> 2016.I know C/C++.Please help me getting started with some easy task you
> might have in m
This series introduces pipe level color management through a set of properties
attached to the CRTC. It also provides an implementation for some Intel
platforms.
This series is based of a previous set of patches by Shashank Sharma.
Cheers,
Lionel
Lionel Landwerlin (5):
drm/i915: Extract out g
The moves a couple of functions programming the gamma LUT and CSC
units into their own file.
On generations prior to Haswell there is only a gamma LUT. From
haswell on there is also a new enhanced color correction unit that
isn't used yet. This is why we need to set the GAMMA_MODE register,
either
Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.
v2: Read GAMMA_MODE register value at init
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_color.c | 17 +
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 1
Patch based on a previous series by Shashank Sharma.
This introduces optional properties to enable color correction at the
pipe level. It relies on 3 transformations applied to every pixels
displayed. First a lookup into a degamma table, then a multiplication
of the rgb components by a 3x3 matrix
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by CTM
v4: Update contributors
v5: Refactor degamma/
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
v3: Refactor degamma/gamma LUTs load into a single function
v4: Remove unused variable
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
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On 23/02/16 00:52, Matt Roper wrote:
> On Mon, Feb 22, 2016 at 02:18:10PM +, Lionel Landwerlin wrote:
>> Patch based on a previous series by Shashank Sharma.
>>
>> v2: Do not read GAMMA_MODE register to figure what mode we're in
>>
>> v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
>>
>
One more round to fix the last issues commented by Tomi Valkeinen.
Changes since v2:
- 09/22 "drm/tilcdc: Allocate register storage based on the actual number
registers"
- Fixed typo in the description
- 21/22 "drm/tilcdc: Initialize crtc->port"
- Changed the code to hand
From: Darren Etheridge
Updating the tilcdc DRM driver code to calculate the LCD controller
pixel clock more accurately. Based on a suggested implementation by
Tomi Valkeinen.
The current code does not work correctly and produces wrong results
with many requested clock rates. It also oddly uses t
From: Tomi Valkeinen
LCDC hardware does not support fb pitch that is different (i.e. larger)
than the screen size. The driver currently does no checks for this, and
the results of too big pitch are are flickering and lower fps.
This issue easily happens when using libdrm's modetest tool with non
From: Dave Gerlach
Update tilcdc driver to set the state of the pins to:
- "default on resume
- "sleep" on suspend
By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- minimize current leakage from pins and thus save power,
- prevent the IP from
There is nothing special about tilcdc HW when the video memory is
concerned. Just using the standard drm helpers for implementation is
enough.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drive
From: Darren Etheridge
On BeagleBone Black if no HDMI monitor is connected and suspend
is requested a kernel panic will result:
root at am335x-evm:~# echo mem > /sys/power/state
[ 65.548710] PM: Syncing filesystems ... done.
[ 65.631311] Freezing user space processes ... (elapsed 0.006 seconds)
From: Darren Etheridge
The frame_done interrupt was only being enabled when the vsync
interrupts were being enabled by DRM. However the frame_done is
used to determine if the LCD controller has successfully completed
the raster_enable, raster_disable commands and the vsync interrupts
are not alw
From: Tomi Valkeinen
Remove broken error handling. The condition for handling the
LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW could never be satisfied as the
LCDC_SYNC_LOST interrupt is not enabled. Also the requirement to have
both LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW fired at once before
handling
From: Grygorii Strashko
Fix build error when !CONFIG_CPU_FREQ
drivers/gpu/drm/tilcdc/tilcdc_drv.c: In function 'tilcdc_load':
drivers/gpu/drm/tilcdc/tilcdc_drv.c:327:1: error: label 'fail_put_clk' defined
but not used [-Werror=unused-label]
fail_put_clk:
^
Signed-off-by: Grygorii Strashko
Si
Allocate suspend/resume register storage based on the actual number
registers the driver is aware of. The static allocation for register
storage had fallen behind badly.
Reported-by: Michael Bode
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 21 -
drive
From: Tomi Valkeinen
Cleanup runtime PM handling. Before the patch the usage of pm_runtime
calls was inconsistent and hard to follow. After the update the
pm_runtime calls are removed from set_scanout() and called around
major operations that access the HW. After the patch the DPMS code does
not
From: Tomi Valkeinen
Disable crtc on unload. Call tilcdc_crtc_dpms() with DRM_MODE_DPMS_OFF
in the beginning of unload function.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 ++
1 file changed, 2 insertion
From: Tomi Valkeinen
Get rid of complex ping-pong mechanism and replace it with simpler
single buffer flipping code.
The LCDC HW appears to be designed mainly static framebuffers in
mind. There are two modes of operation, either static single buffer,
or ping pong double buffering with two static
From: Tomi Valkeinen
Split reset to a separate function and use usleep_range(250, 1000)
instead of msleep(1) to to keep the reset bit on long enough.
Signed-off-by: Tomi Valkeinen
[Added description to the patch, changed mdelay(500) to usleep_range(250, 1000)]
Signed-off-by: Jyri Sarha
---
dr
From: Tomi Valkeinen
Do not update the next frame buffer close to vertical blank. This is
to avoid situation when the frame changes between writing of
LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jy
Removes the duplicate LCDC_INT_ENABLE_SET_REG-entry in registers array.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 964e192
Use devm_kzalloc() and devm_kcalloc() for private data allocation at
driver load time.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 4 +---
drivers/gpu/drm/tilcdc/tilcdc_drv.c| 19 +++
drivers/gpu/drm/tilcdc/tilcdc_panel.c | 20 ++--
Initialize port device node pointer in the tilcdc crtc. Fixes "Falling
back to first CRTC" warning from tda998x driver.
The tda998x encoder driver calls drm_of_find_possible_crtcs() to
initialize possible_crtcs of struct drm_encoder. The crtc->port needs
to be initialized for drm_of_find_possible_
From: Darren Etheridge
The LCD controller must be deactivated and all DMA transactions stopped
when the suspend power state is entered otherwise the PRCM causes the L3
bus to get stuck in transition state.
This commit forces the lcdc to be shut down and waits for all pending DMA
transactions to
From: Tomi Valkeinen
Cleanup irq handling. Clear the irq status unconditionally and
restructure the status bit conditions.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 9 +
1 file changed, 5 inserti
Fix interrupt enable/disable code for version 2 tilcdc. In version 2
tilcdc there is a separate register for disabling interrupts. Writing
0 to enable registers bits does not have any effect. The interrupt
clear register works the same way, writing 1 to specific bit disables
the interrupt and writi
Add ratelimited prints on sync lost and FIFO underrun interrupts.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 8
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
Disable the sync lost interrupt if it fires on every frame for 50
consecutive frames in a row. This is relatively sure sign of the sync
lost interrupt being stuck and firing on every frame even if the
display otherwise appears to work OK.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilc
On Mon, Feb 22, 2016 at 02:32:32PM +0200, Oleksandr Natalenko wrote:
> Ville, Daniel,
>
> any additional info I could provide? I have to return dual-link DVI
> cable back, so let me know if I could reveal more details if necessary.
Unfortunately I'm out of ideas for now. Daniel is on vacation.
A
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