Re: [PATCH v5 08/10] accel/rocket: Add IOCTLs for synchronizing memory accesses

2025-05-30 Thread Jeff Hugo
On 5/20/2025 4:27 AM, Tomeu Vizoso wrote: The NPU cores have their own access to the memory bus, and this isn't cache coherent with the CPUs. Add IOCTLs so userspace can mark when the caches need to be flushed, and also when a writer job needs to be waited for before the buffer can be accessed f

Re: [PATCH v5 08/10] accel/rocket: Add IOCTLs for synchronizing memory accesses

2025-05-20 Thread Lucas Stach
Hi Tomeu, Am Dienstag, dem 20.05.2025 um 12:27 +0200 schrieb Tomeu Vizoso: > The NPU cores have their own access to the memory bus, and this isn't > cache coherent with the CPUs. > > Add IOCTLs so userspace can mark when the caches need to be flushed, and > also when a writer job needs to be wait