Re: [PATCH v6 15/15] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case

2025-02-21 Thread Dmitry Baryshkov
On Mon, Feb 17, 2025 at 10:16:04PM +0800, Jun Nie wrote: > To support high-resolution cases that exceed the width limitation of > a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate, > additional pipes are necessary to enable parallel data processing > within the SSPP width constr

[PATCH v6 15/15] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case

2025-02-17 Thread Jun Nie
To support high-resolution cases that exceed the width limitation of a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate, additional pipes are necessary to enable parallel data processing within the SSPP width constraints and MDP clock rate. Request 4 mixers and 4 DSCs for high-r