On Tue, 4 Jun 2024 10:44:05 +0800, kuro wrote:
> From: Kuro Chung
>
> The spec of timing between IVDD/OVDD and SYSRTEN is 10ms, but SYSRSTN RC
> circuit need at least 25ms for rising time, update for match spec
>
>
Applied, thanks!
[1/1] drm/bridge: it6505: update usleep_range for RC circuit
From: Kuro Chung
The spec of timing between IVDD/OVDD and SYSRTEN is 10ms, but SYSRSTN RC
circuit need at least 25ms for rising time, update for match spec
Signed-off-by: Kuro Chung
Signed-off-by: Hermes Wu
---
drivers/gpu/drm/bridge/ite-it6505.c | 2 +-
1 file changed, 1 insertion(+), 1 dele
