On 02/24/2016 01:34 AM, Rob Herring wrote:
> On Tue, Feb 23, 2016 at 01:11:24PM +0200, Tomi Valkeinen wrote:
>>
>>
>> On 23/02/16 12:43, Archit Taneja wrote:
>>>
>>>
>>> On 02/23/2016 02:48 PM, Tomi Valkeinen wrote:
On 22/02/16 22:10, Rob Herring wrote:
>> If we want all DSI ho
On 02/23/2016 02:48 PM, Tomi Valkeinen wrote:
>
> On 22/02/16 22:10, Rob Herring wrote:
>
>>> If we want all DSI host controllers to use a common binding to describe
>>> lanes, we'd need to go with the most flexible one, and the driver
>>> restricts it to the subsets that we support.
>
> True, bu
On Tue, Feb 23, 2016 at 01:11:24PM +0200, Tomi Valkeinen wrote:
>
>
> On 23/02/16 12:43, Archit Taneja wrote:
> >
> >
> > On 02/23/2016 02:48 PM, Tomi Valkeinen wrote:
> >>
> >> On 22/02/16 22:10, Rob Herring wrote:
> >>
> If we want all DSI host controllers to use a common binding to desc
On 23/02/16 12:43, Archit Taneja wrote:
>
>
> On 02/23/2016 02:48 PM, Tomi Valkeinen wrote:
>>
>> On 22/02/16 22:10, Rob Herring wrote:
>>
If we want all DSI host controllers to use a common binding to describe
lanes, we'd need to go with the most flexible one, and the driver
res
On 22/02/16 22:10, Rob Herring wrote:
>> If we want all DSI host controllers to use a common binding to describe
>> lanes, we'd need to go with the most flexible one, and the driver
>> restricts it to the subsets that we support.
True, but I wonder if that's necessary. The lane property for the
On Mon, Feb 22, 2016 at 1:19 AM, Archit Taneja
wrote:
>
>
> On 02/22/2016 08:23 AM, Rob Herring wrote:
>>
>> On Mon, Feb 15, 2016 at 06:30:59PM +0530, Archit Taneja wrote:
>>>
>>> The DSI driver is currently unaware of how the DSI clock and data pins
>>> are mapped to the logical lanes provided b
On 02/22/2016 08:23 AM, Rob Herring wrote:
> On Mon, Feb 15, 2016 at 06:30:59PM +0530, Archit Taneja wrote:
>> The DSI driver is currently unaware of how the DSI clock and data pins
>> are mapped to the logical lanes provided by the DSI controller.
>>
>> Use the generic 'lanes' DT binding provide
On Mon, Feb 15, 2016 at 06:30:59PM +0530, Archit Taneja wrote:
> The DSI driver is currently unaware of how the DSI clock and data pins
> are mapped to the logical lanes provided by the DSI controller.
>
> Use the generic 'lanes' DT binding provided for DSI lanes (used for DSI
> in bindings/displa
The DSI driver is currently unaware of how the DSI clock and data pins
are mapped to the logical lanes provided by the DSI controller.
Use the generic 'lanes' DT binding provided for DSI lanes (used for DSI
in bindings/display/ti/ti,omap4-dss.txt) to get the desired mapping.
The MSM DSI controlle
