On Thu, Oct 29, 2020 at 10:49:22AM +, Dave Stevenson wrote:
> On Thu, 29 Oct 2020 at 09:17, Maxime Ripard wrote:
> >
> > Hi!
> >
> > On Wed, Oct 28, 2020 at 01:42:20PM +, Dave Stevenson wrote:
> > > Hi Maxime
> > >
> > > On Fri, 25 Sep 2020 at 14:00, Maxime Ripard wrote:
> > > >
> > > > T
Hi!
On Wed, Oct 28, 2020 at 01:42:20PM +, Dave Stevenson wrote:
> Hi Maxime
>
> On Fri, 25 Sep 2020 at 14:00, Maxime Ripard wrote:
> >
> > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > per clock cycle, and cannot deal with odd timings.
> >
> > Let's reject any
On Thu, 29 Oct 2020 at 09:17, Maxime Ripard wrote:
>
> Hi!
>
> On Wed, Oct 28, 2020 at 01:42:20PM +, Dave Stevenson wrote:
> > Hi Maxime
> >
> > On Fri, 25 Sep 2020 at 14:00, Maxime Ripard wrote:
> > >
> > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> > > per cl
Hi Maxime
On Fri, 25 Sep 2020 at 14:00, Maxime Ripard wrote:
>
> The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
> per clock cycle, and cannot deal with odd timings.
>
> Let's reject any mode with such timings.
>
> Signed-off-by: Maxime Ripard
It's unsupported due to th
The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
per clock cycle, and cannot deal with odd timings.
Let's reject any mode with such timings.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 12
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 file
