[PATCH] drm/vc4: hdmi: Block odd horizontal timings

[Maxime Ripard]

The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
per clock cycle, and cannot deal with odd timings.

Let's reject any mode with such timings.

Signed-off-by: Maxime Ripard <max...@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++
 drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1c4dc774d56e..acfb4e235214 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -879,6 +879,11 @@ static int vc4_hdmi_encoder_atomic_check(struct 
drm_encoder *encoder,
        struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
        unsigned long long pixel_rate = mode->clock * 1000;
 
+       if (vc4_hdmi->variant->broken_odd_h_timings &&
+           ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
+            (mode->hsync_end % 2) || (mode->htotal % 2)))
+               return -EINVAL;
+
        if (mode->flags & DRM_MODE_FLAG_DBLCLK)
                pixel_rate *= 2;
 
@@ -901,6 +906,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
 {
        struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 
+       if (vc4_hdmi->variant->broken_odd_h_timings &&
+           ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
+            (mode->hsync_end % 2) || (mode->htotal % 2)))
+               return MODE_H_ILLEGAL;
+
        if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
                return MODE_CLOCK_HIGH;
 
@@ -1950,6 +1960,7 @@ static const struct vc4_hdmi_variant 
bcm2711_hdmi0_variant = {
                PHY_LANE_2,
                PHY_LANE_CK,
        },
+       .broken_odd_h_timings   = true,
 
        .init_resources         = vc5_hdmi_init_resources,
        .csc_setup              = vc5_hdmi_csc_setup,
@@ -1975,6 +1986,7 @@ static const struct vc4_hdmi_variant 
bcm2711_hdmi1_variant = {
                PHY_LANE_CK,
                PHY_LANE_2,
        },
+       .broken_odd_h_timings   = true,
 
        .init_resources         = vc5_hdmi_init_resources,
        .csc_setup              = vc5_hdmi_csc_setup,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index af45b0d81dec..40e51ece8efe 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -62,6 +62,9 @@ struct vc4_hdmi_variant {
         */
        enum vc4_hdmi_phy_channel phy_lane_mapping[4];
 
+       /* The BCM2711 cannot deal with odd horizontal pixel timings */
+       bool broken_odd_h_timings;
+
        /* Callback to get the resources (memory region, interrupts,
         * clocks, etc) for that variant.
         */
-- 
2.26.2

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