On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using
>> clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no
>> longer
>> used. Regmap did take care of DCU using diffe
> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>
> Since using clk_register_divider to setup the pixel clock, regmap is no longer
> used. Regmap did take care of DCU using different endianness. Check
> endianness using the device-tree property
Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.
Cc: stable at vger.kernel.org
Fixes: 2d701449bce1 ("drm/
> >>fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
> >>pix_clk_in_name, 0, base + DCU_DIV_RATIO,
> >> - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> >> + 24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> >
> > Tested-by: Meng Yi
> >
> > O
On 2016-08-22 00:13, Meng Yi wrote:
>> fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>> pix_clk_in_name, 0, base + DCU_DIV_RATIO,
>> -0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>> +24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>
> fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
> pix_clk_in_name, 0, base + DCU_DIV_RATIO,
> - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> + 24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
Tested-by: Meng Yi
On LS1021A-TW
While clk_register_divider will write register as little endian,
Modified the param "shift" from 0 to 24 since DCU is big endian.
Or reg "DCU_DIV_RATIO" will be seted as a incorrect value which
will cause vblank timing issue etc.
Signed-off-by: Meng Yi
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv
