On 2016-08-22 00:13, Meng Yi wrote:
>> fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>> pix_clk_in_name, 0, base + DCU_DIV_RATIO,
>> - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>> + 24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>
> Tested-by: Meng Yi <meng.yi at nxp.com>
>
> On LS1021A-TWR board.
Yeah I wanted to give this a try on Vybrid, but I don't think that works
since on Vybrid the IP is little endian...
We need to come up with a solution which takes that into account.
Alternatively we can put the offset into the SoC specific structure...
--
Stefan
>
>> if (IS_ERR(fsl_dev->pix_clk)) {
>> dev_err(dev, "failed to register pix clk\n");
>> ret = PTR_ERR(fsl_dev->pix_clk);
