https://bugs.freedesktop.org/show_bug.cgi?id=66384
Michel Dänzer changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #8 from Christian K?nig ---
(In reply to David Heidelberger (okias) from comment #7)
> At this moment we have working DRI3 setup (without Present for Radeon).
>
> Is there any effort to port VDPAU to DRI3?
Not yet, but it is on the
https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #7 from David Heidelberger (okias)
---
At this moment we have working DRI3 setup (without Present for Radeon).
Is there any effort to port VDPAU to DRI3?
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https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #6 from nfxjfg at gmail.com ---
Shouldn't this be responsibility of the code that implements the vdpau API?
Maybe it should attempt to remap the MSC counters to system time, and smooth
out the differences. (Sorry I don't know anything
https://bugs.freedesktop.org/show_bug.cgi?id=66384
Christian K?nig changed:
What|Removed |Added
CC||nfxjfg at gmail.com
--- Comment #5 fro
https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #4 from David "okias" Heidelberger
---
Now we have DRI3, is here some code to test? Or we should test this patch?
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https://bugs.freedesktop.org/show_bug.cgi?id=66384
Michel D?nzer changed:
What|Removed |Added
CC||david.heidelberger at ixit.cz
--- Commen
https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #2 from Michel D?nzer ---
Created attachment 83546
--> https://bugs.freedesktop.org/attachment.cgi?id=83546&action=edit
Attempt at making DRI2 MSC counter consistent between CRTCs
Here's an attempt at making the DRI2 MSC counter pe
https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #2 from Michel Dänzer ---
Created attachment 83546
--> https://bugs.freedesktop.org/attachment.cgi?id=83546&action=edit
Attempt at making DRI2 MSC counter consistent between CRTCs
Here's an attempt at making the DRI2 MSC counter pe
https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #1 from Michel D?nzer ---
I think this is because the DRI2 MSC counters differ between CRTCs, so a DRI2
buffer swap or MSC wait times out.
AFAICT it might be tricky to fix this, at least without DRI3.
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https://bugs.freedesktop.org/show_bug.cgi?id=66384
--- Comment #1 from Michel Dänzer ---
I think this is because the DRI2 MSC counters differ between CRTCs, so a DRI2
buffer swap or MSC wait times out.
AFAICT it might be tricky to fix this, at least without DRI3.
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https://bugs.freedesktop.org/show_bug.cgi?id=66384
Micha? G?rny changed:
What|Removed |Added
Hardware|Other |x86-64 (AMD64)
OS|All
https://bugs.freedesktop.org/show_bug.cgi?id=66384
Michał Górny changed:
What|Removed |Added
Hardware|Other |x86-64 (AMD64)
OS|All
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