Hi,
The driver has a few minor whitespace issues, please run through
checkpatch.pl to catch them.
Some more things inline.
On Wed, Sep 18, 2024 at 09:03:08AM +, Hui-Ping Chen wrote:
> Nuvoton MA35 SoCs NAND Flash Interface Controller
> supports 2kiB, 4kiB and 8kiB page size, and up to
> 8-bi
On Thu, Sep 05, 2024 at 04:09:58PM +0800, Andy Yan wrote:
>Hi Sascha,
>
> At 2024-09-05 15:10:56, "Sascha Hauer" wrote:
> >Hi Andy,
> >
> >On Wed, Sep 04, 2024 at 08:02:32PM +0800, Andy Yan wrote:
> >> From: Andy Yan
> >&g
Hi Andy,
On Wed, Sep 04, 2024 at 08:02:32PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> There is a version number hardcoded in the VOP VERSION_INFO
> register, and the version number increments sequentially based
> on the production order of the SOC.
>
> So using this version number to distingu
On Mon, Apr 22, 2024 at 06:19:05PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> The port mux of VP2 should be RK3568_OVL_PORT_SET__PORT2_MUX.
>
> Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
> Signed-off-by: Andy Yan
Acked-by: Sascha Hauer
Sascha
&g
d 10bit formats")
> Signed-off-by: Andy Yan
> ---
Acked-by: Sascha Hauer
Sascha
>
> drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> b/drivers/gpu/drm/rockchip
On Fri, Jan 19, 2024 at 11:08:40AM -0800, Harshit Mogalapalli wrote:
> Unlock before returning on the error path.
>
> Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
> Signed-off-by: Harshit Mogalapalli
Reviewed-by: Sascha Hauer
Thanks for fixing this.
n
> ---
Reviewed-by: Sascha Hauer
Sascha
>
> (no changes since v1)
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +-
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 2 +-
> drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 8
> 3 files changed, 6 insertions
activated modules
>
> Signed-off-by: Andy Yan
Reviewed-by: Sascha Hauer
Sascha
>
> ---
>
> Changes in v4:
> - check NULL pointer at right place
> - fix the index of fb->obj
> - drop explicitly cast of void pointer
> - make the register dump code as a common func
On Wed, Dec 06, 2023 at 06:20:58PM +0800, Andy Yan wrote:
> Hi Sascha:
>
> > > + unsigned int n = vop2->data->regs_dump_size;
> >
> > 'n' is used only once, it might be clearer just to use the value where
> > needed and drop the extra variable.
>
> Okay, will do.
> >
> > > + unsigned int i;
> >
On Tue, Dec 05, 2023 at 05:44:03PM +0800, Andy Yan wrote:
> Hi Sascha:
>
> On 12/5/23 17:29, Sascha Hauer wrote:
> > On Thu, Nov 30, 2023 at 08:24:39PM +0800, Andy Yan wrote:
> > > From: Andy Yan
> > >
> > > VOP2 on rk3588:
> > >
> >
upport
> 4 4K Esmart windows with line RGB/YUV support
>
> Signed-off-by: Andy Yan
With the two nits below feel free to add my:
Reviewed-by: Sascha Hauer
Thanks for working on this.
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
> b/drivers/gpu/drm/rockchip/rockch
On Thu, Nov 30, 2023 at 08:24:49PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> /sys/kernel/debug/dri/vop2/summary: dump vop display state
> /sys/kernel/debug/dri/vop2/regs: dump whole vop registers
> /sys/kernel/debug/dri/vop2/active_regs: only dump the registers of
> activated modules
>
> Sign
On Wed, Nov 29, 2023 at 07:01:37PM +0800, Andy Yan wrote:
> Hi Sascha:
>
>
>
> On 11/29/23 16:52, Sascha Hauer wrote:
> > On Mon, Nov 27, 2023 at 06:56:34PM +0800, Andy Yan wrote:
> > > Hi Sascha:
> > >
> > > thanks for you review.
> &
On Mon, Nov 27, 2023 at 06:56:34PM +0800, Andy Yan wrote:
>Hi Sascha:
>
>thanks for you review.
>
>On 11/27/23 18:13, Sascha Hauer wrote:
>
> On Wed, Nov 22, 2023 at 08:56:01PM +0800, Andy Yan wrote:
>
> From: Andy Yan [1]
>
> /sys/kernel/
On Wed, Nov 22, 2023 at 08:54:54PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> The vop2 need to reference more grf(system grf, vop grf, vo0/1 grf,etc)
> in the upcoming rk3588.
>
> So we rename the current system grf to sys_grf.
>
> Signed-off-by: Andy Yan
Reviewed-b
On Wed, Nov 22, 2023 at 08:54:38PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> Set overlay mode register according to the
> output mode is yuv or rgb.
>
> Signed-off-by: Andy Yan
> ---
>
> (no changes since v1)
>
> drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 +
> drivers/gpu/drm/rockch
On Wed, Nov 22, 2023 at 08:54:25PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> The enable bit and transform offset of cluster windows should be
> cleared when it work at linear mode, or we may have a iommu fault
> issue.
>
> Signed-off-by: Andy Yan
Reviewed-by:
t in
> all case.
>
> Signed-off-by: Andy Yan
Reviewed-by: Sascha Hauer
Sascha
> ---
>
> (no changes since v1)
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 25 ++--
> 1 file changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/d
quot;drm/rockchip: vop2: fix suspend/resume")
>
> Signed-off-by: Andy Yan
Reviewed-by: Sascha Hauer
Sascha
> ---
>
> (no changes since v1)
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
On Wed, Nov 22, 2023 at 08:53:49PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> The output interface related definition can shared between
> vop and vop2, move them to rockchip_drm_drv.h can avoid duplicated
> definition.
>
> Signed-off-by: Andy Yan
Reviewed-by:
Hi Andy,
Looks good overall, two small things inside.
On Wed, Nov 22, 2023 at 08:55:44PM +0800, Andy Yan wrote:
>
> +#define vop2_output_if_is_hdmi(x)(x == ROCKCHIP_VOP2_EP_HDMI0 || x ==
> ROCKCHIP_VOP2_EP_HDMI1)
> +#define vop2_output_if_is_dp(x) (x == ROCKCHIP_VOP2_EP_DP0 ||
On Wed, Nov 22, 2023 at 08:56:01PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> /sys/kernel/debug/dri/vop2/summary: dump vop display state
> /sys/kernel/debug/dri/vop2/regs: dump whole vop registers
> /sys/kernel/debug/dri/vop2/active_regs: only dump the registers of
> activated modules
>
> Sign
On Fri, Nov 17, 2023 at 03:06:35PM +0800, Andy Yan wrote:
> Hi Sebastian:
>
> On 11/16/23 21:47, Sebastian Reichel wrote:
> > Hi,
> >
> > On Thu, Nov 16, 2023 at 06:39:40PM +0800, Andy Yan wrote:
> > > > > vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
> > > > > "rockchip,gr
On Thu, Nov 16, 2023 at 03:24:54PM +0800, Andy Yan wrote:
> > case ROCKCHIP_VOP2_EP_HDMI0:
> > case ROCKCHIP_VOP2_EP_HDMI1:
> > ...
> > }
> >
> > would look a bit better overall.
> >
> > > + /*
> > > + * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate
> > > +
Hi Andy,
Thanks for your patches, some remarks inline.
On Tue, Nov 14, 2023 at 07:28:55PM +0800, Andy Yan wrote:
> From: Andy Yan
>
> VOP2 on rk3588:
>
> Four video ports:
> VP0 Max 4096x2160
> VP1 Max 4096x2160
> VP2 Max 4096x2160
> VP3 Max 2048x1080
>
> 4 4K Cluster windows with AFBC/line R
ion
> - split patch
> - add format check and convert
>
> Andy Yan (4):
> drm/rockchip: fix vop format bpp calculation
> drm/rockchip: remove the unsupported format of vop2 cluster window
> drm/rockchip: Add more format supported by vop2
> drm/rockchip: rename windows
On Fri, Oct 13, 2023 at 02:43:31PM +0800, Andy Yan wrote:
> Hi Sacha:
>
> On 10/13/23 14:11, Sascha Hauer wrote:
> > On Thu, Oct 12, 2023 at 10:37:05AM +0800, Andy Yan wrote:
> > > From: Andy Yan
> > >
> > > The cluster windows on rk3568/6 only suppor
On Thu, Oct 12, 2023 at 10:36:53AM +0800, Andy Yan wrote:
> From: Andy Yan
>
> These structs are undefined and un used.
> Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
>
> Signed-off-by: Andy Yan
Reviewed-by: Sascha Hauer
Sascha
>
>
1 insertion(+), 3 deletions(-)
Reviewed-by: Sascha Hauer
Sascha
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> index 3c524ca23d53..57c05c6b246c 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> +++ b
On Thu, Oct 12, 2023 at 10:37:05AM +0800, Andy Yan wrote:
> From: Andy Yan
>
> The cluster windows on rk3568/6 only support afbc format,
> linear format(RGB/YUV) are not supported.
> The cluster windows on rk3588 support both linear and afbc rgb
> format, but for yuv format it only support afbc.
ixes: 01e2eaf40c9d ("drm/rockchip: Convert to using
> __drm_atomic_helper_crtc_reset() for reset.")
> Signed-off-by: Jonas Karlman
Reviewed-by: Sascha Hauer
Sascha
> ---
> v2:
> - New patch
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 -
> 1 fi
ckchip: Add VOP2 driver")
> Signed-off-by: Jonas Karlman
> ---
> v2:
> - Add check for allocation failure (Sascha)
Reviewed-by: Sascha Hauer
Sascha
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 31 +---
> 1 file changed, 14 insertions(+), 17 deleti
On Tue, Jun 20, 2023 at 06:47:39AM +, Jonas Karlman wrote:
> Add missing call to crtc reset helper to properly vblank reset.
>
> Also move vop2_crtc_reset and call vop2_crtc_destroy_state to simplify
> and remove duplicated code.
>
> Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
> Sig
guard this
> with a WARN_ON() instead of crashing, so let's do that here too.
>
> Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
> Signed-off-by: Jonas Karlman
Reviewed-by: Sascha Hauer
Sascha
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8
n
Reviewed-by: Sascha Hauer
Sascha
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 16 +++-
> 1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> ind
tc_state struct.
>
> Fixes: 4e257d9eee23 ("drm/rockchip: get rid of rockchip_drm_crtc_mode_config")
> Signed-off-by: Jonas Karlman
Reviewed-by: Sascha Hauer
Sascha
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 de
On Mon, Apr 17, 2023 at 12:46:05PM +0200, Heiko Stübner wrote:
> Hi Sascha,
>
> Am Montag, 17. April 2023, 11:42:15 CEST schrieb Sascha Hauer:
> > During a suspend/resume cycle the VO power domain will be disabled and
> > the VOP2 registers will reset to their default v
w-up patch.
Fixes: afa965a45e01 ("drm/rockchip: vop2: fix suspend/resume")
Cc: sta...@vger.kernel.org
Link: https://lore.kernel.org/r/20230417094215.2049231-1-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 10 +++---
1 file changed
On Fri, Apr 14, 2023 at 04:20:10PM +0200, Paul Kocialkowski wrote:
> Hi,
>
> On Thu 13 Apr 23, 10:27, Chris Morgan wrote:
> > On Thu, Apr 13, 2023 at 04:43:47PM +0200, Sascha Hauer wrote:
> > > During a suspend/resume cycle the VO power domain will be disabled and
>
;)
Cc: sta...@vger.kernel.org
Signed-off-by: Sascha Hauer
---
Changes since v1:
- Use regcache_mark_dirty()/regcache_sync() instead of regmap_reinit_cache()
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
by re-initializing the register cache each time we
enable the VOP2. With this the VOP2 will show a picture after a
suspend/resume cycle whereas without this the screen stays dark.
Fixes: 604be85547ce4 ("drm/rockchip: Add VOP2 driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Sa
On Mon, Mar 13, 2023 at 06:08:05AM -0500, Adam Ford wrote:
> On Mon, Mar 13, 2023 at 3:51 AM Sascha Hauer wrote:
> >
> > On Sun, Mar 12, 2023 at 02:28:45PM -0500, Adam Ford wrote:
> > > I am trying to work through a series that was submitted for enabling
> > > th
On Sun, Mar 12, 2023 at 02:28:45PM -0500, Adam Ford wrote:
> I am trying to work through a series that was submitted for enabling
> the DSI on the i.MX8M Mini and Nano. I have extended this series to
> route the DSI to an HDMI bridge, and I am able to get several
> resolutions to properly sync on
On Tue, Mar 07, 2023 at 11:21:16PM +0100, Heiko Stübner wrote:
> Hi Sascha,
>
> Am Donnerstag, 16. Februar 2023, 11:24:44 CET schrieb Sascha Hauer:
> > The different VOP variants support different maximum resolutions. Reject
> > resolutions that are not supported
ister values for mpll_cfg
> - Add patch to discard modes we cannot achieve
>
> Changes since v1:
> - Allow non standard clock rates only on Synopsys phy as suggested by
> Robin Murphy
>
> Sascha Hauer (4):
> drm/rockchip: vop: limit maximium resolution to hardware capabil
Tested-by: Michael Riesch
Tested-by: Dan Johansen
Link: https://lore.kernel.org/r/20230118132213.2911418-4-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v3:
- only check for rate when clk != NULL
Changes since v2:
- new patch
drivers/gpu/drm
ed by all VOP variants. Now with higher resolutions
supported in the HDMI driver we have to limit the resolutions to the
ones supported by the VOP.
The actual maximum resolutions are taken from the Rockchip downstream
Kernel.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v5:
Link: https://lore.kernel.org/r/20230118132213.2911418-3-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v2:
- Use correct mpll_cfg values, previously the 420 values were used
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8
1 file changed, 8 insertions
non standard clock rates only on Synopsys phy as suggested by
Robin Murphy
Sascha Hauer (4):
drm/rockchip: vop: limit maximium resolution to hardware capabilities
drm/rockchip: dw_hdmi: relax mode_valid hook
drm/rockchip: dw_hdmi: Add support for 4k@30 resolution
drm/rockchip: dw_hdmi
work
with non standard clock rates.
Tested-by: Michael Riesch
Link: https://lore.kernel.org/r/20220926080435.259617-2-s.ha...@pengutronix.de
Tested-by: Nicolas Frattaroli
Tested-by: Dan Johansen
Link: https://lore.kernel.org/r/20230118132213.2911418-2-s.ha...@pengutronix.de
Signed-off-by: Sascha
ion
doesn't do. Now my "userspace" is in kernel and the kernel shouldn't try
to solve this problem. We're trapped :-/
Sascha
>
> --
> FUKAUMI Naoki
>
> On 2/8/23 18:08, Sascha Hauer wrote:
> > Some more small changes to this series, see changelog.
values for mpll_cfg
- Add patch to discard modes we cannot achieve
Changes since v1:
- Allow non standard clock rates only on Synopsys phy as suggested by
Robin Murphy
Sascha Hauer (4):
drm/rockchip: vop: limit maximium resolution to hardware capabilities
drm/rockchip: dw_hdmi: relax
Tested-by: Michael Riesch
Tested-by: Dan Johansen
Link: https://lore.kernel.org/r/20230118132213.2911418-4-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v3:
- only check for rate when clk != NULL
Changes since v2:
- new patch
drivers/gpu/drm
ed by all VOP variants. Now with higher resolutions
supported in the HDMI driver we have to limit the resolutions to the
ones supported by the VOP.
The actual maximum resolutions are taken from the Rockchip downstream
Kernel.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v4:
work
with non standard clock rates.
Tested-by: Michael Riesch
Link: https://lore.kernel.org/r/20220926080435.259617-2-s.ha...@pengutronix.de
Tested-by: Nicolas Frattaroli
Tested-by: Dan Johansen
Link: https://lore.kernel.org/r/20230118132213.2911418-2-s.ha...@pengutronix.de
Signed-off-by: Sascha
Link: https://lore.kernel.org/r/20230118132213.2911418-3-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v2:
- Use correct mpll_cfg values, previously the 420 values were used
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8
1 file changed, 8 insertions
On Tue, Feb 07, 2023 at 11:01:26AM +, Jonas Karlman wrote:
> Hi Sascha,
>
> On 2023-02-07 09:44, Sascha Hauer wrote:
> > The Rockchip PLL drivers are currently table based and support only
> > the most common pixelclocks. Discard all modes we cannot achieve
> > a
On Tue, Feb 07, 2023 at 10:46:49AM +, Jonas Karlman wrote:
> Hi Sascha,
> On 2023-02-07 09:44, Sascha Hauer wrote:
> > The different VOP variants support different maximum resolutions. Reject
> > resolutions that are not supported by a specific variant.
> >
> >
On Tue, Feb 07, 2023 at 10:16:57AM +0100, Dan Johansen wrote:
>
> Den 07.02.2023 kl. 09.44 skrev Sascha Hauer:
> > The different VOP variants support different maximum resolutions. Reject
> > resolutions that are not supported by a specific variant.
> >
> > Thi
Tested-by: Michael Riesch
Tested-by: Dan Johansen
Link: https://lore.kernel.org/r/20230118132213.2911418-4-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
Link: https://lore.kernel.org/r/20230118132213.2911418-3-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
b/drivers/gpu/drm/rockchip/dw_hdmi
ed by all VOP variants. Now with higher resolutions
supported in the HDMI driver we have to limit the resolutions to the
ones supported by the VOP.
The actual maximum resolutions are taken from the Rockchip downstream
Kernel.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v3:
Changes since v2:
- Use correct register values for mpll_cfg
- Add patch to discard modes we cannot achieve
Changes since v1:
- Allow non standard clock rates only on Synopsys phy as suggested by
Robin Murphy
Sascha Hauer (4):
drm/rockchip: vop: limit maximium resolution to hardware
work
with non standard clock rates.
Tested-by: Michael Riesch
Link: https://lore.kernel.org/r/20220926080435.259617-2-s.ha...@pengutronix.de
Tested-by: Nicolas Frattaroli
Tested-by: Dan Johansen
Link: https://lore.kernel.org/r/20230118132213.2911418-2-s.ha...@pengutronix.de
Signed-off-by: Sascha
On Mon, Feb 06, 2023 at 03:04:48PM +0100, Sascha Hauer wrote:
> On Wed, Feb 01, 2023 at 09:23:56AM +0900, FUKAUMI Naoki wrote:
> > hi,
> >
> > I'm trying this patch series with 6.1.x kernel. it works fine on rk356x
> > based boards (ROCK 3), but it has a
On Wed, Feb 01, 2023 at 09:23:56AM +0900, FUKAUMI Naoki wrote:
> hi,
>
> I'm trying this patch series with 6.1.x kernel. it works fine on rk356x
> based boards (ROCK 3), but it has a problem on rk3399 boards (ROCK 4).
>
> on rk3399 with this patch, I can see large noise area (about one third righ
low the higher
resolutions on RK3568 where we know it works.
Sascha
>
> --
> FUKAUMI Naoki
>
> On 1/31/23 17:09, Sascha Hauer wrote:
> > Heiko, Sandy,
> >
> > Ok to apply these patches?
> >
> > Sascha
> >
> > On Wed, Jan 18, 2023 at
Heiko, Sandy,
Ok to apply these patches?
Sascha
On Wed, Jan 18, 2023 at 02:22:10PM +0100, Sascha Hauer wrote:
> It's been some time since I last sent this series. This version fixes
> a regression Dan Johansen reported. The reason turned out to be simple,
> I used the YUV420 r
On Tue, Jan 24, 2023 at 06:47:00AM +0100, Michael Riesch wrote:
> Hi all,
>
> This series adds support for the RGB output block that can be found in the
> Rockchip Video Output Processor (VOP) 2. Version 2 of this series
> incorporates the feedback by Dan Carpenter and Sascha H
On Thu, Jan 19, 2023 at 09:48:03PM +0300, Alibek Omarov wrote:
> One of the ports of RK3568 can be configured as LVDS, re-using the DSI DPHY
>
> Signed-off-by: Alibek Omarov
> ---
> drivers/gpu/drm/rockchip/rockchip_lvds.c | 144 +--
> drivers/gpu/drm/rockchip/rockchip_lvds.h
Hi Michael,
On Thu, Jan 19, 2023 at 03:39:10PM +0100, Michael Riesch wrote:
> The Rockchip VOP2 features an internal RGB output block, which can be
> attached to the video port 2 of the VOP2. Add support for this output
> block.
>
> Signed-off-by: Michael Riesch
> ---
> v2:
> - move away from w
The Rockchip PLL drivers are currently table based and support only
the most common pixelclocks. Discard all modes we cannot achieve
at all. Normally the desired pixelclocks have an exact match in the
PLL driver, nevertheless allow for a 0.1% error just in case.
Signed-off-by: Sascha Hauer
This adds the PLL/phy settings to support higher resolutions like 4k@30.
The values were taken from the Rockchip downstream Kernel.
Tested-by: Michael Riesch
Link: https://lore.kernel.org/r/20220926080435.259617-3-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
Notes:
Changes since
work
with non standard clock rates.
Tested-by: Michael Riesch
Link: https://lore.kernel.org/r/20220926080435.259617-2-s.ha...@pengutronix.de
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 26 +++--
1 file changed, 19 insertions(+), 7 deletions
able modes.
Sascha
Changes since v2:
- Use correct register values for mpll_cfg
- Add patch to discard modes we cannot achieve
Changes since v1:
- Allow non standard clock rates only on Synopsys phy as suggested by
Robin Murphy
Sascha Hauer (3):
drm/rockchip: dw_hdmi: relax mode_valid
On Wed, Nov 30, 2022 at 03:02:16PM +0100, Michael Riesch wrote:
> The Rockchip VOP2 features an internal RGB output block, which can be
> attached to the video port 2 of the VOP2. Add support for this output
> block.
>
> Signed-off-by: Michael Riesch
> ---
> drivers/gpu/drm/rockchip/rockchip_drm
On Wed, Nov 30, 2022 at 03:02:13PM +0100, Michael Riesch wrote:
> Commit 540b8f271e53 ("drm/rockchip: Embed drm_encoder into
> rockchip_decoder") provides the means to pass the endpoint ID to the
> VOP2 driver, which sets the interface MUX accordingly. However, this
> step has not yet been carried
On Wed, Oct 05, 2022 at 12:51:57PM +0200, Dan Johansen wrote:
>
> Den 05.10.2022 kl. 12.06 skrev Sascha Hauer:
> > On Wed, Sep 28, 2022 at 10:39:27AM +0200, Dan Johansen wrote:
> > > Den 28.09.2022 kl. 10.37 skrev Sascha Hauer:
> > > > On Tue, Sep 27, 2022 at 07:
On Wed, Sep 28, 2022 at 10:39:27AM +0200, Dan Johansen wrote:
>
> Den 28.09.2022 kl. 10.37 skrev Sascha Hauer:
> > On Tue, Sep 27, 2022 at 07:53:54PM +0200, Dan Johansen wrote:
> > > Den 26.09.2022 kl. 12.30 skrev Michael Riesch:
> > > > Hi Sascha,
> > >
On Tue, Sep 27, 2022 at 07:53:54PM +0200, Dan Johansen wrote:
>
> Den 26.09.2022 kl. 12.30 skrev Michael Riesch:
> > Hi Sascha,
> >
> > On 9/26/22 10:04, Sascha Hauer wrote:
> > > This series adds support for 4k@30 to the rockchip HDMI controller. This
> &g
On Thu, Sep 15, 2022 at 10:13:44AM -0500, Chris Morgan wrote:
> On Wed, Sep 14, 2022 at 03:35:30PM +0200, Sascha Hauer wrote:
> > On Wed, Sep 14, 2022 at 08:04:18AM -0500, Chris Morgan wrote:
> > > On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote:
> > > >
[] array cannot not be used due to hardware
limitations, so without this patch we end up with CRTCs without primary
planes when multiple VPs are active.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
work
with non standard clock rates.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v1:
- Allow non standard clock rates only for the Synopsys phy and stick the
vendor specific phys to current behaviour.
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 26 +++--
1
This adds the PLL/phy settings to support higher resolutions like 4k@30.
The values were taken from the Rockchip downstream Kernel.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/rockchip
first step.
Sascha
Changes since v1:
- Allow non standard clock rates only on Synopsys phy as suggested by
Robin Murphy
Sascha Hauer (2):
drm/rockchip: dw_hdmi: relax mode_valid hook
drm/rockchip: dw_hdmi: Add support for 4k@30 resolution
On Wed, Sep 14, 2022 at 08:04:18AM -0500, Chris Morgan wrote:
> On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote:
> > On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote:
> > > Hi,
> > >
> > > On 9/12/22 20:02, Chris Morgan wrote:
> &g
On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote:
> Hi,
>
> On 9/12/22 20:02, Chris Morgan wrote:
> > From: Chris Morgan
>
> Cc: Sascha -> any thoughts on this one?
>
> Best regards,
> Michael
>
> > If I use more than one VP to output on an RK3566 based device I
> > receive the f
On Wed, Aug 24, 2022 at 05:07:50PM +0100, Robin Murphy wrote:
> On 2022-08-22 16:20, Sascha Hauer wrote:
> > The driver checks if the pixel clock of the given mode matches an entry
> > in the mpll config table. The frequencies in the mpll table are meant as
> > a frequency
On Wed, Aug 24, 2022 at 07:43:03AM +0200, Michael Riesch wrote:
> Hi Sascha,
>
> Can you Cc: linux-rockchip list to get more feedback?
Yes, will do that next time.
>
> On 8/22/22 17:20, Sascha Hauer wrote:
> > This series adds support for 4k@30 to the rockchip HDMI con
Hi Andy Et al.,
On Mon, Aug 22, 2022 at 05:20:15PM +0200, Sascha Hauer wrote:
> This series adds support for 4k@30 to the rockchip HDMI controller. This
> has been tested on a rk3568 rock3a board. It should be possible to add
> 4k@60 support the same way, but it doesn't work for me
This series adds support for 4k@30 to the rockchip HDMI controller. This
has been tested on a rk3568 rock3a board. It should be possible to add
4k@60 support the same way, but it doesn't work for me, so let's add
4k@30 as a first step.
Sascha
Sascha Hauer (2):
drm/rockchip: dw_h
of the mpll frequencies to allow for more display
resolutions.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
b/drivers/gpu/drm/rockchip/dw_hdmi
This adds the PLL/phy settings to support higher resolutions like 4k@30.
The values were taken from the Rockchip downstream Kernel.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/rockchip
The hsync/vsync polarities were not honoured for the eDP and HDMI ports.
Add the register settings to configure the polarities as requested by the
DRM_MODE_FLAG_PHSYNC/DRM_MODE_FLAG_PVSYNC flags.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4
1 file
Hi Maya,
On Fri, May 20, 2022 at 12:02:33PM +0200, Maya Matuszczyk wrote:
> Hello,
>
> wt., 17 maj 2022 o 20:28 Heiko Stuebner napisał(a):
> >
> > Am Freitag, 22. April 2022, 09:28:17 CEST schrieb Sascha Hauer:
> > > It's v11 time. There's only one
Heiko,
On Mon, May 16, 2022 at 10:12:26AM -0500, Rob Herring wrote:
> On Wed, 11 May 2022 10:21:07 +0200, Sascha Hauer wrote:
> > The VOP2 driver relies on reg-names properties, but these are not
> > documented. Add the missing documentation, make reg-names mandatory
> > and
looking
"gamma-lut".
Changes since v1:
- Fix dt_binding_check errors
Sascha Hauer (3):
dt-bindings: display: rockchip: make reg-names mandatory for VOP2
drm: rockchip: Change register space names
arm64: dts: rockchip: rk356x: Change VOP2 register space names
.../bindings/display/
"regs" seems to generic when there are multiple register spaces, so
rename to "vop". Also, replace "gamma_lut" with better looking
"gamma-lut". This has been changed in the driver and binding
documentation as well.
Signed-off-by: Sascha Hauer
---
arch
"regs" seems to generic when there are multiple register spaces, so
rename that one to "vop". Also change "gamma_lut" to better looking
"gamma-lut".
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++--
1 file changed, 2 i
The VOP2 driver relies on reg-names properties, but these are not
documented. Add the missing documentation, make reg-names mandatory
and increase minItems to 2 as always both register spaces are needed.
Signed-off-by: Sascha Hauer
---
Notes:
Changes since v1:
- Drop minItems
- Add
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