On Fri, May 28, 2021 at 11:30:35PM +0300, Roman Stratiienko wrote:
> Create callback to allow updating engine's registers on mode change.
>
> Signed-off-by: Roman Stratiienko
> Reviewed-by: Jernej Skrabec
> ---
> drivers/gpu/drm/sun4i/sun4i_crtc.c | 3 +++
> drivers/gpu/drm/sun4i/sunxi_engin
On Mon, Jan 21, 2019 at 07:13:07PM +0100, Jernej Škrabec wrote:
> Dne ponedeljek, 21. januar 2019 ob 14:34:33 CET je Priit Laes napisal(a):
> > On Mon, Jan 21, 2019 at 08:37:29AM +0000, Priit Laes wrote:
> > > On Fri, Jan 18, 2019 at 10:51:10PM +0100, Jernej Škrabec wrote:
>
From: Priit Laes
Even though HDMI connector features hotplug detect pin (HPD), there
are older devices which do not support it. For these devices fall
back to additional check on I2C bus to probe for EDID data.
One known example is HDMI/DVI display with following edid:
$ xxd -p display.edid
On Thu, Feb 14, 2019 at 09:09:51PM -0800, Vasily Khoruzhick wrote:
> From: Icenowy Zheng
>
> The ANX6345 is an ultra-low power DisplayPower/eDP transmitter designed
> for portable devices. This driver adds initial support for RGB to eDP
> mode, without HPD and interrupts.
>
> This is a configura
From: Priit Laes
Even though HDMI connector features hotplug detect pin (HPD), there
are older devices which do not support it. For these devices fall
back to additional check on I2C bus to probe for EDID data.
One known example is HDMI/DVI display with following edid:
$ xxd -p display.edid
On Mon, Jan 21, 2019 at 02:25:17PM +0100, Maxime Ripard wrote:
> On Fri, Jan 18, 2019 at 02:51:26PM +0000, Priit Laes wrote:
> > On Fri, Jan 18, 2019 at 03:04:18PM +0100, Maxime Ripard wrote:
> > > On Fri, Jan 18, 2019 at 10:10:53AM +, Priit Laes wrote:
> > >
From: Priit Laes
Although TMDS clock is required for HDMI to properly function,
nobody called clk_prepare_enable(). This fixes reference counting
issues and makes sure clock is running when it needs to be running.
Due to TDMS clock being parent clock for DDC clock, TDMS clock
was turned on/off
On Mon, Jan 21, 2019 at 08:37:29AM +, Priit Laes wrote:
> On Fri, Jan 18, 2019 at 10:51:10PM +0100, Jernej Škrabec wrote:
> > Dne četrtek, 17. januar 2019 ob 08:24:02 CET je Priit Laes napisal(a):
> > > On Wed, Jan 16, 2019 at 06:00:32PM +0100, Jernej Škrabec wrote:
>
On Fri, Jan 18, 2019 at 10:51:10PM +0100, Jernej Škrabec wrote:
> Dne četrtek, 17. januar 2019 ob 08:24:02 CET je Priit Laes napisal(a):
> > On Wed, Jan 16, 2019 at 06:00:32PM +0100, Jernej Škrabec wrote:
> > > Dne sreda, 16. januar 2019 ob 13:09:58 CET je Priit Laes napisal(
On Thu, Jan 17, 2019 at 12:33:40PM +0100, Maxime Ripard wrote:
> On Wed, Jan 16, 2019 at 08:35:16PM +0000, Priit Laes wrote:
> > On Wed, Jan 16, 2019 at 08:24:42PM +0100, Maxime Ripard wrote:
> > > Hi Priit,
> > >
> > > On Wed, Jan 16, 2019 at 07:58:54AM +
On Fri, Jan 18, 2019 at 03:04:18PM +0100, Maxime Ripard wrote:
> On Fri, Jan 18, 2019 at 10:10:53AM +0000, Priit Laes wrote:
> > > > > > > It doesn't look related to the clock rate itself, since it doesn't
> > > > > > > change be
On Wed, Jan 16, 2019 at 06:00:32PM +0100, Jernej Škrabec wrote:
> Dne sreda, 16. januar 2019 ob 13:09:58 CET je Priit Laes napisal(a):
> > On Thu, Jan 10, 2019 at 06:10:59PM +0100, Jernej Škrabec wrote:
> > > Dne četrtek, 10. januar 2019 ob 10:15:48 CET je Priit Laes napisal(
On Thu, Jan 10, 2019 at 06:10:59PM +0100, Jernej Škrabec wrote:
> Dne četrtek, 10. januar 2019 ob 10:15:48 CET je Priit Laes napisal(a):
> > On Sun, Nov 04, 2018 at 07:26:39PM +0100, Jernej Skrabec wrote:
> > > Currently MP clocks don't consider adjusting parent rate even if
On Wed, Jan 16, 2019 at 08:24:42PM +0100, Maxime Ripard wrote:
> Hi Priit,
>
> On Wed, Jan 16, 2019 at 07:58:54AM +0000, Priit Laes wrote:
> > > On Mon, Jan 14, 2019 at 01:29:34PM +, Priit Laes wrote:
> > > > I have a somewhat curious case with one HDMI/DV
Jan 14, 2019 at 01:29:34PM +, Priit Laes wrote:
> > I have a somewhat curious case with one HDMI/DVI screen that fails
> > to initialize properly every 6-7 boots. The display itself is also
> > somewhat flawed (missing HPD pin and the VSYNC/HSYNC pulse width
> > is set to 0
On Sun, Nov 04, 2018 at 07:26:39PM +0100, Jernej Skrabec wrote:
> Currently MP clocks don't consider adjusting parent rate even if they
> are allowed to do so. Such behaviour considerably lowers amount of
> possible rates, which is very inconvenient when such clock is used for
> pixel clock, for ex
On Tue, Nov 20, 2018 at 09:58:41AM +0100, Maxime Ripard wrote:
> On Mon, Nov 19, 2018 at 10:26:38AM +, Russell King - ARM Linux wrote:
> > On Mon, Nov 19, 2018 at 09:19:34AM +0100, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Fri, Nov 16, 2018 a
On Mon, Nov 19, 2018 at 09:19:34AM +0100, Maxime Ripard wrote:
> Hi,
>
> On Fri, Nov 16, 2018 at 07:18:29PM +0200, Priit Laes wrote:
> > From: Priit Laes
> >
> > Even though HDMI connector features hotplug detect pin (HPD), there are
> > devices that which do n
From: Priit Laes
Even though HDMI connector features hotplug detect pin (HPD), there are
devices that which do not support it. For these devices fall back to
additional check on I2C bus. Of course, there might be also devices
that do not wire DDC pins too, so we don't really know whether
On Sat, Nov 03, 2018 at 03:38:51PM +0530, Jagan Teki wrote:
> Loop N1 instruction delay for burst mode lcd panel are
> computed as per BSP code.
>
> Reference code is available in BSP
> (in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
> dsi_dev[sel]->dsi_inst_loop_num.bits.loop_n1
On Sat, Oct 27, 2018 at 03:25:29PM +0530, Jagan Teki wrote:
> On Fri, Oct 26, 2018 at 9:43 PM Priit Laes wrote:
> >
> > On Fri, Oct 26, 2018 at 08:13:39PM +0530, Jagan Teki wrote:
> > > Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
> > > L
On Fri, Oct 26, 2018 at 08:13:39PM +0530, Jagan Teki wrote:
> Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
> LCD panel. Add panel driver for it.
>
> Signed-off-by: Jagan Teki
> Tested-by: Jagan Teki
> ---
> Changes for v3:
> - new patch
> Changes for v2:
> - none
>
> drivers/gpu
On Thu, Dec 07, 2017 at 04:58:45PM +0100, Maxime Ripard wrote:
> Hi,
>
> Here is an attempt at supporting the LVDS output in our DRM driver. This
> has been tested on the A83T (with DE2), but since everything is basically
> in the TCON, it should also be usable on the older SoCs with minor
> modif
On Tue, Oct 17, 2017 at 11:06:22AM +0200, Maxime Ripard wrote:
> The TCON supports the LVDS interface to output to a panel or a bridge.
> Let's add support for it.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/Makefile | 1 +-
> drivers/gpu/drm/sun4i/sun4i_lvds.c | 183 +++
On Tue, Oct 17, 2017 at 11:06:22AM +0200, Maxime Ripard wrote:
> The TCON supports the LVDS interface to output to a panel or a bridge.
> Let's add support for it.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/Makefile | 1 +-
> drivers/gpu/drm/sun4i/sun4i_lvds.c | 183 +++
On Mon, 2017-02-13 at 17:20 +0800, Chen-Yu Tsai wrote:
> On Mon, Feb 13, 2017 at 5:16 PM, Maxime Ripard
> wrote:
> > Hi,
> >
> > On Sat, Feb 11, 2017 at 07:43:59PM +0200, Priit Laes wrote:
> > > Added basic display pipeline consisting of tcon, display backen
Added basic display pipeline consisting of tcon, display backend and
frontend blocks.
Signed-off-by: Priit Laes
---
arch/arm/boot/dts/sun4i-a10.dtsi | 104 +++
1 file changed, 104 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot
Depending on the output type, we have to enable/disable some
bits conditionally.
Signed-off-by: Priit Laes
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.h | 3 ++-
3 files changed, 5 insertions(+), 3 deletions
TODO: We still rely on u-boot for lvds reset bit setup :(
Signed-off-by: Priit Laes
---
drivers/gpu/drm/sun4i/sun4i_lvds.c | 29
drivers/gpu/drm/sun4i/sun4i_tcon.c | 54 --
drivers/gpu/drm/sun4i/sun4i_tcon.h | 15 +++
3 files
From: Jonathan Liu
Signed-off-by: Jonathan Liu
---
arch/arm/configs/sunxi_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index da92c25..7abe6a4 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/con
Signed-off-by: Priit Laes
---
arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 95 +---
1 file changed, 86 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
index 9616cde..c19f906 100644
--- a
Add simple-panel support for the LG LP097x02-slq2, which is 10"
1024x768 LVDS panel.
Signed-off-by: Priit Laes
---
drivers/gpu/drm/panel/panel-simple.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/
Signed-off-by: Priit Laes
---
drivers/gpu/drm/sun4i/Makefile | 1 +
drivers/gpu/drm/sun4i/sun4i_lvds.c | 247 +
drivers/gpu/drm/sun4i/sun4i_lvds.h | 15 +++
3 files changed, 263 insertions(+)
create mode 100644 drivers/gpu/drm/sun4i/sun4i_lvds.c
properly set up LVDS reset controller.
---
Jonathan Liu (1):
ARM: sunxi_defconfig: Enable simple panel
Priit Laes (7):
ARM: sun4i: Add display blocks for the sun4i dtsi.
drm/panel: simple: Add support for LG LP097x02-slq2 panel
drm/sun4i: Add optional 'mode' property to TCON
drm/
Add variable to enable either 'rgb' or 'lvds' output.
Signed-off-by: Priit Laes
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
b/Docu
On Wed, 2016-05-11 at 15:15 -0700, Stephen Boyd wrote:
> On 05/10, Priit Laes wrote:
> >
> > On Mon, 2016-05-09 at 15:39 -0700, Stephen Boyd wrote:
> > >
> > > On 05/09, Stephen Boyd wrote:
> > > >
> > > >
> > > >
> >
On Mon, 2016-05-09 at 15:39 -0700, Stephen Boyd wrote:
> On 05/09, Stephen Boyd wrote:
> >
> >
> > Ok I applied this one to clk-next.
> >
> And I squashed this in to silence the following checker warning.
>
> drivers/clk/sunxi/clk-sun4i-display.c:110:33: warning: Variable
> length array is used
On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> Hi everyone,
>
> The Allwinner SoCs (except for the very latest ones) all share the
> same set of controllers, loosely coupled together to form the display
> pipeline.
>
> Depending on the SoC, the number of instances of the controller wil
On Sat, 2016-01-16 at 17:11 +0200, Priit Laes wrote:
> On Thu, 2016-01-14 at 16:24 +0100, Maxime Ripard wrote:
> > The Allwinner A10 and subsequent SoCs share the same display
> > pipeline, with
> > variations in the number of controllers (1 or 2), or the presence
> >
; + */
> +
> +#include
> +#include
> +#include
> +
> +#include "sun4i_drv.h"
> +
> +static void sun4i_de_output_poll_changed(struct drm_device *drm)
> +{
> + struct sun4i_drv *drv = drm->dev_private;
> +
> + if (drv->fbdev)
> + drm_fbdev_cma_hotplug_event(drv->fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs sun4i_de_mode_config_funcs
> = {
> + .output_poll_changed= sun4i_de_output_poll_changed,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> + .fb_create = drm_fb_cma_create,
> +};
> +
> +struct drm_fbdev_cma *sun4i_framebuffer_init(struct drm_device *drm)
> +{
> + drm_mode_config_reset(drm);
> +
> + drm->mode_config.max_width = 8192;
> + drm->mode_config.max_height = 8192;
Shouldn't these be 1920 x 1080 as per A10 User manual?
> +
> + drm->mode_config.funcs = &sun4i_de_mode_config_funcs;
> +
> + return drm_fbdev_cma_init(drm, 32,
> + Â Â drm->mode_config.num_crtc,
> + Â Â drm->mode_config.num_connector);
> +}
> +
> +void sun4i_framebuffer_free(struct drm_device *drm)
> +{
> + struct sun4i_drv *drv = drm->dev_private;
> +
> + drm_fbdev_cma_fini(drv->fbdev);
> + drm_mode_config_cleanup(drm);
> +}
[...]
Päikest,
Priit Laes :)
property_read_string(node, "clock-output-names", &clk_name);
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n", clk_name);
> + return;
> + }
...
Thanks for working on this feature ;)
Päikest,
Priit Laes
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