it: 1300a7f8a7d4c5f88de30312cf34448b96539c23
[2/2] drm/imagination: Add reset controller support for GPU initialization
commit: 3a2b7389feea9a7afd18d58cda59b7a989445f38
Best regards,
--
Matt Coster
ion: avoid unused-const-variable warning
commit: 3206a96675342badb0254558ba4b4c8764aa3ae7
Best regards,
--
Matt Coster
e haven't always
made it easy for you!
This series (sub-series?) is:
Reviewed-by: Matt Coster
If nobody has any objections, I'll apply it to drm-misc-next tomorrow.
Cheers,
Matt
>
> [1] -
> https://lore.kernel.org/all/20250414-apr_14_for_sending-v2-0-70c5a
like
enough of my concerns were due solely to my ignorance that I'd rather
just take this patch as-is than spend time reworking it. (Thanks to Jani
and Andi for filling gaps in my knowledge too!)
To that end,
Reviewed-by: Matt Coster
And I'll take this through drm-misc-next tomorrow
nge in the DT bindings,
> doesn’t appear to conflict with the work you're doing for Rogue series
> enablement.
Agreed, it still applies cleanly on top of drm-misc-next after we landed
the BXS series.
>
> Would you prefer if I re-send them as a mini-series so you can consid
On 10/04/2025 10:55, Matt Coster wrote:
> Use the new compatible string introduced earlier (in "dt-bindings: gpu:
> img: More explicit compatible strings") and add a name to the single power
> domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
&
if (err)
>> +return err;
>> +}
>
> So, how does that work for devfreq? I can understand the rationale for
> resets and the sys clock, but the core clock at least should really be
> handled by the driver.
I agree, this feels a bit "all or nothing
On 01/04/2025 17:45, Michal Wilczynski wrote:
> On 3/26/25 17:48, Matt Coster wrote:
>> The first compatible strings added for the AXE-1-16M are not sufficient to
>> accurately describe all the IMG Rogue GPUs. The current "img,img-axe"
>> string refers to the entire
). That patch adds the function pvr_vm_unmap_obj()
which is used here.
[1]:
https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded2...@imgtec.com
Signed-off-by: Sarah Walker
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank'
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
different GPU power
topologies.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-5-e4c46e828...@imgtec.com
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Move loop variable as per
https
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
Reviewed-by
Use the new compatible string introduced earlier (in "dt-bindings: gpu:
img: More explicit compatible strings") and add a name to the single power
domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
details").
Signed-off-by: Matt Coster
---
Changes in v6:
memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-15-e4c4
errogated from the device at runtime,
we can match on the generic "img,img-rogue" and avoid adding more entries
with NULL data members (barring hardware quirks).
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kern
ard
declaration down here. Can you move it up to the top of the file with
the others?
>
> @@ -73,6 +72,5 @@ void pvr_fw_trace_mask_update(struct pvr_device *pvr_dev,
> u32 old_mask,
> u32 new_mask);
>
> void pvr_fw_trace_debugfs_init(struct pvr_device *pvr_dev, struct dentry
> *dir);
> -#endif /* defined(CONFIG_DEBUG_FS) */
Having said that, surely it makes sense to keep at least
*_debugfs_init() gated behind CONFIG_DEBUG_FS?
>
> #endif /* PVR_FW_TRACE_H */
--
Matt Coster
E: matt.cos...@imgtec.com
OpenPGP_signature.asc
Description: OpenPGP digital signature
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20
o not have
an equivalent register.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-8-e4c46e828...@imgtec.com
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/2025
- Use normal reg syntax for 64-bit values (P8/P21)
- Link to v1:
https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865...@imgtec.com
---
Alessio Belle (3):
drm/imagination: Update register defs for newer GPUs
drm/imagination: Mask GPU IRQs in threaded handler
d
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add
[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel
[2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html
[3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Signed-off-by: Matt Coster
---
Changes in v6:
- None
- Link to v5:
https://lore.ke
-to-be-added RISC-V firmware
processors cannot be masked in hardware. This change allows us to continue
using the threaded handler in GPUs with a RISC-V firmware.
For simplicity, the same approach is taken for all firmware processors.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-12-e4c4
Unlike AXE-1-16M, BXS-4-64 uses two power domains.
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.
Signed-off-by: Matt Coster
Reviewed-by: Krzysztof Kozlowski
---
Changes in v6:
- Add Krzysztof's Rb
- Link to v5:
https://lore.kerne
From: Alessio Belle
Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/202
Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.
Signed-off-by: Matt Coster
Reviewed-by: Frank Binns
---
Changes in v6:
- Add Frank's Rb
- Link to v5:
https://lore.kernel.org/r/20250326-sets-bxs-4-6
and
this property should be applied wherever it accurately describes the
vendor integration.
Note that the new required properties for power domains are conditional on
the new base compatible string to avoid an ABI break.
Signed-off-by: Matt Coster
Reviewed-by: Krzysztof Kozlowski
---
Changes in
06a9697d068711140e9c47
Best regards,
--
Matt Coster
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https
). That patch adds the function pvr_vm_unmap_obj()
which is used here.
[1]:
https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded2...@imgtec.com
Signed-off-by: Sarah Walker
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r
ad.
>
> Ensure all firmware GEM objects are destroyed if firmware image
> processing fails.
>
> [...]
Applied, thanks!
[1/1] drm/imagination: fix firmware memory leaks
commit: a5b230e7f3a55bd8bd8d012eec75a4b7baa671d5
Best regards,
--
Matt Coster
[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel
[2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html
[3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.ke
Use the new compatible string introduced earlier (in "dt-bindings: gpu:
img: More explicit compatible strings") and add a name to the single power
domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
details").
Signed-off-by: Matt Coster
---
Changes in v4:
-to-be-added RISC-V firmware
processors cannot be masked in hardware. This change allows us to continue
using the threaded handler in GPUs with a RISC-V firmware.
For simplicity, the same approach is taken for all firmware processors.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
From: Alessio Belle
Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-3-143b3dbef
[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel
[2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html
[3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.ke
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/
). That patch adds the function pvr_vm_unmap_obj()
which is used here.
[1]:
https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded2...@imgtec.com
Signed-off-by: Sarah Walker
Signed-off-by: Matt Coster
---
Changes in v4:
- Use pvr_vm_unmap_obj() in pvr_riscv_vm_unmap
memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-15-143b3dbef...@imgtec.com
Changes in v3:
- Change
tps://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865...@imgtec.com
---
Alessio Belle (3):
drm/imagination: Update register defs for newer GPUs
drm/imagination: Mask GPU IRQs in threaded handler
drm/imagination: Handle Rogue safety event IRQs
Matt Coster (14):
On 02/04/2025 09:40, Alexandru Dadu wrote:
> Reduce the scope of some loop counters as these aren't needed outside
> the loops they're used in.
>
> Signed-off-by: Alexandru Dadu
Hi Alexandru,
Thanks for dragging us into the bright, bright future of (C)99!
Reviewed-by: Ma
fe53a1736b064
Best regards,
--
Matt Coster
errogated from the device at runtime,
we can match on the generic "img,img-rogue" and avoid adding more entries
with NULL data members (barring hardware quirks).
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v
Use the new compatible string introduced earlier (in "dt-bindings: gpu:
img: More explicit compatible strings") and add a name to the single power
domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
details").
Signed-off-by: Matt Coster
---
Changes in v5:
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-12-d987cf4ca...@imgtec.com
Changes in v4:
- None
- Link to v3
Unlike AXE-1-16M, BXS-4-64 uses two power domains.
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.
Signed-off-by: Matt Coster
---
Changes in v5:
- Replace anyOf/const with enum
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4
-to-be-added RISC-V firmware
processors cannot be masked in hardware. This change allows us to continue
using the threaded handler in GPUs with a RISC-V firmware.
For simplicity, the same approach is taken for all firmware processors.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-15-d987cf4ca...@imgtec.com
Changes in v4:
- None
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-10
and
this property should be applied wherever it accurately describes the
vendor integration.
Note that the new required properties for power domains are conditional on
the new base compatible string to avoid an ABI break.
Signed-off-by: Matt Coster
---
Changes in v5:
- Remove extra
o not have
an equivalent register.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-8-d987cf4ca...@imgtec.com
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-8
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4
different GPU power
topologies.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-5-d987cf4ca...@imgtec.com
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-5-143b3d
Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-9-d987cf4ca...@imgtec.com
Cha
errogated from the device at runtime,
we can match on the generic "img,img-rogue" and avoid adding more entries
with NULL data members (barring hardware quirks).
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes
From: Alessio Belle
Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes in v5:
- None
- Link to v4:
https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-3-d987cf4ca
d30e865...@imgtec.com
---
Alessio Belle (3):
drm/imagination: Update register defs for newer GPUs
drm/imagination: Mask GPU IRQs in threaded handler
drm/imagination: Handle Rogue safety event IRQs
Matt Coster (14):
dt-bindings: gpu: img: Future-proofing enhancements
dt-
_kmalloc_large_node_noprof+0x2c/0x13c
> __kmalloc_noprof+0x48/0x4c0
> pvr_fw_init+0xb0c/0x1f50 [powervr]
>
> Cc: sta...@vger.kernel.org
> Fixes: cc1aeedb98ad ("drm/imagination: Implement firmware infrastructure and
> META FW support")
> Signed-off-by: Brendan
-after-free in
> pvr_queue_prepare_job+0x108/0x868 [powervr]
> [ 124.264893] Read of size 1 at addr 084cb960 by task
> kworker/u16:4/63
>
> Cc: sta...@vger.kernel.org
> Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and
> scheduling")
> Si
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-10
and
this property should be applied wherever it accurately describes the
vendor integration.
Note that the new required properties for power domains are conditional on
the new base compatible string to avoid an ABI break.
Signed-off-by: Matt Coster
---
Changes in v4:
- Add img,img-rogue ba
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https
o not have
an equivalent register.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-8-143b3dbef...@imgtec.com
Changes in v3:
- Reference a different commit removing use of enable/disable ops.
- Link to v2:
https://lore.
Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-9-143b3dbef...@imgtec.com
Cha
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-12-143b3dbef...@imgtec.com
Changes in v3:
- None
- Link to v2
different GPU power
topologies.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-5-143b3dbef...@imgtec.com
Changes in v3:
- None
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-6-3fd45d
Unlike AXE-1-16M, BXS-4-64 uses two power domains.
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.
Signed-off-by: Matt Coster
---
Changes in v4:
- Add minItems: 1 to power-domain-names so we don't break single domain
bindings
- Add
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.
Signed-off-by: Matt Coster
---
Changes in v4:
- None
- Link to v3:
https://lore.kernel.org/r/20250310-sets-bxs-4
from it e.g. via pvr_power_reset().
Note that Rogue GPUs may send interrupts to the host for all types of
safety events, not just the two above. For events not handled by the host,
clearing the associated interrupt is sufficient.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes
[1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel
[2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html
[3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https://lore.ke
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https
---
Alessio Belle (3):
drm/imagination: Update register defs for newer GPUs
drm/imagination: Mask GPU IRQs in threaded handler
drm/imagination: Handle Rogue safety event IRQs
Matt Coster (14):
dt-bindings: gpu: img: Future-proofing enhancements
dt-bindings: gpu: img:
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4
Unlike AXE-1-16M, BXS-4-64 uses two power domains.
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
integration in the TI k3-j721s2.
Signed-off-by: Matt Coster
---
Changes in v3:
- Include adding the second power domain so it's in context
- Remove unnecessary ex
On 11/03/2025 07:50, Krzysztof Kozlowski wrote:
> On Mon, Mar 10, 2025 at 01:10:25PM +0000, Matt Coster wrote:
>> The first compatible strings added for the AXE-1-16M are not sufficient to
>> accurately describe all the IMG Rogue GPUs. The current "img,img-axe"
>&
On 11/03/2025 07:51, Krzysztof Kozlowski wrote:
> On Mon, Mar 10, 2025 at 01:10:26PM +0000, Matt Coster wrote:
>> Unlike AXE-1-16M, BXS-4-64 uses two power domains.
>>
>> Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
>> integration in the TI k3-
errogated from the device at runtime,
we can match on the generic "img,img-rogue" and avoid adding more entries
with NULL data members (barring hardware quirks).
Signed-off-by: Matt Coster
---
Changes in v3:
- Don't use more specific compatible strings when not required
- Link t
memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.
Signed-off-by: Matt Coster
---
Changes in v3:
- Change from a workaround to a regular codepath
- Add missing include
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-11
o not have
an equivalent register.
Signed-off-by: Matt Coster
---
Changes in v3:
- Reference a different commit removing use of enable/disable ops.
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-10-3fd45d9fb...@imgtec.com
Changes in v2:
- None
- Link to
Use the new compatible string introduced earlier (in "dt-bindings: gpu:
img: More explicit compatible strings") and add a name to the single power
domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain
details").
Signed-off-by: Matt Coster
---
Changes in v3:
different GPU power
topologies.
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-6-3fd45d9fb...@imgtec.com
Changes in v2:
- None
- Link to v1:
https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-6-4ed30e865
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.
Signed-off-by: Matt Coster
---
Changes in v3:
- Remove device overrides
- Remove specific co
From: Sarah Walker
Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware
processor instead of the previous MIPS or META.
Signed-off-by: Sarah Walker
Signed-off-by: Matt Coster
---
Changes in v3:
- Don't enable debug module
- Link to v2:
https://lore.kernel.org/r/20241118
From: Alessio Belle
Update the register define header to a newer version that covers more
recent GPUs, including BXS-4-64.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
---
Changes in v3:
- Added
---
drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h | 153 +---
1
Now that enable_reg isn't used, rename the previously shared event_mask to
status_mask since it's only used with status_reg.
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-11-3fd45d9fb...@imgtec.com
Cha
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.
Signed-off-by: Matt Coster
---
Changes in v3:
- None
- Link to v2:
https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-14-3fd45d9fb...@imgtec.com
Changes in v2:
- None
- Link to v1
and
this property should be applied wherever it accurately describes the
vendor integration.
Note that the new required properties for power domains are conditional on
the new base compatible string to avoid an ABI break.
Signed-off-by: Matt Coster
---
Changes in v3:
- Remove unnecessary ex
-to-be-added RISC-V firmware
processors cannot be masked in hardware. This change allows us to continue
using the threaded handler in GPUs with a RISC-V firmware.
For simplicity, the same approach is taken for all firmware processors.
Signed-off-by: Alessio Belle
Signed-off-by: Matt Coster
e. interpreting
> the first value in memory as the lowest 32 bits, and the second value
> as the highest 32 bits (then truncated to 16 bits).
>
> [...]
Applied, thanks!
[1/1] drm/imagination: Fix timestamps in firmware traces
commit: 1d2eabb6616433ccaa13927811bdfa205e91ba60
Best regards,
--
Matt Coster
66 ("drm/imagination: Add firmware trace to debugfs")
> Signed-off-by: Alessio Belle
Reviewed-by: Matt Coster
Cheers,
Matt
> ---
> drivers/gpu/drm/imagination/pvr_fw_trace.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/d
hanks!
[1/1] drm/imagination: Hold drm_gem_gpuva lock for unmap
commit: a5c4c3ba95a52d66315acdfbaba9bd82ed39c250
Best regards,
--
Matt Coster
once
commit: 68c3de7f707e8a70e0a6d8087cf0fe4a3d5dbfb0
Best regards,
--
Matt Coster
> [ 607.458245] Possible unsafe locking scenario:
>
> [...]
Applied, thanks!
[1/1] drm/imagination: avoid deadlock on fence release
commit: df1a1ed5e1bdd9cc13148e0e5549f5ebcf76cf13
Best regards,
--
Matt Coster
n: remove unnecessary header include path
commit: 2e064e3f3282ec016d80cb7b1fadff0d8e2014ca
Best regards,
--
Matt Coster
t;
> Signed-off-by: Brendan King
Hi Brendan,
Reviewed-by: Matt Coster
Would you mind sending a V2 with "Cc: sta...@vger.kernel.org" so this
fix will get picked up for stable backporting?
Cheers,
Matt
> ---
> drivers/gpu/drm/imagination/pvr_fw_meta.c |
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