2130P platform.
> Single CTL is used for all interfaces used by a single path
>
> Fixes: 178575173472 ("drm/msm/dpu: add catalog entry for SAR2130P")
This was probably more of a "developed and merged in parallel" problem than a
faulty patch, because a2649952f66e w
u_hw_ctl_reset_intf_cfg_v1() already takes this approach, and only unsets the
merge_3d bit provided in dpu_hw_intf_cfg, and doesn't clear the whole register
to zero :)
- Marijn
>
> Reviewed-by: Marijn Suijten
> Tested-by: Neil Armstrong # on SM8550-QRD
> Signed-off-by: Dmitry Barysh
On 28 February 2025 05:14:06 CET, Dmitry Baryshkov
wrote:
>If several interfaces are being handled through a single CTL, a main
>('master') INTF needs to be programmed into a separate register. Write
>corresponding value into that register.
>
>Co-developed-by: Marij
On 28 February 2025 05:14:12 CET, Dmitry Baryshkov
wrote:
>Now as we have dropped the DPU_CTL_SPLIT_DISPLAY from DPU >= 5.0
>configuration, drop the rm->has_legacy_ctl condition which short-cutted
>the check for those platforms.
>
>Suggested-by: Marijn Suijten
>Signed-
On 2025-02-21 01:58:58, Dmitry Baryshkov wrote:
> On Fri, Feb 21, 2025 at 12:34:12AM +0100, Marijn Suijten wrote:
> > On 2025-02-20 12:26:23, Dmitry Baryshkov wrote:
> > > Unlike previous generation, since DPU 5.0 it is possible to use just one
> > > CTL to handle a
ght "pair" of CTLs
exist: not on DPU 4.0, but on DPU 3.0 we see that CTL_0 and CTL_2 have this bit
but not CTL_1. Meaning that split display can only work when that specific pair
of CTL_0 and CTL_2 is used in conjunction?
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn S
: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm
acy_ctls &&
> + needs_split_display != has_split_display)
I deduced a long time ago that the check for rm->has_legacy_ctls is not needed.
needs_split_display is always false on DPU >= 5, and neither of those SoCs has
DPU_CTRL_SPLIT_DISPLAY which means false
On 2025-02-20 12:26:20, Dmitry Baryshkov wrote:
> Active controls require setup of the master interface. Pass the selected
> interface to CTL configuration.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_enco
On 2025-02-20 12:26:19, Dmitry Baryshkov wrote:
> If several interfaces are being handled through a single CTL, a main
> ('master') INTF needs to be programmed into a separate register. Write
> corresponding value into that register.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/ms
, CTL_MERGE_3D_ACTIVE, merge_3d_active);
No other writes (except the new CDM, strangely) are done conditionally, since
the value does not change. Let's keep it consistent with the other register
writes and maybe clean this up in the future when this function gets a single
view of all "con
On 2025-02-20 18:06:01, Dmitry Baryshkov wrote:
> On Thu, Feb 20, 2025 at 11:42:28PM +0800, Jun Nie wrote:
> > Dmitry Baryshkov 于2025年2月20日周四 18:39写道：
> > >
> > > On Thu, Feb 20, 2025 at 06:07:56PM +0800, Jun Nie wrote:
> > > > There is dual DSI case that every DSI link is connected to an
> > > >
trated in https://gitlab.freedesktop.org/drm/msm/-/issues/41.
Signed-off-by: Marijn Suijten
---
Changes in v3:
- Removed start of multiline comment inside another comment
(editor detritus from merging two comments in v2);
- Inserted empty newline after the start of multi-line comments (per
kernel coding style
u1: Add support for DSC in topology")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b
per-interface by the current
design of MSM DPU/DSI implementations and their use of the DRM DSC
helpers.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/d
ewed-by: Dmitry Baryshkov
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index
> > > > On Mon, Feb 10, 2025 at 01:54:29PM +0100, Marijn Suijten wrote:
> > > > > On 2025-02-10 01:11:59, Dmitry Baryshkov wrote:
> > > > > > On Sun, Feb 09, 2025 at 10:42:53PM +0100, Marijn Suijten wrote:
> > > > > > > Ordering issues
On 2025-02-12 15:03:46, James A. MacInnes wrote:
> SDM845 DPU hardware is rev 4.0.0 per hardware documents.
> Original patch to enable wide_bus operation did not take into account
> the SDM845 and it got carried over by accident.
>
> - Incorrect setting caused inoperable DisplayPort.
> - Corrected
On 2025-02-11 21:06:19, Danila Tikhonov wrote:
> On 2/9/25 01:09, Marijn Suijten wrote:
> > On 2025-02-03 21:14:26, Danila Tikhonov wrote:
> >> From: Eugene Lepshy
> >>
> >> DRM DSC helper has parameters for various bpc values other than 8:
> > W
On 2025-02-10 14:14:14, Abhinav Kumar wrote:
>
>
> On 2/9/2025 7:51 PM, Ethan Carter Edwards wrote:
> > There is a possibility for an uninitialized *ret* variable to be
> > returned in some code paths.
> >
> > Fix this by initializing *ret* to 0.
> >
> > Addresses-Coverity-ID: 1642546 ("Uniniti
On 2025-02-10 18:13:58, Konrad Dybcio wrote:
> On 10.02.2025 6:10 PM, Konrad Dybcio wrote:
> > On 8.02.2025 11:09 PM, Marijn Suijten wrote:
> >> On 2025-02-03 21:14:26, Danila Tikhonov wrote:
...
> >>> dsc->simple_422 = 0;
> >>> dsc->convert_rgb
st using it without any mentioned issues.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/
On 2025-02-10 01:11:59, Dmitry Baryshkov wrote:
> On Sun, Feb 09, 2025 at 10:42:53PM +0100, Marijn Suijten wrote:
> > Ordering issues here cause an uninitialized (default STANDALONE)
> > usecase to be programmed (which appears to be a MUX) in some cases
> > when msm_dsi_host
trated in https://gitlab.freedesktop.org/drm/msm/-/issues/41.
Signed-off-by: Marijn Suijten
---
Changes in v2:
- Dropped patches that were applied;
- dsi_mgr_setup_components() now sets both the usecase and phy_mode
prior to calling msm_dsi_host_register(), and for non-bonded too;
- Added patch to remove a forc
per-interface by the current
design of MSM DPU/DSI implementations and their use of the DRM DSC
helpers.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 8
drivers/gpu/drm/msm/msm_dsc_
ing into DSI0's
tree are way further down, so if this bit turns out to be a simple mux
between dsiXvco and out_div, that shouldn't have any effect as this
whole tree is off anyway.
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 30 +++-
u1: Add support for DSC in topology")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1
On 2025-02-03 21:14:26, Danila Tikhonov wrote:
> From: Eugene Lepshy
>
> DRM DSC helper has parameters for various bpc values other than 8:
Weird zero-width \u200b spaces here between "values" and "other", please delete
those.
> (8/10/12/14/16).
>
> Remove this guard.
>
> Signed-off-by: Eug
On 2025-01-21 16:58:24, Luca Weiss wrote:
> Hi Marijn,
>
> On Tue Jan 21, 2025 at 12:06 AM CET, Marijn Suijten wrote:
> > Some SoCs such as SC7280 (used in the FairPhone 5) have only a single
> > DSC "hard slice" encoder. The current hardcoded use of 2:2:1 top
stants of 2
DSC encoders are replaced to count or read back the actual number of
DSC hardware blocks that are enabled for the given virtual encoder.
Likewise DSC_MODE_SPLIT_PANEL can no longer be unconditionally enabled.
Cc: Luca Weiss
Signed-off-by: Marijn Suijten
---
Note that this doesn't paint
stants of 2
DSC encoders are replaced to count or read back the actual number of
DSC hardware blocks that are enabled for the given virtual encoder.
Likewise DSC_MODE_SPLIT_PANEL can no longer be unconditionally enabled.
Cc: Luca Weiss
Signed-off-by: Marijn Suijten
---
Note that this doesn't paint
On 2025-01-18 00:00:51, Jun Nie wrote:
> There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd
> interface to 3rd PP instead of the 2nd PP.
Can you explain why this patch uses the number of LMs, instead of dividing the
number of PPs divided by the number of physical encoders? This detai
On 2025-01-17 15:32:44, Jun Nie wrote:
> Dmitry Baryshkov 于2025年1月16日周四 16:32写道：
> >
> > On Thu, Jan 16, 2025 at 03:26:05PM +0800, Jun Nie wrote:
> > > Request 4 mixers and 4 DSC for the case that both dual-DSI and DSC are
> > > enabled.
> >
> > Why? What is the issue that you are solving?
>
>
rora.org/
[2]:
https://lore.kernel.org/linux-arm-msm/CAA8EJpqjWbEbgn9Sw=hd8f7pp+nxdem308jg8hirkjk7qcf...@mail.gmail.com/
>
> To: Rob Clark
> To: Dmitry Baryshkov
> To: Sean Paul
> To: Marijn Suijten
> To: David Airlie
> To: Simona Vetter
> To: Stephen Boyd
On 2024-12-02 19:31:38, Abhinav Kumar wrote:
> On some MSM chipsets, the display port controller is capable of supporting
> two streams. To drive the second stream, the pixel clock for the corresponding
> stream needs to be enabled. In order to add the bindings for the pixel clock
> for the second
On 2024-08-29 18:17:32, Jun Nie wrote:
> Data width for dsc engine is aligned with pipe, not with whole screen
> width. Because the width may be halved in DSI bonded case.
>
> The dsc width is not related to the timing with back front porch in
> later stage, so update dsc timing earlier.
>
> Sign
ryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 49
quot;).
>
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 37 -
> 1 file changed, 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/
ed-off-by: Dmitry Baryshkov
Patch itself is fine, just think the title could be clearer:
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 5 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
On 2024-06-13 20:05:05, Dmitry Baryshkov wrote:
> Add enum dpu_vsync_source instead of a series of defines. Use this enum
> to pass vsync information.
>
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
> drivers/gpu/drm/
On 2024-06-13 20:05:10, Dmitry Baryshkov wrote:
> Make the DPU driver use the TE source specified in the DT. If none is
> specified, the driver defaults to the first GPIO (mdp_vsync0).
mdp_vsync_p?
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 44
>
On 2024-06-13 20:05:11, Dmitry Baryshkov wrote:
> Rename dpu_hw_setup_vsync_source functions to make the names match the
> implementation: on DPU 5.x the TOP only contains timer setup, while 3.x
> and 4.x used MDP_VSYNC_SEL register to select TE source.
Yeah that was never really clear anymore aft
tch, but
how a followup patch is going to respond when msm_dsi_get_te_source() returns
NULL. (Or how that followup patch is expected to deal with that - worth a
doc-comment?)
>
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
>
On 2024-06-13 20:05:04, Dmitry Baryshkov wrote:
> Command mode panels provide TE signal back to the DSI host to signal
> that the frame display has completed and update of the image will not
> cause tearing. Usually it is connected to the first GPIO with the
> mdp_vsync function, which is the defau
C code to be guarded by the separate
> DRM_DISPLAY_DSC_HELPER Kconfig symbol.
>
> Reviewed-by: Jessica Zhang
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/amd/amdgpu/Kconfig | 1 +
> drivers/gpu/drm/display/Kconfig| 6 ++
&g
wed-by: Neil Armstrong
> Fixes: 069a6c0e94f9 ("drm: panel: Add LG sw43408 panel driver")
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/panel/panel-lg-sw43408.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
n
the future, otherwise this patch is slightly unclear for anyone who isn't aware
of the current patch series and its context. Other than that, for the change
itself:
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/panel/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
On 2024-05-22 09:25:54, Dmitry Baryshkov wrote:
> This panel driver uses DSC PPS functions and as such depends on the
> DRM_DISPLAY_DP_HELPER. Select this symbol to make required functions
Here and in the title: maybe this is a remnant from v2, but you split out a
DRM_DISPLAY_DSC_HELPER and should
On 2024-04-18 02:30:59, Dmitry Baryshkov wrote:
> On Wed, Apr 17, 2024 at 01:57:45AM +0200, Marijn Suijten wrote:
> > This comment one line down references a single, "same CTL" that controls
> > two interfaces, so the comment should clearly describe two interfaces
> >
On 2024-04-17 14:58:25, Dmitry Baryshkov wrote:
> On Wed, 17 Apr 2024 at 02:57, Marijn Suijten
> wrote:
> >
> > When configuring the timing of DSI hosts (interfaces) in
> > dsi_timing_setup() all values written to registers are taking bonded
> > DSI into account
On 2024-04-17 18:29:34, David Wronek wrote:
> Add support for the 2560x1600@90Hz OLED panel by EDO bundled with a
> Raydium RM69380 controller, as found on the Lenovo Xiaoxin Pad Pro 2021.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: David Wronek
Reviewed-by:
On 2024-04-17 11:18:58, Dmitry Baryshkov wrote:
> On Wed, 17 Apr 2024 at 02:57, Marijn Suijten
> wrote:
> >
> > Ordering issues here cause an uninitalized (default STANDALONE)
> > usecase to be programmed (which appears to be a MUX) in some cases
> > when msm
expected to only set the slice width and
number of slices for half the panel, i.e. what will be sent by each
host individually, rather than fixing that up like hdisplay here.
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Marijn Suijten
---
drive
adjusted for DSC compression) msm_host->pixel_clk_rate
which is passed to clk_set_rate() just below. Fix that by printing the
actual pixel_clk_rate that is being set.
Fixes: ed9976a09b48 ("drm/msm/dsi: adjust dsi timing for dual dsi mode")
Signed-off-by: Marijn Suijten
---
drivers/
ing into DSI0's
tree are way further down, so if this bit turns out to be a simple mux
between dsiXvco and out_div, that shouldn't have any effect as this
whole tree is off anyway.
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 +++
1 fil
This comment one line down references a single, "same CTL" that controls
two interfaces, so the comment should clearly describe two interfaces
used with a single active CTL and not "two CTLs".
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Ma
All other functions in dpu_hw_intf name the "self" parameter `intf`,
except dpu_hw_intf_setup_timing_engine() and the recently added
dpu_hw_intf_program_intf_cmd_cfg(). Clean that up for consistency.
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_i
in hw_ctl")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a06f69d0b257..2e50049f2f85 10064
ensource/display-drivers/-/blob/display-kernel.lnx.5.4.r1-rel/msm/sde/sde_encoder_phys_cmd.c?ref_type=heads#L1131-1139
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 ---
1 file changed, 3
.r1-rel/msm/sde/sde_encoder_phys_cmd.c?ref_type=heads#L1131-1139
Signed-off-by: Marijn Suijten
---
Marijn Suijten (7):
drm/msm/dsi: Print dual-DSI-adjusted pclk instead of original mode pclk
drm/msm/dsi: Pass bonded-DSI hdisplay/2 to DSC timing configuration
drm/msm/dpu: Always flush t
Hi Randy,
[..]
> Do you see differences in the generated html for these changes?
I have not yet generated the HTML locally to test this patch, but will surely do
if that's a requirement.
> "&struct somestruct" and "&somestruct" should both be OK AFAIK, although
> Documentation/doc-guide/kernel-
On 2024-04-16 20:30:49, David Wronek wrote:
> Add support for the 2560x1600@90Hz OLED panel by EDO bundled with a
> Raydium RM69380 controller, as found on the Lenovo Xiaoxin Pad Pro 2021.
>
> Signed-off-by: David Wronek
> ---
> drivers/gpu/drm/panel/Kconfig | 14 +
> drivers/gp
On 2024-04-15 19:50:49, Dmitry Baryshkov wrote:
> On Mon, Apr 15, 20
[...]
> > +static int rm69380_on(struct rm69380_panel *ctx)
[...]
> ret = mipi_dsi_dcs_set_display_brightness_large(dsi, 0x7ff);
Downstream may send this here, but why? As far as I've observed, update_status
also sets &backlight
also already having a `&` reference prefix in two
of the three cases. Remove the `struct` prefix to turn these references
into proper links to the designated field.
Fixes: 7beb691f1e6f ("drm: Initialize struct drm_crtc_state.no_vblank from
device settings")
Signed-off-by: Marijn Sui
On 2024-04-08 02:53:52, Dmitry Baryshkov wrote:
> Add the extended version of mipi_dsi_compression_mode(). It provides
> a way to specify the algorithm and PPS selector.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Something doesn't stick with me on the _ex
Can we drop (fix video mode DSC) from this patch title? It looks like more
patches are required to get this done, such a mention is more something for the
cover letter.
We could also clarify further to "set Word Count for video-mode DSC".
- Marijn
On 2024-04-03 17:10:59, Jun Nie wrote:
> From:
On 2024-04-08 17:58:29, Jun Nie wrote:
> Dmitry Baryshkov 于2024年4月3日周三 17:41写道：
> >
> > On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> > >
> > > Add variable for slice number of a DSC compression bit stream packet.
> > > Its value shall be specified in panel driver, or default value can be set
> >
On 2024-04-03 05:37:29, Dmitry Baryshkov wrote:
> On Tue, Apr 02, 2024 at 11:17:52PM +0200, Marijn Suijten wrote:
> > On 2024-04-02 02:51:15, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIPI-DSI pan
and support turning off the panel]
> Signed-off-by: Caleb Connolly
> [DB: partially rewrote the driver and fixed DSC programming]
> Signed-off-by: Dmitry Baryshkov
Some small nits but I think this deserves a:
Reviewed-by: Marijn Suijten
> ---
> MAINTAINERS
On 2024-04-02 02:51:14, Dmitry Baryshkov wrote:
> Add the extended version of mipi_dsi_compression_mode(). It provides
> a way to specify the algorithm and PPS selector.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 33 +++--
> include/d
ixes: f4dea1aaa9a1 ("drm/dsi: add helpers for DSI compression mode and PPS
> packets")
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/drm_mipi_dsi.c | 6 +++---
> include/drm/drm_mipi_dsi.h | 6 +++---
> 2 files changed, 6
On 2024-04-02 10:23:22, Dmitry Baryshkov wrote:
> On Tue, 2 Apr 2024 at 09:31, Krzysztof Kozlowski
> wrote:
> >
> > On 02/04/2024 01:51, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel present on Google Pixel 3
> > > phones.
> > >
> > >
On 2024-04-01 22:11:48, Dmitry Baryshkov wrote:
> On Mon, 1 Apr 2024 at 13:29, Marijn Suijten
> wrote:
> >
> > On 2024-03-30 16:37:08, Dmitry Baryshkov wrote:
> > > On Sat, 30 Mar 2024 at 12:27, Marijn Suijten
> > > wrote:
> > > >
> &
On 2024-03-30 05:59:29, Dmitry Baryshkov wrote:
> The LG SW43408 panel requires sending non-standard data as a part of the
> MIPI_DSI_COMPRESSION_MODE packet. Rather than hacking existing
> mipi_dsi_compression_mode() add mipi_dsi_compression_mode_raw(), which
> accepts raw data buffer and length.
On 2024-03-30 16:37:08, Dmitry Baryshkov wrote:
> On Sat, 30 Mar 2024 at 12:27, Marijn Suijten
> wrote:
> >
> > On 2024-03-30 05:59:30, Dmitry Baryshkov wrote:
> > > From: Sumit Semwal
> > >
> > > LG SW43408 is 1080x2160, 4-lane MIP
On 2024-03-30 11:31:37, Marijn Suijten wrote:
> On 2024-03-30 05:53:22, Dmitry Baryshkov wrote:
> > There is little point in using %ps to print a value known to be NULL. On
> > the other hand it makes sense to print the callback symbol in the
> > 'invalid IRQ' m
On 2024-03-30 05:52:29, Dmitry Baryshkov wrote:
> In case of CMD DSI panels, the vblank IRQ can be used outside of
> irq_enable/irq_disable pair. This results in the following kind of
Can you clarify when exactly that is? Is it via ops.control_vblank_irq in
dpu_encoder_toggle_vblank_for_crtc()?
t;
> Fixes: 6893199183f8 ("drm/msm/dpu: stop using raw IRQ indices in the kernel
> output")
> Signed-off-by: Dmitry Baryshkov
Agreed, this is a lot more clear:
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8
> 1 fi
On 2024-03-30 05:59:30, Dmitry Baryshkov wrote:
> From: Sumit Semwal
>
> LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel, used in some Pixel3
> phones.
>
> Whatever init sequence we have for this panel isn't capable of
> initialising it completely, toggling the reset gpio ever causes the
> panel
not yet used to correctly configure
this flag.
Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
Signed-off-by: Marijn Suijten
---
Note that more changes are needed to properly support the proposed 2:2:2
and 1:1:1 topology (in contrast to the already-suppo
drm_mipi_dsi.h already provides a conversion function from MIPI_DSI_FMT_
to bpp, named mipi_dsi_pixel_format_to_bpp().
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm
On 2024-01-21 20:41:05, Adam Skladowski wrote:
> Declare pinctrls for SDC pins and wire them to consumers.
>
> Signed-off-by: Adam Skladowski
Where'd the original sign-offs go?
https://lore.kernel.org/linux-arm-msm/20221214232049.703484-1-marijn.suij...@somainline.org/
Thanks taking taking car
Title typo: SC8108X -> SC8180X :)
On 2023-12-03 03:32:01, Dmitry Baryshkov wrote:
> Enable WB2 hardware block, enabling writeback support on this platform.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 18 ++
> 1 file changed, 18 in
e of using DRM_ERROR over DPU_ERROR*, resulting
in unnecessary divergence (and un-readability) between error messages and the
code (DPU_DEBUG_CMDENC, which has a corresponding DPU_ERROR variant, is also
used within that function...)
Reviewed-by: Marijn Suijten
> drivers/gpu/drm/msm/disp/dpu1/dpu_
for DSI")
> Signed-off-by: Jonathan Marek
Conditional r-b assuming this will be submitted to mesa, otherwise it'll
disappear when the next person updates and regenerates these bindings.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
> drivers/gpu/d
On 2023-11-14 14:00:19, Jonathan Marek wrote:
> On 11/14/23 1:28 PM, Marijn Suijten wrote:
> > On what hardware have you been testing this? Dmitry and I have a stack of
> > patches to resolve support for Active CTL programming on newer hardware (DPU
> > 5.0+ IIRC),
On what hardware have you been testing this? Dmitry and I have a stack of
patches to resolve support for Active CTL programming on newer hardware (DPU
5.0+ IIRC), where a single CTL is responsible for programming multiple INTF and
DSC blocks as used in bonded DSI.
On 2023-11-14 12:42:16, Jonathan
On 2023-10-09 18:36:11, Neil Armstrong wrote:
> Starting with the SM8550 platform, the SSPP & WB Clock Controls are
> no more in the MDP TOP registers, but in the SSPP & WB register space.
>
> Add the corresponding SSPP & WB ops and use them from the vbif QoS
> and OT limit setup functions.
>
> S
. Set it now, splitting the vig_sblk data
> which has different version fields.
>
> Reported-by: Marijn Suijten
> Fixes: 9b6f4fedaac2 ("drm/msm/dpu: Add SM6125 support")
> Fixes: 27f0df03f3ff ("drm/msm/dpu: Add SM6375 support")
> Fixes: 3186acba5cdc ("drm/msm/dp
On 2023-08-22 10:42:07, Jessica Zhang wrote:
> DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> 48 bits of compressed data instead of 24.
>
> Enable this mode whenever DSC is enabled for supported chipsets.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/dsi/
-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 +-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 51 +++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 2 +
> 3 files changed, 46 insertions
writeback got the
> older invocation in place. This was unnoticed for several releases, but
> now it's time to fix it.
>
> Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for
> writeback")
> Signed-off-by: Dmitry Baryshkov
Reviewed-b
On 2023-08-03 22:47:24, Danila Tikhonov wrote:
> Add definitions for the display hardware used on the Qualcomm SM7150
> platform.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../msm/disp/dpu1/catalog/dpu_5_2_sm7150.h| 277 ++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|
On 2023-08-03 22:47:23, Danila Tikhonov wrote:
> Document the DPU hardware found on the Qualcomm SM7150 platform.
>
> Signed-off-by: Danila Tikhonov
> ---
> .../bindings/display/msm/qcom,sm7150-dpu.yaml | 116 ++
> 1 file changed, 116 insertions(+)
> create mode 100644
> Docume
.
>
> Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant
> chipsets")
> Reported-by: Ryan McCann
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
> ---
>
> Changes since v1:
> - Rebased o
.
>
> Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant
> chipsets")
> Reviewed-by: Abhinav Kumar
> Reviewed-by: Marijn Suijten
> Signed-off-by: Dmitry Baryshkov
> ---
>
> Changes since v1:
> - Rebased on top of the catalog
On 2023-08-02 11:08:49, Jessica Zhang wrote:
> DPU supports a data-bus widen mode for DSI INTF.
>
> Enable this mode for all supported chipsets if widebus is enabled for DSI.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ---
> driver
I find this title very undescriptive, it doesn't really explain from/to
where this move is happening nor why.
On 2023-08-02 11:08:48, Jessica Zhang wrote:
> Move the setting of dpu_enc.wide_bus_en to
> dpu_encoder_virt_atomic_enable() so that it mirrors the setting of
> dpu_enc.dsc.
mirroring "th
On 2023-07-30 03:35:18, Dmitry Baryshkov wrote:
> As the INTF is fixed at the encoder creation time, we can move the
> check whether INTF supports tearchck to dpu_encoder_phys_cmd_init().
> This function can return an error if INTF doesn't have required feature.
> Performing this check in dpu_encod
On 2023-07-30 03:35:12, Dmitry Baryshkov wrote:
> The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
> Rather than checking for the flag, check for the presense of the
> corresponding interrupt line.
>
> Reviewed-by: Marijn Suijten
This patch changed signi
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