> From: Hai Li [mailto:hali at codeaurora.org]
> Sent: den 21 augusti 2015 12:56
>
> When I made DSI changes, I tried to limit the information in DT (like
> our downstream driver), until there is a case driver really cannot
> figure it out by the existing information.
> I think this is the require
> From: Hai Li [mailto:hali at codeaurora.org]
> Sent: den 21 augusti 2015 13:14
> Hi Werner,
>
> I will prepare a change to make the lane swap configurable.
>
> Thanks,
> Hai
That sounds really great Hai!
Any idea as to why this lane swap would misbehave? In theory the swap should be
complete
Hi,
I'm having issues with non-functional DSI output driving a 2-lane panel
connected to DSI0 on MSM8x74 MDP5 v1.2 hardware. The code in
drivers/gpu/drm/msm/dsi/dsi_host.c around line 703 enables lane 1 and 2 instead
of lane 0 and 1 for performance reasons (and then enables lane swapping in the
Hi,
In drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c there are a few "magic number"
writes to the PHY_LN_CFG_4(x) registers around line 108 (adjusting the hs_zero
period per lane). This causes some problems with certain panel timings when
timing->hs_zero plus an "unknown integer" becomes evenly di
Hi,
In drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c there are a few "magic number"
writes to the PHY_LN_CFG_4(x) registers around line 108 (adjusting the hs_zero
period per lane). This causes some problems with certain panel timings when
timing->hs_zero plus an "unknown integer" becomes evenly di
Hi,
I'm having issues with non-functional DSI output driving a 2-lane panel
connected to DSI0 on MSM8x74 MDP5 v1.2 hardware. The code in
drivers/gpu/drm/msm/dsi/dsi_host.c around line 703 enables lane 1 and 2 instead
of lane 0 and 1 for performance reasons (and then enables lane swapping in the
