On Tue, Oct 27, 2020 at 06:36:02PM -0700, Hyun Kwon wrote:
> Hi Peter,
>
> Thanks for the patch.
>
> On Fri, Oct 23, 2020 at 02:46:02AM -0700, Peter Ujfalusi wrote:
> > There is no need to use the of_dma_request_slave_channel() directly as
> > dma_request_chan()
Hi Peter,
Thanks for the patch.
On Fri, Oct 23, 2020 at 02:46:02AM -0700, Peter Ujfalusi wrote:
> There is no need to use the of_dma_request_slave_channel() directly as
> dma_request_chan() is going to try to get the channel via OF as well.
>
> Signed-off-by: Peter Ujfalusi
So now dma_request_
default implementations, so they are just kept empty now.
> >
> > v2:
> > * initialize with DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE (Laurent)
> >
> > Signed-off-by: Thomas Zimmermann
>
> Reviewed-by: Laurent Pinchart
>
Reviewed-by: Hyun Kwon
Thanks,
-h
On Fri, Sep 11, 2020 at 09:27:08AM -0700, Hyun Kwon wrote:
> Hi Daniel,
>
> On Fri, Sep 11, 2020 at 01:15:19AM -0700, Daniel Vetter wrote:
> > On Thu, Sep 10, 2020 at 11:14:18AM -0700, Hyun Kwon wrote:
> > > Hi Jason,
> > >
> > > On Thu, Sep 10,
Hi Daniel,
On Fri, Sep 11, 2020 at 01:15:19AM -0700, Daniel Vetter wrote:
> On Thu, Sep 10, 2020 at 11:14:18AM -0700, Hyun Kwon wrote:
> > Hi Jason,
> >
> > On Thu, Sep 10, 2020 at 07:06:30AM -0700, Jason Yan wrote:
> > > This addresses the follow
245 | static const u32 scaling_factors_666[] = {
> | ^~~
>
> Reported-by: Hulk Robot
> Signed-off-by: Jason Yan
Reviewed-by: Hyun Kwon
Thanks!
-hyun
> ---
> drivers/gpu/drm/xlnx/zynqmp_disp.c | 6 --
> 1 file changed, 6 delet
ut in the error path of the probe
> code.
>
> v2: Drop the misplaced drm_dev_put from zynqmp_dpsub_drm_init (all
> other paths leaked on error, this should have been in
> zynqmp_dpsub_probe), now that subsumed by the auto-cleanup of
> devm_drm_dev_alloc.
>
> Signed-off-b
Hi Kenneth,
> -Original Message-
> From: Kenneth Sloat
> Sent: Thursday, August 20, 2020 2:18 PM
> To: Hyun Kwon ; linux-arm-ker...@lists.infradead.org
> Cc: Michal Simek ; dri-devel@lists.freedesktop.org; linux-
> ker...@vger.kernel.org; laurent.pinch...@ideasonbo
> -Original Message-
> From: dri-devel On Behalf Of Hyun
> Kwon
> Sent: Thursday, July 30, 2020 7:33 PM
> To: Laurent Pinchart
> Cc: Dan Carpenter ; dri-
> de...@lists.freedesktop.org; Daniel Vetter
> Subject: Re: [PATCH v2 1/1] drm: xlnx: zynqmp: Use swi
Hi Laurent,
Thanks for the comment.
On Thu, Jul 30, 2020 at 04:12:46PM -0700, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wed, Jul 29, 2020 at 04:30:45PM -0700, Hyun Kwon wrote:
> > Use switch - case to downshift from the current link rate. It&#
uot; from Jul 7, 2018, leads to the following
static checker warning:
drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
error: iterator underflow 'bws' (-1)-2
Reported-by: Dan Carpenter
Signed-off-by: Hyun Kwon
---
v2
- Convert the for loop into switch - case
Hi Daniel,
Thanks for the review.
On Wed, Jul 29, 2020 at 02:34:16PM -0700, Daniel Vetter wrote:
> On Wed, Jul 29, 2020 at 8:21 PM Hyun Kwon wrote:
> >
> > The loop should exit at the lowest link rate, so break the loop
> > at the lowest link rate without check. The
d76271d22694 ("drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> > DisplayPort Subsystem")
> > Reported-by: Hulk Robot
> > Signed-off-by: Wei Yongjun
>
> Reviewed-by: Laurent Pinchart
>
Reviewed-by: Hyun Kwon
I'll commit this to drm-misc-next-fixes soon.
istake in a dev_dbg messages. Fix it.
>
> There is a spelling mistake in the commit message, s/xln/xlnx/ ;-)
>
> > Signed-off-by: Colin Ian King
>
> Reviewed-by: Laurent Pinchart
>
Reviewed-by: Hyun Kwon
I'll fix the commit message and commit this change to drm-
Hi Dan,
Thanks for sharing.
On Mon, Jul 27, 2020 at 04:18:25AM -0700, dan.carpen...@oracle.com wrote:
> Hello Hyun Kwon,
>
> The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> DisplayPort Subsystem" from Jul 7, 2018, leads to the following
&g
-2
Reported-by: Dan Carpenter
Signed-off-by: Hyun Kwon
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
index b735072..1be2b19 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
+
Hello,
On Tue, Jul 28, 2020 at 03:35:43PM -0700, Laurent Pinchart wrote:
> On Wed, Jul 29, 2020 at 12:02:05AM +0200, dan...@ffwll.ch wrote:
> > Hi Hyun Kwon,
> >
> > Are you all sorted with drm-misc commit rights so you can push the 3
> > (maybe there's more) xln
Hi Laurent,
On Wed, 2020-05-27 at 15:45:24 -0700, Laurent Pinchart wrote:
> Hi Hyun,
>
> On Wed, May 27, 2020 at 10:54:35AM -0700, Hyun Kwon wrote:
> > On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote:
> > > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun K
Hi Laurent,
On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote:
> Hi GVRao,
>
> Thank you for the patch.
>
> On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> > On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> > > Th
Hi GVRao,
Thanks for the patch. Sorry for late reply.
On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video
> data from AXI-4 stream interface.
>
> It supports upto 4 lanes, optional register interface for th
Hi Sam,
On Wed, 2020-03-18 at 12:26:51 -0700, Sam Ravnborg wrote:
> On Wed, Mar 18, 2020 at 05:37:24PM +0200, Laurent Pinchart wrote:
> > From: Hyun Kwon
> >
> > The bindings describe the ZynqMP DP subsystem. They don't support the
> > interface with the progra
Hi Laurent,
On Fri, 2019-11-08 at 09:13:25 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> (CC'ing Daniel, with a question for him below)
>
> On Fri, Sep 27, 2019 at 05:04:57PM -0700, Hyun Kwon wrote:
> > On Wed, 2019-09-25 at 16:55:42 -0700, Laurent Pinchart wr
Hi Laurent,
Thanks for the patch.
On Wed, 2019-09-25 at 16:55:42 -0700, Laurent Pinchart wrote:
> From: Hyun Kwon
>
> The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort
> Subsystem. It includes a buffer manager, a video pipeline renderer
> (blender), an au
Hi Daniel,
On Thu, 2019-02-28 at 02:01:46 -0800, Daniel Vetter wrote:
> On Wed, Feb 27, 2019 at 04:36:06PM -0800, Hyun Kwon wrote:
> > Hi Daniel,
> >
> > On Wed, 2019-02-27 at 06:13:45 -0800, Daniel Vetter wrote:
> > > On Tue, Feb 26, 2019 at 11:20 PM Hyun Kwon wr
Hi Daniel,
On Wed, 2019-02-27 at 06:13:45 -0800, Daniel Vetter wrote:
> On Tue, Feb 26, 2019 at 11:20 PM Hyun Kwon wrote:
> >
> > Hi Daniel,
> >
> > Thanks for the comment.
> >
> > On Tue, 2019-02-26 at 04:06:13 -0800, Daniel Vetter wrote:
> >
Hi Daniel,
Thanks for the comment.
On Tue, 2019-02-26 at 04:06:13 -0800, Daniel Vetter wrote:
> On Tue, Feb 26, 2019 at 12:53 PM Greg Kroah-Hartman
> wrote:
> >
> > On Sat, Feb 23, 2019 at 12:28:17PM -0800, Hyun Kwon wrote:
> > > Add the dmabuf map / unmap inter
Hi Greg,
Thanks for the comments.
On Tue, 2019-02-26 at 03:53:11 -0800, Greg Kroah-Hartman wrote:
> On Sat, Feb 23, 2019 at 12:28:17PM -0800, Hyun Kwon wrote:
> > Add the dmabuf map / unmap interfaces. This allows the user driver
> > to be able to import the external dmabuf and u
Add the dmabuf map / unmap interfaces. This allows the user driver
to be able to import the external dmabuf and use it from user space.
Signed-off-by: Hyun Kwon
---
drivers/uio/Makefile | 2 +-
drivers/uio/uio.c| 43 +
drivers/uio/uio_dmabuf.c | 210
may not be available for
all such devices on all platforms. So any feedback to move forward
would be appreciated.
Thanks,
-hyun
[1] https://patchwork.kernel.org/patch/10774761/
Hyun Kwon (1):
uio: Add dma-buf import ioctls
drivers/uio/Makefile | 2 +-
drivers/uio/ui
orcing the GPL license on its users or
on the module itself when it has a copy of the header in its source
code.
Any guide on what can be done would be appreciated.
Thanks,
-hyun
[1] https://github.com/OpenAMP/libmetal/blob/master/LICENSE.md
Hyun Kwon (1):
staging: android: ion: Add the GPL exc
Add "WITH Linux-syscall-note" to the license to not put GPL
restrictions on user space programs using this header.
Signed-off-by: Hyun Kwon
---
drivers/staging/android/uapi/ion.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/android/uapi/ion.h
correctly.
MAKE_RGBA() can use MAKE_RGBA_64() by scaling each 8bit component
to 16bit, for compatilbity.
Signed-off-by: Hyun Kwon
---
tests/util/pattern.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index
-archive.com/dri-devel@lists.freedesktop.org/msg219340.html
Hyun Kwon (3):
tests: util: pattern: Use 64bit RGB samples
modetest: Add support for YUV422 and YUV444
tests: util: Add support for YUV422 and YUV444
tests/modetest/buffers.c | 29 ++---
tests/util/format.c | 4
Enable YUV422 and YUV444 formats by adding to the format table
and pattern generation calls.
Signed-off-by: Hyun Kwon
---
tests/util/format.c | 4
tests/util/pattern.c | 8
2 files changed, 12 insertions(+)
diff --git a/tests/util/format.c b/tests/util/format.c
index 15ac5e1
This allows dumb buffer allocation for YUV422 and YUV444 with correct
subsampling values.
Signed-off-by: Hyun Kwon
---
tests/modetest/buffers.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
Hi Laurent,
This series is primary waiting for your ack as I didn't hear back on v7 [1].
Please take a look and let me know if there's any concern. I've addressed
most of your comments in v6.
Thanks,
-hyun
[1] https://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg21
This driver creates DRM encoder and connector for ZynqMP DisplayPort.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v8
- Allow to initialize without any phy lane
v7
- Use correct number of lanes
v6
- Constify all function pointers
- Clean up the duplicated license paragraphs
- Do
multiple subdevices and
to represent the entire pipeline as a single DRM device. The module
includes helper (ex, framebuffer and gem helpers) and glue logic
(ex, crtc interface) functions.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v7
- Unbind as component in shutdown
- Register release
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon
Reviewed-by: Rob Herring
---
v6
- Add more descriptions and references
- Remove the description for child node
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v8
- Support reserved memory through memory-region dt binding
v6
- Accomodate the migration of logical master from platform device to device
- Remove the duplicate license
This allows dumb buffer allocation for YUV422 and YUV444 with correct
subsampling values.
Signed-off-by: Hyun Kwon
---
tests/modetest/buffers.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c
Hi,
This set adds more format support for modetest, including fixes for
10bit RGB formats and addition of 422/444 YUV formats.
Thanks,
-hyun
Hyun Kwon (3):
tests: util: pattern: Use 64bit RGB samples
modetest: Add support for YUV422 and YUV444
tests: util: Add support for YUV422 and
correctly.
MAKE_RGBA() can use MAKE_RGBA_64() by scaling each 8bit component
to 16bit, for compatilbity.
Signed-off-by: Hyun Kwon
---
tests/util/pattern.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index
Enable YUV422 and YUV444 formats by adding to the format table
and pattern generation calls.
Signed-off-by: Hyun Kwon
---
tests/util/format.c | 4
tests/util/pattern.c | 8
2 files changed, 12 insertions(+)
diff --git a/tests/util/format.c b/tests/util/format.c
index 15ac5e1
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon
Reviewed-by: Rob Herring
---
v6
- Add more descriptions and references
- Remove the description for child node
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for
multiple subdevices and
to represent the entire pipeline as a single DRM device. The module
includes helper (ex, framebuffer and gem helpers) and glue logic
(ex, crtc interface) functions.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v7
- Unbind as component in shutdown
- Register release
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
Hi Laurent,
On top of addressing your comments in v6, I've incorporated some
relatively small fixes in v7. I'm mainly waiting for your feedback
before committing this series, unless there's any additional review
comments. Please take a look.
Thanks,
-hyun
Hyun Kwon (5):
drm: x
This driver creates DRM encoder and connector for ZynqMP DisplayPort.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v7
- Use correct number of lanes
v6
- Constify all function pointers
- Clean up the duplicated license paragraphs
- Do complete forward declaration in the header
v2
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v6
- Accomodate the migration of logical master from platform device to device
- Remove the duplicate license paragraphs
- Do complete forward declaration in the header
v5
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v6
- Accomodate the migration of logical master from platform device to device
- Remove the duplicate license paragraphs
- Do complete forward declaration in the header
v5
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon
Reviewed-by: Rob Herring
---
v6
- Add more descriptions and references
- Remove the description for child node
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for
This driver creates DRM encoder and connector for ZynqMP DisplayPort.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v6
- Constify all function pointers
- Clean up the duplicated license paragraphs
- Do complete forward declaration in the header
v2
- Change the SPDX identifier format
multiple subdevices and
to represent the entire pipeline as a single DRM device. The module
includes helper (ex, framebuffer and gem helpers) and glue logic
(ex, crtc interface) functions.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v6
- Fix the function desc for pipeline calls
- Rebase on
Hi Laurent,
On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> > Xilinx has various platforms for display, where users can create
> > using multiple I
Hi Danidel,
Thanks for the comment.
On Mon, 2018-02-19 at 06:22:56 -0800, Daniel Vetter wrote:
> On Fri, Feb 09, 2018 at 05:35:54PM -0800, Hyun Kwon wrote:
> > This patch adds new formats needed by Xilinx IP. Pixels are not
> > byte-aligned in these formats, and the drm_format
Hi Laurent,
On Thu, 2018-02-22 at 06:23:38 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wednesday, 7 February 2018 03:36:37 EET Hyun Kwon wrote:
> > This add a dt binding for ZynqMP DP subsystem.
> >
> > Signed-off-by: Hyun K
Hi Laurent,
On Thu, 2018-02-22 at 05:40:50 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> On Thursday, 22 February 2018 04:50:42 EET Hyun Kwon wrote:
> > On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> > > On Wednesday, 7 February 2018 03:36:36 EET Hyun K
Hi Laurent,
On Wed, 2018-02-21 at 15:22:31 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> On Tuesday, 20 February 2018 19:11:42 EET hyun.k...@xilinx.com wrote:
> > On Monday, February 19, 2018 1:43 AM Daniel Vetter wrote:
> > > On Tue, Feb 06, 2018 at 05:36:36P
Hi Laurent,
Thanks for the comment.
On Wed, 2018-02-21 at 16:18:35 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wednesday, 7 February 2018 03:36:39 EET Hyun Kwon wrote:
> > This driver creates DRM encoder and connector for ZynqMP Display
Hi Laurent,
Thanks for the review.
On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> > Xilinx has various platforms for display, where users can create
&
This patch adds new formats needed by Xilinx IP. Pixels are not
byte-aligned in these formats, and the drm_format_info for these
formats has macro-pixel information.
Signed-off-by: Jeffrey Mouroux
Signed-off-by: Hyun Kwon
---
v3
- Update entries for changes
- Squash fourcc patch into this
v2
/archives/dri-devel/2017-November/158744.html
[2] https://www.spinics.net/lists/dri-devel/msg163388.html
Hyun Kwon (6):
drm: fourcc.h: Use inline kern-doc style for struct drm_format_info
drm: drm_fourcc: Introduce macro-pixel info to drm_format_info
drm: fourcc: Add drm_format_plane_width_bytes
level rounding.
Use this drm_fb_cma_get_gem_addr() for offset calculation.
Signed-off-by: Hyun Kwon
---
v3
- Update according to member changes
- Use @cpp for byte-aligned formats, and macro-pixel for non byte-aligned ones
- Squash a change in drm_fb_cma_helper.c into this
v2
- This function is
acro-pixel with 3 pixels. This aligns non-byte addressable
formats with drm core where each pixel / component is expected to be
byte aligned.
Add 'pixels_per_macro' to note how many pixels are in a macro-pixel.
'bytes_per_macro' specifies the size of a macro-pixel in bytes.
Si
This adds packed YUV and grey scale format fourccs.
Signed-off-by: Hyun Kwon
---
v3
- Update entries for changes
- Squash fourcc patch into this
- Note these don't have any reference in mainline
v2
- Split from the previous patch
---
---
drivers/gpu/drm/drm_fourcc.c | 5 +
include
Use the inline kern-doc style for struct drm_format_info for better
readability. This is just a preliminary change for further table update.
Signed-off-by: Hyun Kwon
---
v3
- This is added
---
---
include/drm/drm_fourcc.h | 45 +
1 file changed, 37
Use drm_format_width_bytes() to support non-byte aligned formats.
Signed-off-by: Hyun Kwon
---
v3
- 2 patches are squashed
---
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b
Hi Daniel,
On Tue, 2018-01-30 at 02:27:07 -0800, Daniel Vetter wrote:
> On Thu, Jan 25, 2018 at 06:03:59PM -0800, Hyun Kwon wrote:
> > Multiple pixels can be grouped as a single unit and form a 'macro-pixel'.
> > This is to model formats where multiple pixels are stored t
Hi Daniel,
On Tue, 2018-01-30 at 02:22:40 -0800, Daniel Vetter wrote:
> On Thu, Jan 25, 2018 at 06:03:59PM -0800, Hyun Kwon wrote:
> > Multiple pixels can be grouped as a single unit and form a 'macro-pixel'.
> > This is to model formats where multiple pixels are stored t
This driver creates DRM encoder and connector for ZynqMP DisplayPort.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v2
- Change the SPDX identifier format
- Split drm properties into a separate patch
---
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v4
- Use the newly added xlnx pipeline calls to initialize drm device
v2
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon
Reviewed-by: Rob Herring
---
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for layers
- Update the example accordingly
v2
- Group multiple ports under '
multiple subdevices and
to represent the entire pipeline as a single DRM device. The module
includes helper (ex, framebuffer and gem helpers) and
glue logic (ex, crtc interface) functions.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v5
- Redefine xlnx_pipeline_init()
v4
- Fix a bug in of
Add information for DRM_FORMAT_XV15 and DRM_FORMAT_XV20 to
the drm format table.
Signed-off-by: Hyun Kwon
---
v2
- Accomodate macro pixel changes
---
---
drivers/gpu/drm/drm_fourcc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm
://lists.freedesktop.org/archives/dri-devel/2018-January/162559.html
Hyun Kwon (9):
drm: drm:fourcc: Add bpp information to struct drm_format_info
drm: drm_fourcc: Introduce macro-pixel info to drm_format_info
drm: fourcc: Add drm_format_plane_width_bytes()
drm: xlnx: zynqmp: use drm_format_width_bytes
drm_format_plane_width_bytes() calculates and returns
the number of bytes for given width of specified format.
The calculation uses the macro pixel information to avoid
bit level rounding.
Signed-off-by: Hyun Kwon
---
v2
- This function is added
---
---
drivers/gpu/drm/drm_fourcc.c | 22
This adds new formats (packed YUV and grey scale) to
the drm format table.
Signed-off-by: Hyun Kwon
---
v2
- Split from previous patch
---
---
drivers/gpu/drm/drm_fourcc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index
'cpp' doesn't work for any format where component size is not byte aligned.
Add 'bpp' to have a bit level information. Add a meesage to
drm_format_plane_cpp() to indicate that the returned cpp would be
rounded for non byte aligned formats.
Signed-off-by: Hyun Kwo
Signed-off-by: Hyun Kwon
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index d2e1034..fd6ddfe 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu
cro-pixel as there can be some extra padding bits.
Signed-off-by: Hyun Kwon
---
v2
- Introduce macro-pixel over scaling factors
---
---
drivers/gpu/drm/drm_fourcc.c | 136 +--
include/drm/drm_fourcc.h | 9 +++
2 files changed, 77 insertions(+), 68 dele
From: Jeffrey Mouroux
The Xilinx Video Mixer andn Xilinx Video Framebuffer DMA IP
support video memory formats that are not represented in the
current DRM fourcc library. This patch adds those missing
fourcc codes.
Signed-off-by: Jeffrey Mouroux
Signed-off-by: Hyun Kwon
---
v2
- Add detailed
This adds packed YUV and grey scale format fourccs.
Signed-off-by: Hyun Kwon
---
v2
- Split from the previous patch
---
---
include/uapi/drm/drm_fourcc.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 6ac5282
In order to handle non byte aligned formats, use
drm_format_plane_width_bytes(). Use of 'cpp' can result in
incorrect number of bytes from bit level rounding.
Signed-off-by: Hyun Kwon
---
v2
- This patch is added.
---
---
drivers/gpu/drm/drm_fb_cma_helper.c | 3 ++-
1 file changed, 2
Signed-off-by: Hyun Kwon
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index fd6ddfe..b1aaa71 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers
Hi Daniel,
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> Vetter
> Sent: Wednesday, January 17, 2018 12:20 AM
> To: Hyun Kwon
> Cc: dri-devel@lists.freedesktop.org; devicet...@vger.kernel.org; Michal
> Simek ;
This driver creates DRM encoder and connector for ZynqMP DisplayPort.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v2
- Change the SPDX identifier format
- Split drm properties into a separate patch
---
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v4
- Use the newly added xlnx pipeline calls to initialize drm device
v2
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon
---
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for layers
- Update the example accordingly
v2
- Group multiple ports under 'ports'
- Replace linu
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
multiple subdevices and
to represent the entire pipeline as a single DRM device. The module
includes helper (ex, framebuffer and gem helpers) and
glue logic (ex, crtc interface) functions.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v4
- Fix a bug in of graph binding handling
- Remove vblank
Hi Rob,
Thanks for the review.
> -Original Message-
> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> Of Rob Herring
> Sent: Friday, January 19, 2018 4:31 PM
> To: Hyun Kwon
> Cc: devicet...@vger.kernel.org; Laurent Pinchart
> ; Micha
Hi Rob,
Thanks for the review.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Friday, January 19, 2018 3:33 PM
> To: Hyun Kwon
> Cc: dri-devel@lists.freedesktop.org; devicet...@vger.kernel.org; Michal
> Simek ; Daniel Vetter ;
> Laurent Pi
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon
---
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers/gpu/drm/xlnx/Makefile | 3 +
drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 149
This driver creates DRM encoder and connector for ZynqMP DisplayPort.
Signed-off-by: Hyun Kwon
---
v2
- Change the SPDX identifier format
- Split drm properties into a separate patch
---
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738 ++
drivers/gpu/drm/xlnx
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
Add drm properties for DisplayPort synchronous mode and bpc
configurations.
Signed-off-by: Hyun Kwon
---
v2
- Split from the original patch
---
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 116 ++-
1 file changed, 114 insertions(+), 2 deletions(-)
diff --git a
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