When the power domains cannot be parsed, the message is incorrectly
logged as an info message. Let's change this to an error since an error
is returned.
Fixes: 92a511a568e4 ("fbdev/simplefb: Add support for generic power-domains")
Signed-off-by: Brian Masney
---
drivers/video/f
Hi Juerg,
On Fri, Jun 16, 2023 at 02:28:15PM +0200, Juerg Haefliger wrote:
> Add missing MODULE_FIRMWARE macros and remove some for firmwares that
> the driver no longer references.
>
> Signed-off-by: Juerg Haefliger
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 23 ++
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: dri-devel@lists.freedesktop.org
> Cc: Dave Airlie
> Cc: Thierry Reding
This patch fixes the build error that I see with qcom_defconfig in
linux-next.
Tested-by: Brian Masney
upport")
> Cc: Brian Masney
> Cc: Dan Murphy
> Signed-off-by: Andy Shevchenko
Reviewed-by: Brian Masney
Rob Clark
> Fixes: 2d99ced787e3d ("drm/msm: async commit support")
Nice job tracking down this fix!
Reviewed-by: Brian Masney
Tested-by: Brian Masney
___
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On Wed, Dec 30, 2020 at 05:29:42PM +0200, Iskren Chernev wrote:
> From: Craig Tatlor
>
> vram.size is needed when binding a gpu without an iommu and is defined
> in msm_init_vram(), so run that before binding it.
>
> Signed-off-by: Craig Tatlor
For the series:
Reviewe
es to child nodes and should
> be moved up to the parent node.
>
> Fixes: 957fd69d396b ("dt-bindings: soc: qcom: add On Chip MEMory (OCMEM)
> bindings")
> Cc: Brian Masney
> Cc: Bjorn Andersson
> Cc: linux-arm-...@vg
On Sun, Mar 15, 2020 at 02:43:55PM +0100, Sam Ravnborg wrote:
> Add the lg panels that matches the panel-simple binding to
> panel-simple.yaml
>
> Signed-off-by: Sam Ravnborg
> Cc: Alexandre Courbot
> Cc: Brian Masney
> Cc: Thierry Reding
> Cc: Sam Ravnborg
R
. The a3xx/a4xx example in the GPU is replaced with what was
in the GMU.
Signed-off-by: Brian Masney
Fixes: 198a72c8f9ee ("dt-bindings: display: msm: gmu: add optional ocmem
property")
---
Background thread:
https://lore.kernel.org/lkml/20200303170159.ga13...@jcrouse1-lnx.qualcomm.com/
98 clock rate on the panel
$ modetest -v -s 32:1080x19
freq: 55.44Hz
freq: 55.09Hz
freq: 55.88Hz
...
Brian
>
> (FYI glmark-x11 isn't vsynced which is why I specifically mentioned
> glmark-drm)
>
> On 3/3/20 9:16 PM, Brian Masney wrote:
> > On Tue, Mar 03, 2020 at 08:04:0
it force-enabled) since the
> results are all 26-27 (X works a bit differently and gets double the
> framerate somehow?)
>
> On 3/3/20 9:53 PM, Brian Masney wrote:
> > On Tue, Mar 03, 2020 at 09:27:50PM -0500, Jonathan Marek wrote:
> > > modetest should be printing &q
.462 ms
[desktop] blur-radius=5:effect=blur:passes=1:separable=true:windows=4:
FPS: 26 FrameTime: 38.462 ms
[desktop] effect=shadow:windows=4: FPS: 27 FrameTime: 37.037 ms
...
Brian
>
> On 3/3/20 7:26 AM, Brian Masney wrote:
> > On Mon, Mar 02, 2020 at 10:36:54PM -0500, Jonathan Marek wrot
x27;s patch going in.
Brian
>
> On 3/2/20 10:28 PM, Jonathan Marek wrote:
> >
> > On 3/2/20 10:13 PM, Brian Masney wrote:
> > > On Mon, Mar 02, 2020 at 03:48:22PM -0500, Jonathan Marek wrote:
> > > > Hi,
> > > >
> > > > This is a c
On Tue, Mar 03, 2020 at 08:50:28AM -0700, Jeffrey Hugo wrote:
> On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse wrote:
> >
> > On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote:
> > > Hi Jordan.
> > >
> > > On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote:
> > > > Convert disp
see if that
affects the speed.
I'm still ok with Ville's patch going in given the existing slow state.
There's no clear path forward right now for the autocommit patch that I
linked to earlier in this thread. :(
Brian
>
> On 3/3/20 9:16 PM, Brian Masney wrote:
> > O
On Tue, Mar 03, 2020 at 10:01:59AM -0700, Jordan Crouse wrote:
> On Tue, Mar 03, 2020 at 10:54:05AM -0500, Brian Masney wrote:
> > On Tue, Mar 03, 2020 at 08:50:28AM -0700, Jeffrey Hugo wrote:
> > > On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse
> > > wrote:
> > &g
X11
and everything appears to be working fine. You can add my Tested-by if
you end up applying this.
Tested-by: Brian Masney
Brian
> On 3/2/20 3:34 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The currently listed dotclock disagrees with the currently
>
Add rate limiting of the 'pp done time out' warnings since these
warnings can quickly fill the dmesg buffer.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm
On Tue, Dec 31, 2019 at 10:50:27PM -0500, Brian Masney wrote:
> On Sun, Dec 29, 2019 at 09:00:53PM -0500, Brian Masney wrote:
> > Since the introduction of commit 2d99ced787e3 ("drm/msm: async commit
> > support"), command-mode panels began throwing the following errors:
rdware has a
suggestion for something to try.
Signed-off-by: Brian Masney
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 44 +
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 4b161b809dd5..2515a3bd
On Sun, Dec 29, 2019 at 09:00:53PM -0500, Brian Masney wrote:
> Since the introduction of commit 2d99ced787e3 ("drm/msm: async commit
> support"), command-mode panels began throwing the following errors:
>
> msm fd90.mdss: pp done time out, lm=0
>
> Le
e to
implement async commit support for the MDP5 in a follow up patch.
Signed-off-by: Brian Masney
Suggested-by: Jeffrey Hugo
Fixes: 2d99ced787e3 ("drm/msm: async commit support")
---
Changes since v1:
- Send a single start command to kick off the pipeline.
The reason I marked this patc
e to
implement async commit support for the MDP5 in a follow up patch.
Signed-off-by: Brian Masney
Suggested-by: Jeffrey Hugo
Fixes: 2d99ced787e3 ("drm/msm: async commit support")
---
Changes since v1:
- Send a single start command to kick off the pipeline.
The reason I marked this patc
Hi Jeffrey,
On Tue, Dec 03, 2019 at 07:18:31AM -0700, Jeffrey Hugo wrote:
> On Mon, Dec 2, 2019 at 6:40 PM Brian Masney wrote:
> > On Wed, Nov 13, 2019 at 06:23:34AM -0500, Brian Masney wrote:
> > > On Tue, Nov 12, 2019 at 08:38:27AM -0700, Jeffrey Hugo wrote:
> > >
Hi Jeffrey,
On Wed, Nov 13, 2019 at 06:23:34AM -0500, Brian Masney wrote:
> On Tue, Nov 12, 2019 at 08:38:27AM -0700, Jeffrey Hugo wrote:
> > On Tue, Nov 12, 2019 at 3:49 AM Brian Masney wrote:
> > >
> > > Since the introduction of commit 2d99ced787e3 ("drm
there's now two available interconnects, let's add the
interconnect-names property.
Signed-off-by: Brian Masney
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm
Set the two interconnect paths for the GPU to maximum speed for now to
work towards getting the GPU working upstream. We can revisit a later
time to optimize this for battery life.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 8
1 file changed, 8 insertions
nnect paths to the highest speed for a3xx and a4xx-based
platforms.
Changes since v1:
- Don't rename icc_path to gfx_mem_icc_path. Leave existing variable
named as is and add comment to declaration in struct msm_gpu.
Brian Masney (4):
dt-bindings: drm/msm/gpu: document second interconnect
, the two interconnect paths for the
GPU are between:
- MSM_BUS_MASTER_GRAPHICS_3D and MSM_BUS_SLAVE_EBI_CH0
- MSM_BUS_MASTER_V_OCMEM_GFX3D and MSM_BUS_SLAVE_OCMEM
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +-
drivers/gpu/drm/msm/msm_
Set the two interconnect paths for the GPU to maximum speed for now to
work towards getting the GPU working upstream. We can revisit a later
time to optimize this for battery life.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 8
1 file changed, 8 insertions
Set the two interconnect paths for the GPU to maximum speed for now to
work towards getting the GPU working upstream. We can revisit a later
time to optimize this for battery life.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 8
1 file changed, 8 insertions
Set the two interconnect paths for the GPU to maximum speed for now to
work towards getting the GPU working upstream. We can revisit a later
time to optimize this for battery life.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 8
1 file changed, 8 insertions
nnect paths to the highest speed for a3xx and a4xx-based
platforms.
Brian Masney (4):
dt-bindings: drm/msm/gpu: document second interconnect
drm/msm/gpu: add support for ocmem interconnect path
drm/msm/a3xx: set interconnect bandwidth vote
drm/msm/a4xx: set interconnect bandwidth
, the two interconnect paths for the
GPU are between:
- MSM_BUS_MASTER_GRAPHICS_3D and MSM_BUS_SLAVE_EBI_CH0
- MSM_BUS_MASTER_V_OCMEM_GFX3D and MSM_BUS_SLAVE_OCMEM
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +++---
drivers/gpu/drm/msm/adreno/adreno_gpu.c
Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
and must use the On Chip MEMory (OCMEM) in order to be functional.
There's a separate interconnect path that needs to be setup to OCMEM.
Let's document this second interconnect path that's available.
Signe
On Tue, Nov 12, 2019 at 08:38:27AM -0700, Jeffrey Hugo wrote:
> On Tue, Nov 12, 2019 at 3:49 AM Brian Masney wrote:
> >
> > Since the introduction of commit 2d99ced787e3 ("drm/msm: async commit
> > support"), command-mode panels began throwing the following errors
s that
we can use to implement async commit support for the MDP5 in a follow up
patch.
Signed-off-by: Brian Masney
Suggested-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 15 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c | 9 +
2 files changed, 15 insertions(+),
On Mon, Nov 11, 2019 at 07:51:22AM -0700, Jeffrey Hugo wrote:
> On Mon, Nov 11, 2019 at 4:38 AM Brian Masney wrote:
> >
> > On Sun, Nov 10, 2019 at 10:37:33AM -0700, Jeffrey Hugo wrote:
> > > On Sun, Nov 10, 2019 at 6:53 AM Brian Masney
> > > wrote:
> > &g
On Sun, Nov 10, 2019 at 10:37:33AM -0700, Jeffrey Hugo wrote:
> On Sun, Nov 10, 2019 at 6:53 AM Brian Masney wrote:
> >
> > On Fri, Nov 08, 2019 at 07:56:25AM -0700, Jeffrey Hugo wrote:
> > There's a REG_MDP5_PP_AUTOREFRESH_CONFIG() macro upstream here:
> > http
On Fri, Nov 08, 2019 at 07:56:25AM -0700, Jeffrey Hugo wrote:
> On Thu, Nov 7, 2019 at 7:03 PM Rob Clark wrote:
> >
> > On Thu, Nov 7, 2019 at 9:40 AM Jeffrey Hugo
> > wrote:
> > >
> > > On Thu, Nov 7, 2019 at 9:17 AM Rob Clark wrote:
> > > >
On Wed, Nov 06, 2019 at 08:58:59AM -0800, Rob Clark wrote:
> On Wed, Nov 6, 2019 at 8:47 AM Jeffrey Hugo wrote:
> >
> > On Wed, Nov 6, 2019 at 9:30 AM Rob Clark wrote:
> > >
> > > On Wed, Nov 6, 2019 at 1:13 AM Brian Masney wrote:
> > > >
> >
On Tue, Nov 05, 2019 at 08:23:27AM -0800, Rob Clark wrote:
> On Tue, Nov 5, 2019 at 2:08 AM Brian Masney wrote:
> > The 'pp done time out' errors go away if I revert the following three
> > commits:
> >
> > cd6d923167b1 ("drm/msm/dpu: async commit suppor
Hey Rob,
Since commit 2d99ced787e3 ("drm/msm: async commit support"), the frame
buffer console on my Nexus 5 began throwing these errors:
msm fd90.mdss: pp done time out, lm=0
The display still works.
I see that mdp5_flush_commit() was introduced in commit 9f6b65642bd2
("drm/msm: add kms->f
On Mon, Nov 04, 2019 at 04:19:07PM -0800, Rob Clark wrote:
> On Mon, Nov 4, 2019 at 4:01 PM Brian Masney wrote:
> >
> > Hey Rob,
> >
> > Since commit 2d99ced787e3 ("drm/msm: async commit support"), the frame
> > buffer console on my Nexus 5 began throw
On Wed, Oct 09, 2019 at 08:39:26AM -0700, Stephen Boyd wrote:
> Quoting Brian Masney (2019-10-08 23:05:20)
> > On Tue, Oct 08, 2019 at 07:21:30PM -0700, Stephen Boyd wrote:
> > > Quoting Brian Masney (2019-10-06 18:45:08)
> > > > diff --git a/arch/arm/boot/dts/qcom-ms
On Tue, Oct 08, 2019 at 07:21:30PM -0700, Stephen Boyd wrote:
> Quoting Brian Masney (2019-10-06 18:45:08)
> > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
> > b/arch/arm/boot/dts/qcom-msm8974.dtsi
> > index 7fc23e422cc5..af02eace14e2 100644
> > --- a/arch/arm
s requires
the following patch I sent out on 2019-09-22 to analogix-anx78xx that
corrects an i2c address:
https://lore.kernel.org/lkml/20190922175940.5311-1-masn...@onstation.org/
Brian Masney (5):
drm/bridge: analogix-anx78xx: add support for avdd33 regulator
drm/msm/hdmi: add msm8974 PLL su
Add HDMI tx and phy nodes to support an external display that can be
connected over the SlimPort. This is based on work from Jonathan Marek.
Signed-off-by: Brian Masney
Reviewed-by: Linus Walleij
---
Changes since v1:
- Add hdmi_pll to hdmi-phy node
- add power-domain to hdmi-phy per binding
til I get the external
display fully working on the Nexus 5 and then I can submit proper
support then that powers down this regulator in the power off function.
Signed-off-by: Brian Masney
---
Changes since v1:
- None
drivers/gpu/drm/bridge/analogix-anx78xx.c | 33 +++
1
Add msm8974 Phase-Locked Loop (PLL) support to the MSM HDMI so that an
external display can be used on this SoC.
Signed-off-by: Brian Masney
---
Changes since v1:
- New patch introduced in v2
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h | 6
ff-by: Brian Masney
Reviewed-by: Linus Walleij
---
Changes since v1:
- None
arch/arm/boot/dts/qcom-pm8941.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi
b/arch/arm/boot/dts/qcom-pm8941.dtsi
index f198480c8ef4..c1f2012d1c8b 100644
--- a
Add HDMI nodes and other supporting infrastructure in order to support
the external display. This is based on work from Jonathan Marek.
Signed-off-by: Brian Masney
Reviewed-by: Linus Walleij
---
Changes since v1:
- Regulators always on as a temporary haack.
- Hot plug detect pin for the HDMI
are fixed based on the model, and pass the i2c addresses to the driver
via the data pointer in the driver's of_match_table.
Signed-off-by: Brian Masney
Reviewed-by: Laurent Pinchart
---
Changes since v2:
- Change comments in analogix-anx78xx.h from using the address to the
name
drivers
On Fri, Sep 20, 2019 at 01:49:45PM +0300, Laurent Pinchart wrote:
> Hi Brian,
>
> Thank you for the patch.
>
> On Fri, Sep 20, 2019 at 06:14:38AM -0400, Brian Masney wrote:
> > According to the downstream Android sources, the anx7808 variants use
> > address 0x7
are fixed based on the model, and pass the i2c addresses to the data
pointer in the driver's of_match_table.
Signed-off-by: Brian Masney
---
V1 of this patch with some discussion:
https://lore.kernel.org/lkml/20190815004854.19860-6-masn...@onstation.org/
drivers/gpu/drm/bridge/analogix
On Mon, Sep 16, 2019 at 12:02:09PM +0200, Andrzej Hajda wrote:
> On 15.08.2019 02:48, Brian Masney wrote:
> > When attempting to configure this driver on a Nexus 5 phone (msm8974),
> > setting up the dummy i2c bus for TX_P0 would fail due to an -EBUSY
> > error. The downstre
On Mon, Sep 16, 2019 at 01:32:58PM +0200, Enric Balletbo i Serra wrote:
> Hi,
>
> On 16/9/19 12:49, Laurent Pinchart wrote:
> > Hi Brian,
> >
> > On Mon, Sep 16, 2019 at 06:36:14AM -0400, Brian Masney wrote:
> >> On Mon, Sep 16, 2019 at 12:02:09PM +0200, Andr
On Mon, Sep 16, 2019 at 12:36:19PM +0200, Enric Balletbo i Serra wrote:
> Hi Andrzej and Brian
>
> On 16/9/19 12:02, Andrzej Hajda wrote:
> > On 15.08.2019 02:48, Brian Masney wrote:
> >> When attempting to configure this driver on a Nexus 5 phone (msm8974),
> >>
Hi Andrzej,
On Mon, Sep 16, 2019 at 10:13:58AM +0200, Andrzej Hajda wrote:
> Hi Brian,
>
> On 15.08.2019 02:48, Brian Masney wrote:
> > This patch series begins to add support for the external display over
> > HDMI that is supported on msm8974 SoCs. I'm testing this
Hi Rob C / Sean P,
On Fri, Aug 23, 2019 at 05:16:30AM -0700, Brian Masney wrote:
> This patch series adds support for Qualcomm's On Chip MEMory (OCMEM)
> that is needed in order to support some a3xx and a4xx-based GPUs
> upstream. This is based on Rob Clark's patch series tha
-by: Brian Masney
Reviewed-by: Bjorn Andersson
---
Changes since v6:
- None
Changes since v5:
- None
Changes since v4:
- None
Changes since v3:
- None
Changes since v2:
- None
Changes since v1:
- Use existing __qcom_scm_restore_sec_cfg() function stub in
qcom_scm-32.c that was unimplemented
Add ocmem driver that's needed for some a3xx and a4xx based systems.
Signed-off-by: Brian Masney
---
Changes since v6:
- None
Changes since v5:
- None
This patch was introduced in v5.
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/co
From: Rob Clark
Add support for the OCMEM lock/unlock interface that is needed by the
On Chip MEMory (OCMEM) that is present on some Snapdragon devices.
Signed-off-by: Rob Clark
[masn...@onstation.org: ported to latest kernel; minor reformatting.]
Signed-off-by: Brian Masney
Reviewed-by
The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
and adreno_gpu_ocmem_cleanup) that removes some duplicated code.
Signed-off-by: Brian Masney
---
Changes since v6:
- None
Changes since v5:
- None
v6:
- link to gmu-sram child node in device tree
- add ranges property to ocmem example in adreno GMU example (patch 2)
to match bindings in patch 1
See individual patches for changelogs for previous versions.
Brian Masney (5):
dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings
d
Add device tree bindings for the On Chip Memory (OCMEM) that is present
on some Qualcomm Snapdragon SoCs.
Signed-off-by: Brian Masney
Reviewed-by: Rob Herring
---
Changes since v6:
- None
Changes since v5:
- None
Changes since v4:
- remove qcom from path in $id
Changes since v3:
- add ranges
Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
must use the On Chip MEMory (OCMEM) in order to be functional. Add the
optional ocmem property to the Adreno Graphics Management Unit bindings.
Signed-off-by: Brian Masney
---
Changes since v6:
- link to gmu-sram in example
ed to zero to match what the hardware
expects. The driver can be updated to read the reserved memory regions
from device tree once other users of OCMEM are added upstream.
Signed-off-by: Brian Masney
Co-developed-by: Rob Clark
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
Change
Add device tree bindings for the On Chip Memory (OCMEM) that is present
on some Qualcomm Snapdragon SoCs.
Signed-off-by: Brian Masney
Reviewed-by: Rob Herring
---
Changes since v5:
- None
Changes since v4:
- remove qcom from path in $id
Changes since v3:
- add ranges property
- remove
ed to zero to match what the hardware
expects. The driver can be updated to read the reserved memory regions
from device tree once other users of OCMEM are added upstream.
Signed-off-by: Brian Masney
Co-developed-by: Rob Clark
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
Change
The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
and adreno_gpu_ocmem_cleanup) that removes some duplicated code.
Signed-off-by: Brian Masney
---
Changes since v5:
- None
Changes since v4:
- None
Add ocmem driver that's needed for some a3xx and a4xx based systems.
Signed-off-by: Brian Masney
---
Changes since v5:
- None
This patch was introduced in v5.
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/co
-by: Brian Masney
---
Changes since v5:
- None
Changes since v4:
- None
Changes since v3:
- None
Changes since v2:
- None
Changes since v1:
- Use existing __qcom_scm_restore_sec_cfg() function stub in
qcom_scm-32.c that was unimplemented
- Set the cfg.ctx_bank_num to the spare function
Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
must use the On Chip MEMory (OCMEM) in order to be functional. Add the
optional ocmem property to the Adreno Graphics Management Unit bindings.
Signed-off-by: Brian Masney
---
Changes since v5:
- rename ocmem property to
From: Rob Clark
Add support for the OCMEM lock/unlock interface that is needed by the
On Chip MEMory (OCMEM) that is present on some Snapdragon devices.
Signed-off-by: Rob Clark
[masn...@onstation.org: ported to latest kernel; minor reformatting.]
Signed-off-by: Brian Masney
Reviewed-by
:
- Rename ocmem device tree property to sram
See individual patches for changelogs for previous versions.
Brian Masney (5):
dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings
dt-bindings: display: msm: gmu: add optional ocmem property
soc: qcom: add OCMEM driver
drm/msm/gpu: add
On Wed, Aug 21, 2019 at 02:26:02PM -0500, Rob Herring wrote:
> On Mon, Aug 05, 2019 at 08:22:24PM -0400, Brian Masney wrote:
> > Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
> > must use the On Chip MEMory (OCMEM) in order to be functional. Add the
>
On Thu, Aug 15, 2019 at 10:22:45AM +0200, Linus Walleij wrote:
> On Thu, Aug 15, 2019 at 2:49 AM Brian Masney wrote:
>
> > Add support for the avdd33 regulator to the analogix-anx78xx driver.
> > Note that the regulator is currently enabled during driver probe and
> > dis
On Thu, Aug 15, 2019 at 10:34:17AM +0200, Linus Walleij wrote:
> On Thu, Aug 15, 2019 at 2:49 AM Brian Masney wrote:
>
> > pm8941 is missing the 5vs2 regulator node so let's add it since its
> > needed to get the external display working. This regulator was alread
Walleij
For the series:
Reviewed-by: Brian Masney
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ff-by: Brian Masney
---
arch/arm/boot/dts/qcom-pm8941.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi
b/arch/arm/boot/dts/qcom-pm8941.dtsi
index f198480c8ef4..c1f2012d1c8b 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boo
Silence a warning message due to an -EPROBE_DEFER error to help cleanup
the system boot log.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy.c
b/drivers/gpu/drm/msm
Add CONFIG_DRM_ANALOGIX_ANX78XX as a module so that the external display
can be used on the Nexus 5 phones.
Signed-off-by: Brian Masney
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index
til I get the external
display fully working on the Nexus 5 and then I can submit proper
support then that powers down this regulator in the power off function.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 33 +++
1 file changed, 33 insertions(+)
Silence two warning messages that occur due to -EPROBE_DEFER errors to
help cleanup the system boot log.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix
Add HDMI tx and phy nodes to support an external display that can be
connected over the SlimPort. This is based on work from Jonathan Marek.
Signed-off-by: Brian Masney
---
The hdmi-tx node in the downstream MSM sources:
https://github.com/AICP/kernel_lge_hammerhead/blob/n7.1/arch/arm/boot/dts
Add support for the 7808 variant. While we're here, the of match table
was missing support for the 7812 and 7818 variants, so add them as well.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gp
Add HDMI nodes and other supporting infrastructure in order to support
the external display. This is based on work from Jonathan Marek.
Signed-off-by: Brian Masney
---
The hdmi-tx node in the downstream MSM sources:
https://github.com/AICP/kernel_lge_hammerhead/blob/n7.1/arch/arm/boot/dts
.
[1]
https://github.com/AICP/kernel_lge_hammerhead/blob/n7.1/drivers/video/slimport/slimport_tx_reg.h
Signed-off-by: Brian Masney
---
drivers/gpu/drm/bridge/analogix-anx78xx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.h
b/drivers
that aren't ready with 'PATCH RFC'.
I'm using an Analogix Semiconductor SP6001 SlimPort Micro-USB to 4K HDMI
Adapter to connect my phone to an external display via a standard HDMI
cable. This works just fine with the downstream MSM kernel using
Android.
Brian Masney (11):
Add support for the analogix,anx7808, analogix,anx7812, and
analogix,anx7818 variants.
Signed-off-by: Brian Masney
---
.../devicetree/bindings/display/bridge/anx7814.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display
The i2c_new_dummy() function is deprecated since it returns NULL on
error. Change this to use the recommended replacement
i2c_new_dummy_device() that returns an error code that can be read with
PTR_ERR() and friends.
Signed-off-by: Brian Masney
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 15
-by: Brian Masney
---
Changes since v4:
- None
Changes since v3:
- None
Changes since v2:
- None
Changes since v1:
- Use existing __qcom_scm_restore_sec_cfg() function stub in
qcom_scm-32.c that was unimplemented
- Set the cfg.ctx_bank_num to the spare function parameter. It was
previously
Add ocmem driver that's needed for some a3xx and a4xx based systems.
Signed-off-by: Brian Masney
---
This is a new patch that was introduced in v5.
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/co
individual patches for the changelog.
This was tested with the GPU on a LG Nexus 5 (hammerhead) phone and
this will work on other msm8974-based systems. For a summary of what
currently works upstream on the Nexus 5, see my status page at
https://masneyb.github.io/nexus-5-upstream/.
Brian Masney
Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
must use the On Chip MEMory (OCMEM) in order to be functional. Add the
optional ocmem property to the Adreno Graphics Management Unit bindings.
Signed-off-by: Brian Masney
---
Changes since v4:
- None
Changes since v3
The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
and adreno_gpu_ocmem_cleanup) that removes some duplicated code.
Signed-off-by: Brian Masney
---
Changes since v4:
- None
Changes since v3:
- None
Add device tree bindings for the On Chip Memory (OCMEM) that is present
on some Qualcomm Snapdragon SoCs.
Signed-off-by: Brian Masney
Reviewed-by: Rob Herring
---
Changes since v4:
- remove qcom from path in $id
Changes since v3:
- add ranges property
- remove unnecessary literal block |
- add
ed to zero to match what the hardware
expects. The driver can be updated to read the reserved memory regions
from device tree once other users of OCMEM are added upstream.
Signed-off-by: Brian Masney
Co-developed-by: Rob Clark
Signed-off-by: Rob Clark
Reviewed-by: Bjorn Andersson
---
Change
From: Rob Clark
Add support for the OCMEM lock/unlock interface that is needed by the
On Chip MEMory (OCMEM) that is present on some Snapdragon devices.
Signed-off-by: Rob Clark
[masn...@onstation.org: ported to latest kernel; minor reformatting.]
Signed-off-by: Brian Masney
Reviewed-by
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